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Step-byStep Flyback SMPS Design
y prasunkuls.
Abstract
Prasun kulshrestha, Sr. Design Engineer Hardware, Intellect Systeme (I) Pvt Ltd., Nagpur,
INDIA.
Abstract: The approach of this article is to develop a sequential approach of practically
esigning the SMPS design Which are examined by me for years practically. The aim's to
look on ground levels to clear fundamentals inteligence regarding SMPS. Thad never seen
Easy & step- by-step calculations to ideally decide the nature of SMPS. The Step-by-step
caleuations ilustrated in ths article wil help you to actually see the practical result on
paper before performing t practically. This alo include the expertise tins wherever tis
Sesired for elther caution or for intelligence.
Moreover, when you will make the actual schematic using these calculations, you will just
eee a perfect guidance for implementing correct component data book. Twas also looking
‘to include the probable components that could be referred but finaly I amnot including fn
‘his.
Universal Block Diagram
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Prater
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: Flee Wish Sac
Sims Je Ea os
Fig: Pras:
Introduction
Designing the system step-by step could be realized below. Moreover the block diagram
‘above is a self-explanatory Universal block diagram of SMPS.
Thad enlisted the Sequential formulas below which wil clear the insight towards SMPS.
[A Step by step Designing Formulas:
IC No information is available , just assume Ef
75 for low output applications & 0.85 for
high voltage applications.
1. Maximum input power:
Pin =Po/ Et
Put Eff = as discussed above.
2. Load occupying factor:
iNow, if we have fo take multiple outputs from smps,the load occupying factor ( KLn) must
bee found as-
Kan=Po(n/Po
Here, Po(n) is the rraximum output power for nth output.
Usually, If single output fromsmps is desired, key rule is to consider KL = 13. Input capacttor Selection:
It is algo known as OC lnk capackor.
‘The unwversal approach shouldbe to fist recognize the few parameters as
Vac max; Vac min ; switching frequency ; line frequency & output power;
This would clear the nature of quality of an Ideal SMPS you are looking at,
‘The key rule to decige the value of Dc link capacitor as 2-3 micro farac per watt of input
range ( 85-265vims) & 1 micro ferad per watt of Input power of European range ( 195v
2esvers)
Aso, take my experience suggestion to use DC ink capacitor more than 2 micro farad per
‘watt of input range so as to get better quality of DC output.
Also, for 230 v mains line, select the capacitor of min 400 v rating, It is because that we
‘may use fectifier device which may multiply the input with the factor of 1.41
3, Min DC tink voltage:
Ve min = sprt( 2* ( v tne min )42-Pin ( 1-Deh / Cac. FI)
Where ,
Deh- a¢ link capacitor charging duty ratio.
Deh is 0.2 to 0.25
Deh = 1 /t2
4, Maximum de lk voltage
Vide max = sqrt (2 )* V line max
5, maximum DC link ripple voltage:
Change in Vde max = sart (2) * Vin rin ~ V de erin
While calculating this factor, care should be taken as accuracy of this factor affects the
systema lot.
6, output reflected voltage:
Vro = Drax® vde min / (1- Drax)
7. Maximum MOSFET voltage
Vds nom = Vde max 4Vro
Where Ve min & Vde max is already calculated in step 3.84,
Practical approach key rule:
For step 6&7;
I we decrease the value of Drax, the voltage stress over MOSFET can be reduced suitably
But this willin tum increase the voltage stress over rectifier diode in the secondary sie. Se
Twould suggest with my experience to Select Dmax as large as possible ifthe voltage rating
of MOSFET allows,
8, Designing The Inductance of the transformer primary side Lm
Lins (Vee min * Omax)square / (2 Pin * Fs * Kit)
Where Lm- primary incuctance
F s- switching Frequency
Kif- riage factor in full ad & min input voltage.
Key nut
For discontinuous mode , set kef =1
For continuous mode, set kef <1
IF you are making flyback converter to be operated in CCM mode, just prefer to set kr
between 0.25 ~ 0.5 for universal input range & kif = 0.4 ~ 0.8 for European input range.
9. Tds peak
ede + ( Change in current / 2)
10, Ids rvs = sqrt((3* (Lede)square + ( change incurrent / 2 )square)Dmax / 3)
LL where Jede = Pin / (Ve min * Drax)
12, Also, change in current = Vae min * D max / (Lav Fs)
13, Vode in cem mode = [1/(sart(2*Lm*tS*Pin))-1/Vro]*(-1)
Key rule:
If the result of equation 13 is in negative value, the converter is always In CCM uncer full
load condition regardless of the input voltage variation
14. Np (min) =[ Lint lim * 10°(6) / ( Bsat * Ae)] (tums)
Where lim - pulse by pulse current limit level
Ae = cross section area of the core
Beat = saturation flux density in teslaKey rule: if no information is avalable regarding Bsat,for generalized smps, set Bsat betwee:
0.3 to 0.35 tesla
15. Transformer Gesion
Np/Ns1] =[Vrd/ ( VOuAVEE )]
Where No- number of tums of primary side
Nel- number of tums of reference output
vo1 ~ output voltage
VFI - Diode forward vokage drop of the reference output
Key suggestion:
Now, determine the proper integer number for NS so that resulting Np Is larger than Np min
Obtained from step 14,
16. The number of tums for the other output , nth output, is determined as:
Ns (n) = [VO (n) + F(a) Ns1] / [VOL +¥F2 J turns
17. The number of turns for VOe winding is determined as
Na'= [Vee + Vea /( VOL + VFL) ]* Nei tums
Where Vec ~ norrinal voltage for Vec.
far Diode forward voltage drop.
18, with deterring tums of the primary side, the gap length of the core is obtained as
G40" 3.14 * Ae [ {Np*(2)/ 1000Lm}- 1/8] units in ram
Where Ak Al value with no gap in nki/turns (2)
Ae = Cross section area of the core,
Np =o. of tums for prirary side of the transformer.
19: The RMS current of the nth secondary winding is obtained as
sec (n)ms = 1 65 rms sqrt [ (1-Dmax/Drax)] * vio * Kin / (Von + VEn >
Where Von ~ output voltage of nth output
V tn = diode forward volage drop
Kin ~ load occupying factor for nth output cefined in equation 2.
Key information:
‘The current density ie SA / mm2 when the wire is long (> Im). when the wire is short with ¢
small number of turns , a current density of 6-10 A/mm is also acceptable.
Avoid using wire with & diameter larger than Lim to avoid severe eddy current losses as
Wwell as to make winding easier
For high current output, It is better to use parallel winding with multiple strands of thinner
Wire to minimize skin effect.
19. The required winding window area is given by
Aw = Ae KE
Where Ac - actual conductor area
Kf = Fill factor
Key to
Usually, fill factor sin between 0.2 to 0.25 for single output application,
For, mukiple output, ic Is in between 0.15 to 0.2.
20. The maxirum voltage & the rms current of the rectifier dlode of the nth output are
obtained os
Ve = Von + Vde max [ Von + fn }/ Veo
2A: dn rms = Ids ems sqrt (1+ Drax /Omax ) * Vro * in/ ( Von + Vin }
where von ~ output voltage of nth output
Vin- diode forward drop.
22. The typical voltage & current margins for rectifier diode are as follows:
Vien > 1.3 * Ven
23.1f > 1.5 * Len rms
where ,
for eauation 23 & 23.