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ProcessorSimulator
ProcessorSimulator(char*); // Load program from file
int runSim();

CPU
CPU(BIU*);
Word getFlags();
void setFlags(Word);
Content readReg(registerName);
void writeReg(registerName, Content&);

BIU

Bus

Memory
Memory(char *);

BIU(Bus*);

Bus(Memory*);

Instruction* fetchInstruction(Address);

Instruction* fetchInstruction(Address);

void storeInstruction(Address, Instruction*);

void storeInstruction(Address, Instruction*);

Byte fetchDataByte(Address);

Byte fetchDataByte(Address);

void storeDataByte(Address, Byte);

void storeDataByte(Address, Byte);

Instruction* decodeInstruction(Address);
Instruction* readInstruction(Address);
void writeInstruction(Address, Instruction*);
Byte readDataByte(Address);
void writeDataByte(Address, Byte);

Word fetchDataWord(Address);
Instruction* fetchInstruction(Address);

void storeDataWord(Address, Word);

void storeInstruction(Address, Instruction*);


Byte fetchDataByte(Address);
void storeDataByte(Address, Byte);
Word fetchDataWord(Address);
void storeDataWord(Address, Word);
int go(); //Start fetch and execute cycle

Register<Content>
Content read();
void Write(Content);

Address

Word

Byte

Operand

Instruction

virtual Word read(CPU&) = 0;


virtual void write(CPU&, Word) throw(ErrorMsg) = 0;
virtual Address getEffectiveAddress(CPU&);
throw(ErrorMsg) = 0; Byte getSize();

Instruction();
virtual void execute(CPU&)
throw(Halt, ErrorMsg) = 0; Byte getLength();
void setLength(Byte);

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ProcessorSimulator

Proc8088Simulator

ProcessorSimulator(char*); // Load program from file

Proc8088Simulator(char*); // Load program from file

int runSim();

CPU

BIU

Bus

Memory

CPU(BIU*);

BIU(Bus*);

Bus(Memory*);

Word getFlags();
void setFlags(Word);

Instruction* fetchInstruction(Address);

Instruction* fetchInstruction(Address);

void storeInstruction(Address, Instruction*);

void storeInstruction(Address, Instruction*);

Content readReg(registerName);
void writeReg(registerName, Content&);

Memory(char *);
Instruction* decodeInstruction(Address);
Instruction* readInstruction(Address);
void writeInstruction(Address, Instruction*);
Byte readDataByte(Address);
void writeDataByte(Address, Byte);

Instruction* fetchInstruction(Address);
void storeInstruction(Address, Instruction*);
Byte fetchDataByte(Address);

BIU8Bit

void storeDataByte(Address, Byte);


Word fetchDataWord(Address);

BIU8Bit(Bus8Bit*);

void storeDataWord(Address, Word);

Byte fetchDataByte(Address);

int go(); //Start fetch and execute cycle

void storeDataByte(Address, Byte);


Word fetchDataWord(Address);

Bus8Bit
Bus8Bit(Memory*);

Byte fetchDataByte(Address);
void storeDataByte(Address, Byte);

void storeDataWord(Address, Word);

Register<Content>
Content read();

Address

void Write(Content);

Word

DataStore

Byte

Byte read(Address);
void write(Address, Byte);

CodeStore
Instruction* read(Address);
void write(Address, Instruction*);

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CodeStore
Instruction* read(Address);
void write(Address, Instruction*);

Instruction
Instruction();
virtual void execute(CPU&) throw(Halt, ErrorMsg) = 0;
Byte getLength();
void setLength(Byte);

ZeroOpInst

OneOpInst

TwoOpInst

ZeroOpInst();

OneOpInst(Operand *);

TwoOpInst(Operand *, Operand *);

virtual void execute(CPU&) throw(Halt, ErrorMsg) = 0;

virtual void execute(CPU&) throw(Halt, ErrorMsg) = 0;

virtual void execute(CPU&) throw(Halt, ErrorMsg) = 0;

...

...

Ret
Ret();
void execute(CPU&) throw(Halt,ErrorMsg);

...

Jmp

Add

Jmp(Operand *);
void execute(CPU&) throw(Halt,ErrorMsg);

Add(Operand *, Operand *);


void execute(CPU&) throw(Halt,ErrorMsg);

Operand
virtual Word read(CPU&) = 0;
virtual void write(CPU&, Word) throw(ErrorMsg) = 0;
virtual Address getEffectiveAddress(CPU&) throw(ErrorMsg) = 0;
Byte getSize();

MemOp

RegOp

ImmOp

MemOp(Memory *, Address, Byte&, Byte);

RegOp(Memory *, Address, Byte);

ImmOp(Memory *, Address, Byte, Byte);

Word read(CPU&);

RegOp(registerName);
Word read(CPU&);

ImmOp(Word);
Word read(CPU&);

void write(CPU&, Word) throw(ErrorMsg);


Address getEffectiveAddress(CPU&) throw(ErrorMsg);

void write(CPU&, Word) throw(ErrorMsg);


Address getEffectiveAddress(CPU&) throw(ErrorMsg);

void write(CPU&, Word) throw(ErrorMsg);


Address getEffectiveAddress(CPU&) throw(ErrorMsg);

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Cpu

Biu

Bus

Memory

CodeStore

IP

Inst

go();

read();
addr
fetchInstruction(addr);
fetchInstruction(addr);
readInstruction(addr);
read(addr);
Inst*

if Inst* == NULL?
decodeInstruction(addr);
forever
Inst*
Inst*
Inst*
Inst*
read();
addr
getLength();
len
write(addr+len);

execute(Cpu&);

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ADD

DestOperand

SourceOperand

Cpu

FLAGS

execute(Cpu&);
read(Cpu&);
destOp
read(Cpu&);
srcOp
getFlags();
read();
flags
flags
setFlags(newFlags);
write(newFlags);

write(CPU&, destOp+srcOp);

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ProcessorSimulator

Proc8088Simulator

ProcessorSimulator(char*); // Load program from file


int runSim();

Proc8088Simulator(char*); // Load program from file

Proc8086Simulator
Proc8086Simulator(char*); // Load program from file

CPU

BIU

CPU(BIU*);
Word getFlags();
void setFlags(Word);

Bus

Memory
Memory(char *);

BIU(Bus*);

Bus(Memory*);

Instruction* fetchInstruction(Address);

Instruction* fetchInstruction(Address);

void storeInstruction(Address, Instruction*);

void storeInstruction(Address, Instruction*);

Content readReg(registerName);
void writeReg(registerName, Content&);

Instruction* decodeInstruction(Address);
Instruction* readInstruction(Address);
void writeInstruction(Address, Instruction*);
Byte readDataByte(Address);
void writeDataByte(Address, Byte);

Instruction* fetchInstruction(Address);
void storeInstruction(Address, Instruction*);
Byte fetchDataByte(Address);

BIU8Bit

void storeDataByte(Address, Byte);


Word fetchDataWord(Address);

BIU8Bit(Bus8Bit*);

void storeDataWord(Address, Word);

Byte fetchDataByte(Address);

int go(); //Start fetch and execute cycle

void storeDataByte(Address, Byte);


Word fetchDataWord(Address);

Bus8Bit
Bus8Bit(Memory*);

Byte fetchDataByte(Address);
void storeDataByte(Address, Byte);

void storeDataWord(Address, Word);

Register<Content>

BIU16Bit

Content read();
void Write(Content);

Bus16Bit

BIU16Bit(Bus16Bit*);

Bus16Bit(Memory*);

Word fetchDataWord(Address);

Word fetchDataWord(Address);

void storeDataWord(Address, Word);

void storeDataWord(Address, Word);

Address

Word

DataStore
Byte

Byte read(Address);
void write(Address, Byte);

CodeStore
Instruction* read(Address);
void write(Address, Instruction*);

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Proc8088Simulator
Proc8088Simulator(char*); // Load program from file

ProcessorSimulator

Proc8086Simulator

ProcessorSimulator(char*); // Load program from file


int runSim();

Proc8086Simulator(char*); // Load program from file

DebuggingSimulator
DebuggingSimulator(char*); // Load program from file
void debug();

CPU

BIU

CPU(BIU*);
Word getFlags();
void setFlags(Word);

Bus

Memory
Memory(char *);

BIU(Bus*);

Bus(Memory*);

Instruction* fetchInstruction(Address);

Instruction* fetchInstruction(Address);

void storeInstruction(Address, Instruction*);

void storeInstruction(Address, Instruction*);

Content readReg(registerName);
void writeReg(registerName, Content&);

Instruction* decodeInstruction(Address);
Instruction* readInstruction(Address);
void writeInstruction(Address, Instruction*);
Byte readDataByte(Address);
void writeDataByte(Address, Byte);

Instruction* fetchInstruction(Address);
void storeInstruction(Address, Instruction*);
Byte fetchDataByte(Address);

BIU8Bit

void storeDataByte(Address, Byte);


Word fetchDataWord(Address);

BIU8Bit(Bus8Bit*);

void storeDataWord(Address, Word);

Byte fetchDataByte(Address);

int go(); //Start fetch and execute cycle

void storeDataByte(Address, Byte);


Word fetchDataWord(Address);

Bus8Bit
Bus8Bit(Memory*);

Byte fetchDataByte(Address);
void storeDataByte(Address, Byte);

void storeDataWord(Address, Word);

Register<Content>

BIU16Bit

Content read();
void Write(Content);

DebuggingCPU

Bus16Bit

BIU16Bit(Bus16Bit*);

Bus16Bit(Memory*);

Word fetchDataWord(Address);

Word fetchDataWord(Address);

void storeDataWord(Address, Word);

void storeDataWord(Address, Word);

DebuggingCPU(BIU*);
void debug();
void trace();
void printRegs();
void dumpMemory();
void help();

Address

Word

DataStore
Byte

Byte read(Address);
void write(Address, Byte);

CodeStore
Instruction* read(Address);
void write(Address, Instruction*);

  36 "                

CodeStore
Instruction* read(Address);
void write(Address, Instruction*);

Instruction
Instruction();
virtual void execute(CPU&) throw(Halt, ErrorMsg) = 0;
Byte getLength();
void setLength(Byte);
virtual void print() = 0;
virtual void printMnemonic() = 0;

ZeroOpInst

OneOpInst

TwoOpInst

ZeroOpInst();

OneOpInst(Operand *);

TwoOpInst(Operand *, Operand *);

virtual void execute(CPU&) throw(Halt, ErrorMsg) = 0;

virtual void execute(CPU&) throw(Halt, ErrorMsg) = 0;


void print();
virtual void printMnemonic() = 0;

virtual void execute(CPU&) throw(Halt, ErrorMsg) = 0;

void print();
virtual void printMnemonic() = 0;

...

void print();
virtual void printMnemonic() = 0;

...

Ret

...

Jmp

Add

Ret();
void execute(CPU&) throw(Halt,ErrorMsg);

Jmp(Operand *);
void execute(CPU&) throw(Halt,ErrorMsg);

Add(Operand *, Operand *);


void execute(CPU&) throw(Halt,ErrorMsg);

void printMnemonic();

void printMnemonic();

void printMnemonic();

Operand
virtual Word read(CPU&) = 0;
virtual void write(CPU&, Word) throw(ErrorMsg) = 0;
virtual Address getEffectiveAddress(CPU&) throw(ErrorMsg) = 0;
Byte getSize();
virtual void print() = 0;

MemOp
MemOp(Memory *, Address, Byte&, Byte);

RegOp

ImmOp

RegOp(Memory *, Address, Byte);


RegOp(registerName);
Word read(CPU&);
void write(CPU&, Word) throw(ErrorMsg);

ImmOp(Memory *, Address, Byte, Byte);


ImmOp(Word);
Word read(CPU&);
void write(CPU&, Word) throw(ErrorMsg);

Address getEffectiveAddress(CPU&) throw(ErrorMsg);

Address getEffectiveAddress(CPU&) throw(ErrorMsg);

Address getEffectiveAddress(CPU&) throw(ErrorMsg);

void print();

void print();

void print();

Word read(CPU&);
void write(CPU&, Word) throw(ErrorMsg);

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JMP

SourceOperand

CPU

IP

execute(Cpu&);
read(Cpu&);
offset
readReg(IP);
read();
addr
addr
writeReg(IP, addr+offset);
write(addr+offset);

  +6 -    B    


    L:;   

'%

PUSH

Cpu

SP

SourceOperand

Biu

Bus

Memory

DataStore

execute(Cpu&);
readReg(SP);
read();
addr
addr
writeReg(SP,addr-2);
write(addr-2);

read(CPU&);
dataWord
storeDataWord(addr-2, dataWord);
storeDataWord(addr-2, dataWord);
storeDataByte(addr-1, highByte);
writeDataByte(addr-1, highByte);
write(addr-1, highByte);

storeDataByte(addr-2, lowByte);
writeDataByte(addr-2, lowByte);
write(addr-2, lowByte);

 

6 -    B    


    ;F1   

'4

RegOp

CPU

AX

write(Cpu&, value);
writeReg(AX, value);
write(value);

  '6 -    B              


  "P

MemOp

Cpu

BX

Biu

Bus

Memory

DataStore

read(Cpu&);
readReg(BX);
read();
addr
addr
fetchDataWord(addr);
fetchDataWord(addr);
fetchDataByte(addr+1);
readDataByte(addr+1);
read(addr+1);
highByte
highByte
highByte
fetchDataByte(addr);
readDataByte(addr);
read(addr);
lowByte
lowByte
lowByte
fullWord
fullWord
fullWord

  26 -    B      ,       


  $9P(

',

DebuggingCpu

Biu

Bus

Memory

CodeStore

trace();
read();
addr
fetchInstruction(addr);
fetchInstruction(addr);
readInstruction(addr);
read(addr);
Inst*

if Inst* == NULL?
decodeInstruction(addr);

Inst*
Inst*
Inst*
Inst*
read();
addr
getLength();
len
write(addr+len);

execute(Cpu&);

  %6 -    B       

'3

IP

Inst

  46 F     

'&

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