1st+lecture Sequential Synchronous)

Digital Circuits
Part-2
2B: 1, 2, 3, 4
Contents of Part-2
Sequential Circuits Registers Memories CAD for digital circuit: Basic VHDL Digital Integrated Circuits: Basic and Applications
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Sequential Circuits
A Short Review of Part-1 Synchronous Sequential Circuits - Introduction - Analysis and Design - Examples - Homework - Conclusion
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Objectives
Sequential
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Part-1 Review
In the latter part of the 19th century, George Boole, a philosophers and mathematicians, suggested that logical thought could be represented through mathematical equations.
Computers, as we know them today, are implementations of Booles Laws of Thought.
Part-1 Review: Boolean Algebra

A Boolean operator can be completely described using a truth table. The truth table for the Boolean operators AND and OR are shown at the right. The AND operator is also known as a Boolean product. The OR operator is the Boolean sum.
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The truth table for the Boolean NOT operator is shown at the right. The NOT operation is most often designated by an overbar. It is sometimes indicated by a prime mark ( ) or an elbow ().

A Boolean function has:

At least one Boolean variable, At least one Boolean operator, and At least one input from the set {0,1}.
It produces an output that is also a member of the set {0,1}.

Now you know why the binary numbering system is so handy in digital systems.

The truth table for the Boolean function:
is shown at the right. To make evaluation of the Boolean function easier, the truth table contains extra (shaded) columns to hold evaluations of subparts of the function.
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As with common arithmetic, Boolean operations have rules of precedence. The NOT operator has highest priority, followed by AND and then OR. This is how we chose the (shaded) function subparts in our table.
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Digital computers contain circuits that implement Boolean functions. The simpler that we can make a Boolean function, the smaller the circuit that will result.
Simpler circuits are cheaper to build, consume less power, and run faster than complex circuits.
With this in mind, we always want to reduce our Boolean functions to their simplest form. There are a number of Boolean identities that help us to do this.
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Most Boolean identities have an AND (product) form as well as an OR (sum) form. We give our identities using both forms. Our first group is rather intuitive:
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Our second group of Boolean identities should be familiar to you from your study of algebra:
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Our last group of Boolean identities are perhaps the most useful. If you have studied set theory or formal logic, these laws are also familiar to you.
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We can use Boolean identities to simplify the function: as follows:
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Sometimes it is more economical to build a circuit using the complement of a function (and complementing its result) than it is to implement the function directly. DeMorgans law provides an easy way of finding the complement of a Boolean function. Recall DeMorgans law states:
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DeMorgans law can be extended to any number of variables. Replace each variable by its complement and change all ANDs to ORs and all ORs to ANDs. Thus, we find the the complement of:
is:
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Through our exercises in simplifying Boolean expressions, we see that there are numerous ways of stating the same Boolean expression.
These synonymous forms are logically equivalent. Logically equivalent expressions have identical truth tables.
In order to eliminate as much confusion as possible, designers express Boolean functions in standardized or canonical form.
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There are two canonical forms for Boolean expressions: sum-of-products and product-of-sums. Recall the Boolean product is the AND operation and the Boolean sum is the OR operation. In the sum-of-products form, ANDed variables are ORed together. For example: In the product-of-sums form, ORed variables are ANDed together: For example:
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It is easy to convert a function to sum-of-products form using its truth table. We are interested in the values of the variables that make the function true (=1). Using the truth table, we list the values of the variables that result in a true function value. Each group of variables is then ORed together.
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The sum-of-products form for our function is:
We note that this function is not in simplest terms. Our aim is only to rewrite our function in canonical sum-of-products form.
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Part-1 Review: Logic Gates

We have looked at Boolean functions in abstract terms. In this section, we see that Boolean functions are implemented in digital computer circuits called gates. A gate is an electronic device that produces a result based on two or more input values. In reality, gates consist of one to six transistors, but digital designers think of them as a single unit. Integrated circuits contain collections of gates suited to a particular purpose.
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The three simplest gates are the AND, OR, and NOT gates.
They correspond directly to their respective Boolean operations, as you can see by their truth tables.
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Another very useful gate is the exclusive OR (XOR) gate. The output of the XOR operation is true only when the values of the inputs differ.
Note the special symbol for the XOR operation.

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NAND and NOR are two very important gates. Their symbols and truth tables are shown at the right.
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NAND and NOR are known as universal gates because they are inexpensive to manufacture and any Boolean function can be constructed using only NAND or only NOR gates.
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Gates can have multiple inputs and more than one output.
A second output can be provided for the complement of the operation. Well see more of this later.
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Part-1 Review: Digital Components

The main thing to remember is that combinations of gates implement Boolean functions. The circuit below implements the Boolean function:
We simplify our Boolean expressions so that we can create simpler circuits.

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Part-1 Review: Combinational Circuits

We have designed a circuit that implements the Boolean function: This circuit is an example of a combinational logic circuit. Combinational logic circuits produce a specified output (almost) at the instant when input values are applied.
In a later section, we will explore circuits where this is not the case.
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Combinational logic circuits give us many useful devices. One of the simplest is the half adder, which finds the sum of two bits. We can gain some insight as to the construction of a half adder by looking at its truth table, shown at the right.
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As we see, the sum can be found using the XOR operation and the carry using the AND operation.
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We can change our half adder into to a full adder by including gates for processing the carry bit. The truth table for a full adder is shown at the right.
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How can we change the half adder shown below to make it a full adder?
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Heres our completed full adder.
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Just as we combined half adders to make a full adder, full adders can connected in series. The carry bit ripples from one adder to the next; hence, this configuration is called a ripple-carry adder.
Todays systems employ more efficient adders.

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Decoders are another important type of combinational circuit. Among other things, they are useful in selecting a memory location according a binary value placed on the address lines of a memory bus. Address decoders with n inputs can select any of 2n locations.
This is a block diagram for a decoder.
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This is what a 2-to-4 decoder looks like on the inside.
If x = 0 and y = 1, which output line is enabled?

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A multiplexer does just the opposite of a decoder. It selects a single output from several inputs. The particular input chosen for output is determined by the value of the multiplexers control lines. To be able to select among n inputs, log2n control lines are needed.
This is a block diagram for a multiplexer.

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This is what a 4-to-1 multiplexer looks like on the inside.
If S0 = 1 and S1 = 0, which input is transferred to the output?

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This shifter moves the bits of a nibble one position to the left or right.
If S = 0, in which direction do the input bits shift?

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Sequential Circuits
Combinational logic circuits are perfect for situations when we require the immediate application of a Boolean function to a set of inputs. There are other times, however, when we need a circuit to change its value with consideration to its current state as well as its inputs.
These circuits have to remember their current state.
Sequential logic circuits provide this functionality for us.
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Sequential Circuits
Asynchronous
Inputs Combinational Circuit Memory Elements Outputs
Synchronous
Inputs Combinational Circuit Flip-flops Clock Outputs
Sequential Circuits
As the name implies, sequential logic circuits require a means by which events can be sequenced. State changes are controlled by clocks. A clock is a special circuit that sends electrical pulses through a circuit. Clocks produce electrical waveforms such as the one shown below.
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Sequential Circuits
State changes occur in sequential circuits only when the clock ticks. Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage.
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Sequential Circuits
Circuits that change state on the rising edge, or falling edge of the clock pulse are called edgetriggered. Level-triggered circuits change state when the clock voltage reaches its highest or lowest level.
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Sequential Circuits
The behavior of sequential circuits can be expressed using characteristic tables or finite state machines (FSMs).
FSMs consist of a set of nodes that hold the states of the machine and a set of arcs that connect the states.
Moore and Mealy machines are two types of FSMs that are equivalent.
They differ only in how they express the outputs of the machine.
Moore machines place outputs on each node, while Mealy machines present their outputs on the transitions.
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Sequential Circuit Analysis
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SR Latch
0 0
Latches
S R Q0 0 0 0 Q 0 Q 1
Q=Q 0
Initial Value
Latches
SR Latch
0 1
S R Q0 0 0 0 0 0 1 Q 0 1 Q 1 0
Q=Q 0 Q=Q 0
Latches
SR Latch
1 0
S 0 0 0 R 0 0 1 Q0 0 1 0 Q 0 1 0 Q 1 0 1
Q=Q 0 Q=0
Latches
SR Latch
1 1
S 0 0 0 0 R 0 0 1 1 Q0 0 1 0 1 Q 0 1 0 0 Q 1 0 1 1
Q=Q 0 Q=0 Q=0
Latches
SR Latch
0 0
S 0 0 0 0 1 R 0 0 1 1 0 Q0 0 1 0 1 0 Q 0 1 0 0 1 Q 1 0 1 1 0
Q=Q 0 Q=0 Q=1
Latches
SR Latch
0 1
S 0 0 0 0 1 1 R 0 0 1 1 0 0 Q0 0 1 0 1 0 1 Q 0 1 0 0 1 1 Q 1 0 1 1 0 0
Q=Q 0 Q=0 Q=1 Q=1
Latches
SR Latch
1 0
S 0 0 0 0 1 1 1 R 0 0 1 1 0 0 1 Q0 0 1 0 1 0 1 0 Q 0 1 0 0 1 1 0 Q 1 0 1 1 0 0 0
Q=Q 0 Q=0
Q=1 Q = Q
1 0
Latches
SR Latch
1 1 0
S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 Q 0 1 0 0 1 1 0 0 Q 1 0 1 1 0 0 0 0
Q=Q 0 Q=0
Q=1 Q = Q Q = Q
Latches
SR Latch
S R 0 0 1 1 S 0 0 1 1 0 1 0 1 Q Q0 0 1 Q=Q=0
No change Reset Set Invalid
Q R 0 Q=Q=1 1 1 0 0 Q0 1
Invalid Set Reset No change
Latches
SR Latch
S R 0 0 1 1 0 1 0 1 Q Q0 0 1 Q=Q=0 Q Q=Q=1 1 0 Q0
Invalid Set Reset No change No change Reset Set Invalid
S R 0 0 1 1 0 1 0 1
Controlled Latches
SR Latch with Control Input
C S R 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1
Q Q0 Q0 0 1 Q=Q
No change No change Reset Set Invalid
Controlled Latches
D Latch (D = Data)
C D Timing Diagram
C D 0 x 1 0 1 1
Q Q0 0 1
No change Reset Set
Output may change
Controlled Latches
D Latch (D = Data)
C D Timing Diagram
C D 0 x 1 0 1 1
Q Q0 0 1
Output may change No change Reset Set
Flip-Flops
Controlled latches are level-triggered
C
Flip-Flops are edge-triggered

CLK Positive Edge
CLK
Negative Edge
Flip-Flops
Master-Slave D Flip-Flop
D D D Latch C (Master) Q D D Latch C (Slave) Q Q
Master
Slave
CLK CLK
D Looks like it is negative edgetriggered
Q Master Q Slave
Flip-Flops
Edge-Triggered D Flip-Flop
D Q
Q Positive Edge
Q CLK
D Q
Q
Q Negative Edge
Flip-Flops
JK Flip-Flop
D = JQ + KQ
K Q
Flip-Flops
T Flip-Flop
T J Q T D Q
D = JQ + KQ D = TQ + TQ = T Q
Flip-Flop Characteristic Tables

D Q Q
D 0 1 J 0 0 1 1 T 0 1
Q(t+1) 0 1 K Q(t+1) 0 Q(t) 1 0 0 1 1 Q(t) Q(t+1) Q(t) Q(t)
Reset Set
No change Reset Set Toggle
Q No change Toggle
Flip-Flop Characteristic Equations

D Q Q
D 0 1 J 0 0 1 1 T 0 1
Q(t+1) 0 1 K Q(t+1) 0 Q(t) 1 0 0 1 1 Q(t) Q(t+1) Q(t) Q(t)
Q(t+1) = D
Q(t+1) = JQ + KQ
Q Q(t+1) = T Q

Analysis / Derivation
J 0 0 0 0 1 1 1 1 K Q(t) Q(t+1) 0 0 0 0 1 1 1 0 1 1 0 0 0 1 1 0 1 1

J 0 0 0 0 1 1 1 1 K Q(t) Q(t+1) 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1

J 0 0 0 0 1 1 1 1 K Q(t) Q(t+1) 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 1

J 0 0 0 0 1 1 1 1 K Q(t) Q(t+1) 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 1 1 0

J 0 0 0 0 1 1 1 1 K Q(t) Q(t+1) 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 1 1 0
K 0 J 1 1 1 Q 0 0 0 1
Q(t+1) = JQ + KQ
Flip-Flops with Direct Inputs

Asynchronous Reset
R 0
D CLK Q(t+1) x x 0
Q R Reset

Asynchronous Reset
Q R Reset
R 0 1 1
D CLK Q(t+1) x x 0 0 0 1 1

Asynchronous Preset and Clear
Preset PR D Q
PR CLR D CLK Q(t+1) 1 0 x x 0
Q CLR Reset

Preset PR D Q
Q CLR Reset
PR CLR D CLK Q(t+1) 1 0 x x 0 x 0 1 x 1

Preset PR D Q
Q CLR Reset
PR CLR D CLK Q(t+1) 1 0 x x 0 x 0 1 x 1 1 1 0 0 1 1 1 1
Analysis of Clocked Sequential Circuits

The State
State = Values of all Flip-Flops
Example AB=00
x D Q Q A
D CLK
Q Q

State Equations
A(t+1) = D A = A(t) x(t)+B(t) x(t) =Ax+Bx B(t+1) = D B = A(t) x(t) = A x y(t) = [A(t)+ B(t)] x(t) = (A + B) x
CLK x D Q Q A
Q Q

State Table (Transition Table)
Present Input State Next State Output
x D Q Q A
A 0 0 0 0 1 1 1 1
t
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1
t+1
B 0 1 0 1 0 0 0 0
t
y 0 0 1 0 1 0 1 0
D CLK
Q Q
A(t+1) = A x + B x B(t+1) = A x y(t) = (A + B) x

State Table (Transition Table)
Present State Next State Output x=0 x=1 x=0 x=1
x D Q Q A
A 0 0 1 1
t
B 0 1 0 1
A 0 0 0 0
B 0 0 0 0
t+1
A 0 1 1 1
B 1 1 0 0
y 0 1 1 1
t
y 0 0 0 0
D CLK
Q Q
A(t+1) = A x + B x B(t+1) = A x y(t) = (A + B) x

State Diagram
AB
Present State
Next State x=0 x=1
Output x=0 x=1
input/output
A B 0 0 0 1 1 0 1 1
A B A B 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0
y 0 1 1 1
y 0 0 0 0
0/0 0/1
00
1/0
10
x
0/1 1/0 0/1 1/0
Q Q
D CLK
Q Q
01
11
1/0

D Flip-Flops Example:
Present Input State Next State
x y CLK D Q A
A 0 0 0 0 1 1 1 1
x 0 0 1 1 0 0 1 1
y 0 1 0 1 0 1 0 1
A 0 1 1 0 1 0 0 1
A(t+1) = D = A x y A
01,10 00,11 0 01,10 1 00,11

JK Flip-Flops Example:
Present Next I/P State State A B x A B 0 0 0 0 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 Flip-Flop Inputs JA KA JB KB 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0
J =B A J = x B
J x K Q Q A
J K CLK
Q Q
K = B x A K =Ax B
A(t+1) = J Q + K Q A A A A = AB + AB + Ax B(t+1) = J Q + K Q B B B B = Bx + ABx + ABx

JK Flip-Flops Example:
Present Next I/P State State A B x A B 0 0 0 0 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 Flip-Flop Inputs JA KA JB KB 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0
01 10 00 11

T Flip-Flops Example:
Present Next F.F I/P O/P State State Inputs A B x A B TA TB y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1
T =Bx T =x A B y =AB A(t+1) = T Q + T Q A A A A = AB + Ax + ABx B(t+1) = T Q + T Q B B B B =xB

T Flip-Flops Example:
Present Next F.F I/P O/P State State Inputs A B x A B TA TB y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1
11 10
0/0
00
0/0 1/0
01
1/1
1/0
0/1
1/0
0/0
Mealy and Moore Models

The Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15).
The outputs may change if the inputs change during the clock pulse period.
The outputs may have momentary false values unless the inputs are synchronized with the clocks.
The Moore model: the outputs are functions of the present state only (Fig. 5-20).
The outputs are synchronous with the clocks.
Fig. 5.21 Block diagram of Mealy and Moore state machine

Mealy
Present State A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 I/P x 0 1 0 1 0 1 0 1 Next O/P State A B y 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 Present State A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
Moore
I/P x 0 1 0 1 0 1 0 1 Next O/P State A B y 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1
For the same state state, the output changes with the input
For the same state state, the output does not change with the input
Moore State Diagram

State / Output 0 1
00/0 01/0
11/1
10/0
1 0
State Reduction and Assignment

State Reduction Reductions on the number of flip-flops and the number of gates. A reduction in the number of states may result in a reduction in the number of flipflops. An example state diagram showing in Figure
State diagram
State Reduction
State: a a b c d e f f g f g a Input: 0 1 0 1 0 1 1 0 1 0 0
Output:
0 0 0 0 0 1 1 0 1 0 0
Only the input-output sequences are important. Two circuits are equivalent
Have identical outputs for all input sequences; The number of states is not important.
State diagram
Equivalent states
Two states are said to be equivalent
For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state. One of them can be removed.
Reducing the state table

e = g (remove g); d = f (remove f);
The reduced finite state machine
State: Input:
Output:
a 0 0
a 1 0
b 0 0
c 1 0
d 0 0
e 1 1
d 1 1
d 0 0
e 1 1
d 0 0
e 0 0
State Reduction
The checking of each pair of states for possible equivalence can be done systematically using Implication Table. The unused states are treated as don't-care condition fewer combinational gates.
Fig. 5.26 Reduced State diagram
State Assignment
State Assignment To minimize the cost of the combinational circuits. Three possible binary state assignments. (m states need n-bits, where 2n > m)
State Assignment
Any binary number assignment is satisfactory as long as each state is assigned a unique number. Use binary assignment 1.
Design Procedure
Design Procedure for sequential circuit
The word description of the circuit behavior to get a state diagram; State reduction if necessary; Assign binary values to the states; Obtain the binary-coded state table; Choose the type of flip-flops; Derive the simplified flip-flop input equations and output equations; Draw the logic diagram;
Design of Clocked Sequential Circuits

Example: Detect 3 or more consecutive 1s
0 S /0 0 0 0 1 1 S /0 1
State A B S0 0 0 S1 0 1 S2 1 0 1 1 S3
S /1 3 1 1
S /0 2

A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1
B 0 1 0 0 0 1 0 1
y 0 0 0 0 0 0 1 1
0 S /0 0
1 S /0 1 0 0 1
S /1 3 1 1
S /0 2

A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1
B 0 1 0 0 0 1 0 1
y 0 0 0 0 0 0 1 1
Synthesis using D Flip-Flops
A(t+1) = D (A, B, x) A = (3, 5, 7) B(t+1) = D (A, B, x) B = (1, 5, 7) y (A, B, x) = (6, 7)

D (A, B, x) = (3, 5, 7) A =Ax +B x D (A, B, x) = (1, 5, 7) B = A x + B x
B 0 0 1 0 A 0 1 1 0 x B 0 1 0 0 A 0 1 1 0 x
B
y (A, B, x) = (6, 7) =AB
0 0 0 0 A 0 0 1 1 x

D =Ax +Bx A D = A x + B x B y =AB
Flip-Flop Excitation Tables

Present Next State State F.F. Input Present Next State State F.F. Input
0 0 (No change) 0 1 (Reset) 1 0 (Set) 1 1 (Toggle) 0 1 (Reset) 1 1 (Toggle) 0 0 (No change) 1 0 (Set)
Q(t) Q(t+1) 0 0 0 1 1 0 1 1
D 0 1 0 1
Q(t) Q(t+1) J K 0 x 0 0 1 x 0 1 x 1 1 0 x 0 1 1 Q(t) Q(t+1) 0 0 0 1 1 0 1 1 T 0 1 1 0
Design of Clocked Sequential Circuits with JK F.F. Example: Detect 3 or more consecutive 1s
Present Input State Next State Flip-Flop Inputs
Synthesis using JK F.F. J (A, B, x) = (3) A d JA (A, B, x) = (4,5,6,7)
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1
B JA 0 0 1 0 0 0 0 1 0 x 1 x 0 x 1 x
KA JB KB x 0 x x 1 x x x 1 x x 1 1 0 x 0 1 x 1 x 1 0 x 0
K (A, B, x) = (4, 6) A d KA (A, B, x) = (0,1,2,3)
J (A, B, x) = (1, 5) B d JB (A, B, x) = (2,3,6,7)
K (A, B, x) = (2, 3, 6) B d KB (A, B, x) = (0,1,4,5)
Design of Clocked Sequential Circuits with JK F.F. Example: Detect 3 or more consecutive 1s
Synthesis using JK Flip-Flops
J = B x K = x A A J =x B K = A + x B
B 0 0 1 0 A x x x x x B 0 1 x x A 0 1 x x x
B x x x x A 1 0 0 1 x B x x 1 1 A x x 0 1 x
Design of Clocked Sequential Circuits with T F.F. Example: Detect 3 or more consecutive 1s
Present Input State Next State F.F. Input
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
A 0 0 0 1 0 1 0 1
B 0 1 0 0 0 1 0 1
TA 0 0 0 1 1 0 1 0
TB 0 1 1 1 0 1 1 0
Synthesis using T Flip-Flops
T (A, B, x) = (3, 4, 6) A T (A, B, x) = (1, 2, 3, 5, 6) B
Design of Clocked Sequential Circuits with T F.F. Example: Detect 3 or more consecutive 1s
Synthesis using T Flip-Flops
T = A x + A B x A T = A B + B x B
B 0 0 1 0 A 1 0 0 1 x
B 0 1 1 1 A 0 1 0 1 x
Sequential Circuits
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Sequential Circuits
This is an ASM for a microwave oven.
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Example: State Machine

Another type of sequential circuit
Combines combinational logic with storage Remembers state, and changes output (and state) based on inputs and current state
State Machine
Inputs
Combinational Logic Circuit
Outputs
Storage Elements
Example: State Machine Combinational vs. Sequential

Two types of combination locks
30 25 5 10 15
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Combinational Success depends only on the values, not the order in which they are set.
Sequential Success depends on the sequence of values (e.g, R-13, L-22, R-3).
State
The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken. Examples: The state of a basketball game can be represented by the scoreboard. Number of points, time remaining, possession, etc. The state of a tic-tac-toe game can be represented by the placement of Xs and Os on the board.
State of Sequential Lock

Our lock example has four different states, labeled A-D: A: The lock is not open, and no relevant operations have been performed. B: The lock is not open, and the user has completed the R-13 operation. C: The lock is not open, and the user has completed R13, followed by L-22. D: The lock is open.
Sequential Lock State Diagram

Shows states and actions that cause a transition between states.
Example: Traffic Sign

A blinking traffic sign
No lights on 1 & 2 on 1, 2, 3, & 4 on 1, 2, 3, 4, & 5 on (repeat as long as switch is turned on)
1 5 2 3 4
DANGER
MOVE RIGHT
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Traffic Sign State Diagram
Switch on Switch off
State bit S 1
State bit S 0 Outputs
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Traffic Sign Truth Tables

Outputs (depend only on state: S S ) 1 0
Lights 1 and 2 Lights 3 and 4 Switch Light 5
Next State: S S 1 and (depend on state 0 input)
In S1 0 0 1 1 S0 0 1 0 1 Z 0 1 1 1 Y 0 0 1 1 X 0 0 0 1 0 1 1 1 1
Whenever In=0, next state is 00.
S1 X 0 0 1 1
S0 S1 S0 X 0 1 0 1 0 0 1 1 0 0 1 0 1 0
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Traffic Sign Logic
Master-slave flipflop
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Conclusion
Computers are implementations of Boolean logic. Boolean functions are completely described by truth tables. Logic gates are small circuits that implement Boolean operators. The basic gates are AND, OR, and NOT.
The XOR gate is very useful in parity checkers and adders.
The universal gates are NOR, and NAND.

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Conclusion
Computer circuits consist of combinational logic circuits and sequential logic circuits. Combinational circuits produce outputs (almost) immediately when their inputs change. Sequential circuits require clocks to control their changes of state. The basic sequential circuit unit is the flip-flop: The behaviors of the SR, JK, and D flip-flops are the most important to know.
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Conclusion
The behavior of sequential circuits can be expressed using characteristic tables or through various finite state machines. Moore and Mealy machines are two finite state machines that model high-level circuit behavior. Algorithmic state machines are better than Moore and Mealy machines at expressing timing and complex signal interactions. Examples of sequential circuits include memory, counters, and Viterbi encoders and decoders.
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Digital Circuits

Computers, as we know them today, are implementations of Booles Laws of Thought.

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

It produces an output that is also a member of the set {0,1}.

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Boolean Algebra

Part-1 Review: Logic Gates

Part-1 Review: Logic Gates

Part-1 Review: Logic Gates

Note the special symbol for the XOR operation.

Part-1 Review: Logic Gates

Part-1 Review: Logic Gates

Part-1 Review: Logic Gates

Part-1 Review: Digital Components

We simplify our Boolean expressions so that we can create simpler circuits.

Part-1 Review: Combinational Circuits

Part-1 Review: Combinational Circuits

Part-1 Review: Combinational Circuits

Part-1 Review: Combinational Circuits

Part-1 Review: Combinational Circuits

Part-1 Review: Combinational Circuits

Part-1 Review: Combinational Circuits

Todays systems employ more efficient adders.

Part-1 Review: Combinational Circuits

Part-1 Review: Combinational Circuits

If x = 0 and y = 1, which output line is enabled?

Part-1 Review: Combinational Circuits

This is a block diagram for a multiplexer.

Part-1 Review: Combinational Circuits

If S0 = 1 and S1 = 0, which input is transferred to the output?

Part-1 Review: Combinational Circuits

If S = 0, in which direction do the input bits shift?

Sequential logic circuits provide this functionality for us.

Sequential Circuit Analysis

Invalid Set Reset No change

No change No change Reset Set Invalid

No change Reset Set

Output may change

Output may change No change Reset Set

Flip-Flops are edge-triggered

D Looks like it is negative edgetriggered

Flip-Flop Characteristic Tables

Q(t+1) 0 1 K Q(t+1) 0 Q(t) 1 0 0 1 1 Q(t) Q(t+1) Q(t) Q(t)

No change Reset Set Toggle

Flip-Flop Characteristic Equations

Q(t+1) 0 1 K Q(t+1) 0 Q(t) 1 0 0 1 1 Q(t) Q(t+1) Q(t) Q(t)

Flip-Flop Characteristic Equations

Flip-Flop Characteristic Equations

Flip-Flop Characteristic Equations