1 2 3 4 5 6 7 8

D D

In 32-bit data mode be supported below,

-UART2 channel with RTS/CTS
-or UART0's RxD/TxD with RTS/CTS & SIO VDD

U1

1 16
C1+ VCC
C9 C12
0.1uF 0.1uF
3 2
C1- V+
VDD
4 6
C2+ V-
P1 U2
C11 C13
C CONNECTOR DB9 C
0.1uF
0.1uF
1 5 15 1 16
C2- GND C1+ VCC
6
2 14 11 TxD0 C10 C14
T1OUT T1IN
7 nCTS0_M 13 12 RxD0
R1IN R1OUT 0.1uF 0.1uF
3 TXD1_M 7 10 TxD1 3 2
T2OUT T2IN C1- V+
8 nRTS0_M TXD2_M 8 9 RxD1
R2IN R2OUT
4 4 6
C2+ V-
9
5 C15 C16
MAX3232C
0.1uF
5 15 0.1uF
C2- GND
nRTS0_M 14 11 nRTS0
P2 T1OUT T1IN
13 12 nCTS0
CONNECTOR DB9 R1IN R1OUT
nCTS0_M 7 10 nRTS1
T2OUT T2IN
1 8 9 nCTS1
R2IN R2OUT
6
2 TXD1_M
7 nCTS1_M
MAX3232C
3 TXD2_M
8 nRTS1_M
4
9
5

B B
(FEMAIL) nRTS1_M

nCTS1_M UART Interface

In 32-bit mode , UART0 Handshake

A A

Title

Size Number Revision

A3
Date: 12-May-2003 Sheet of
File: F:\LAYOUT\ARM_DEVELOP_BOARD V1.0\ARM_DEVELOP_BOARD.Ddb
Drawn By:
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8 9 10 11 12

D D

VDD
U3A
D1
LED0 1 2 R5
J1 330
CON40 VDD
74HC04 LED

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
U3B

9
8
7
6
5
4
3
2
1
D2 OM[1:0] : Bus Size
VDD LED1 3 4 R6
00 : Byte (8-bit)
330 R9 R10 R11 R12 01 : Halfword (16-bit)
S1 10 : Word (32-bit)
74HC04 LED 4.7K 4.7K 4.7K 4.7K 11 : Test Mode
1 3
R1

DATA14
DATA15
2 4 KEYIN3 U3C ENDIAN
SW_PUSH2 10K D3 H : Big, L : Little
R7

EXTAL1
XTAL1

AIN7
AIN6
LED2 5 6

AVCOM
AREFB
AREFT
S2 330
74HC04 LED

D12SUSPD
LED0
LED1
LED2
1 3 OM0
R2

nRTS1
nCTS1

nRTS0
nCTS0

VD0
VD1
VD2
VD3
VCLK
VLINE
VM
VFRAME
2 4 KEYIN2
OM0
SW_PUSH2 10K

TxD1
RxD1

TxD0
RxD0

2
VD7
VD6
VD5
VD4

VDD_CPU
S3
JP1 OM1 OM3
1 3
2 4 KEYIN1 R3 OM1

2
10K R13

1
SW_PUSH2

nDISP-ON
4.7K

nEL-ON
JP2 OM2
S4
1 3 VDDADC EDN J8
R4

3
2 4 KEYIN0 U3D

1
HD3
SW_PUSH2 10K
VDDRTC nDISP-ON 9 8 DISP-ON JP3 2 ENDIAN

74HC04

1
U3E OM[3:2] : Clock Mode
00 : Crystal, PLL on
nEL-ON 11 10 EL-ON J10 01 : Externall, PLL on
VD0 10 : Test Mode
1 11 : Test Mode
VD1 R15
74HC04 2
VD2
3 4.7K
VDD_CPU VDDRTC VD3
4
VD4
5
VD5
6

nEL-ON
nDISP-ON
VDDIO VDDADC VD6
7
C17 103 VD7
VR1 8
VFRAME Boot ROM Bus Size, ENDIAN, and Clock Mode Select
C 20K 9 C
VDD GND
10
VCLK
11
VLINE
12
C18 103 VCTL
13
VM

VD7
VD6
VD5
VD4
14

RxD1

RxD0
TxD1

TxD0
nRESET

VFRAME
D12SUSPD
15
EL-ON

VLINE
nRTS1
nCTS1

nRTS0
nCTS0

VCLK
16
C19 103 XTAL1 VDDIO

VD0
VD1
VD2
VD3

VM
LED0 17
LED1
LED2
DISP-ON
18

AVCOM
AREFB
AREFT
EXTAL1
X1 19

XTAL1
VCC5.0 CON20
20

AIN7
AIN6
DATA15 32.768kHz
DATA14 RTC Input LCD CONNECTOR
EXTAL1

VDD
C20 C21
22pF 22pF
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
U4

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
S3C44B0X

AIN7
AIN6
DATA14
DATA15

DATA28/TxD1/GPC12
DATA29/RxD1/GPC13

VLINE/GPD5

AREFB
VDDADC
VDD3

AVCOM
DATA26/nRTS1/GPC10
DATA27/nCTS1/GPC11

DATA30/nRTS0/GPC14
DATA31/nCTS0/GPC15

RxD0/GPE2

VFRAME/GPD7
VSSIO3
VDDRTC
TxD0/GPE1

EXTAL1
XTAL1

AREFT
DATA16/IISLRCK/GPC0
DATA17/IISDO/GPC1

DATA24/nXDACK1/GPC8
DATA25/nXDREQ1/GPC9

VD0/GPD0
VD1/GPD1
VD2/GPD2
VD3/GPD3
VCLK/GPD4

VM/GPD6
VSS3
DATA18/IISDI/GPC2
DATAA19/IISCLK/GPC3
DATA20/VD7/GPC4
DATA21/VD6/GPC5
DATA22/VD5/GPC6
DATA23/VD4/GPC7

R16 R17
U5
10K 10K
D8 VDDRTC
1 8
NC0 VDD
VDD 1 2 2 7
NC1 WP
3 6 IICSCL
NC2 SCL

VDD_CPU
1N4004 4 5 IICSDA
VSS SDA

R54

VDDIO
J2
KS24C080
DATA13 DATA13 121 80 AIN5 10K
1 DATA13 AIN5
DATA12 DATA12 122 79 AIN4 C59
2 DATA12 AIN4
DATA11 DATA11 123 78 AIN3 8-SOP-225
3 DATA11 AIN3 104
DATA10 DATA10 124 77 AIN2 VDDIO
4 DATA10 AIN2
VDDIO 125 76 AIN1 BT1 IIC Interface J3
5 VDDIO2 AIN1
GND 126 75 AIN0 AIN5
6 VSSIO4 AIN0 R14 40
DATA9 DATA9 127 74 3V AIN4
7 DATA9 VSSADC 4.7K 39
DATA8 DATA8 128 73 AIN3
8 DATA8 VSSIO2 38
DATA7 DATA7 129 72 GPE7 AIN2
9 DATA7 TOUT4/VD7/GPE7 37
DATA6 DATA6 130 71 GPE6 AIN1
10 DATA6 TOUT3/VD6/GPE6 36
DATA5 DATA5 131 70 BEEP VCC5.0 AIN0
11 DATA5 TOUT2/TCLK/GPE5 35
DATA4 DATA4 132 69 GPE4
12 DATA4 TOUT1/TCLK/GPE4 34
DATA3 DATA3 133 68 GPE3
13 DATA3 TOUT0/GPE3 33
DATA2 DATA2 134 67 EXTCLK GPE7
14 DATA2 EXTCLK 32
DATA1 DATA1 135 66 PLLCAP C48 GPE6
15 DATA1 PLLCAP 31
DATA0 DATA0 136 65 EXTAL0 BEEP
16 DTAT0 EXTAL0 104 30
GPA9 GPA9 137 64 XTAL0 C47 GPE4
17 ADDR24/GPA9 XTAL0 29
VDD_CPU 138 63 GPE3
18
19
ADDR23 ADDR23
139
140
VDD4
VSS4 S3C44B0X VSS2
VDD2
62
61 IICSCL
820pF
PLLCAP
EXTCLK
28
27
20 ADDR23/GPA8 IICSCL/GPF0 26
ADDR22 ADDR22 141 60 IICSDA XTAL0 EXTAL0
21 ADDR22/GPA7 IICSDA/GPF1 25
ADDR21 ADDR21 142 59 IISLRCK XTAL0
22 ADDR21/GPA6 SIOTxD/nRTS1/IISLRCK/GPF5 24
ADDR20 ADDR20 143 SAMSUNG ELECTRONICS CO.,LTD 58 IISDO
23 ADDR20/GPA5 SIORDY/TxD1/IISDO/GPF6 X2 23
ADDR19 ADDR19 144 57 GPF7
24 ADDR19/GPA4 SIORxD/RxD1/IISDI/GPF7 10MHz 22
B ADDR18 ADDR18 145 56 IISCLK IICSCL B
25 ADDR18/GPA3 SIOCLK/nCTS1/IISCLK/GPF8 21
ADDR17 ADDR17 146 55 ENDIAN IICSDA
26 ADDR17/GPA2 ENDIAN/CODECLK/GPE8 20
ADDR16 ADDR16 147 54 OM3 EXTAL0 IISLRCK
27 ADDR16/GPA1 OM3 19
ADDR15 ADDR15 148 53 OM2 IISDO
28 ADDR15 OM2 18
ADDR14 ADDR14 149 52 OM1 VDD GPF7
29 ADDR14 OM1 17
ADDR13 ADDR13 150 51 OM0 IISCLK
30 ADDR13 OM0 C22 C28 LS1 16
ADDR12 ADDR12 151 50 nRESET U3F ENDIAN
31 ADDR12 nRESET 22pF 22pF 15
152 49 ATA_BUFF_DIR OM3
32 VSSIO5 CLKout/GPE0 14
ADDR11 ADDR11 153 48 BEEP 13 12 OM2
33 ADDR11 VSSIO1 13
ADDR10 ADDR10 154 47 OM1
34 ADDR10 VDDIO1 12
ADDR9 ADDR9 155 46 TDO X-TAL SPEAKER OM0
35 ADDR9 TDO 74HC04 11
ADDR8 ADDR8 156 45 TDI nRESET
36 ADDR8 TDI 10
ADDR7 ADDR7 157 44 TMS ATA_BUFF_DIR
37 ADDR7 TMS 9
ADDR6 ADDR6 158 43 TCK
38 ADDR6 TCK 8
ADDR5 ADDR5 159 42 nTRST
39 ADDR5 nTRST 7
ADDR4 ADDR4 160 41 KEYIN3 TDO
40 ADDR4 ExINT7/IISLRCK/GPG7 6
VDDIO TDI
5
nBE2:nWBE2:DQM2/GPB4
nBE3:nWBE3:DQM3/GPB5

CON40 TMS
nXDACK0/nXBACK/GPF3
nXDREQ0/nXBREQ/GPF4

4
TCK
3
ExINT4/IISCLK/GPG4
nGCS6:nSCS0:nRAS0
nGCS7:nSCS1:nRAS1

ExINT2/nCTS0/GPG2
ExINT3/nRTS0/GPG3

nTRST
ExINT6/IISDO/GPG6
nBE0:nWBE0:DQM0
nBE1:nWBE1:DQM1
nCAS2:nSCAS/GPB2
nCAS3:nSRAS/GPB3

ExINT5/IISDI/GPG5

2
ExINT0/VD4/GPG0
ExINT1/VD5/GPG1

KEYIN3
1
nGCS5/GPB10
ADDR0/GPA0

CON40
nWAIT/GPF2
nGCS1/GPB6
nGCS2/GPB7
nGCS3/GPB8

nGCS4/GPB9

SCKE/GPB0
SCLK/GPB1
VDDIO0

R18 R19 R20 R25

VSSIO0
ADDR3
ADDR2
ADDR1

nCAS0
nCAS1

nGCS0

VDD0

VDD1
VSS0

VSS1
nWE

10K 10K 10K 10K

nOE

CN1
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9

2 1
nTRST
4 3
TDI
6 5
TMS
8 7
ADDR3
ADDR2
ADDR1
ADDR0

+ C34 + C33 TCK

10 9
TDO
/D12_INT
ETH_INT

10uF/16V
SCLK

12 11
SCKE

KEYIN0
KEYIN1
KEYIN2
EXINT2
EXINT3

10uF/16V
nSCAS
nSRAS
nCAS0
nCAS1

14 13
VDD_CPU VDDIO
JP4
nWBE0
nWBE1
nWBE2
nWBE3

1 2
nCSROM
nWE

E_ICE
nOE

/D12_CS

nRESET
nATA_CS
n8019_CS

nGCS4
nGCS5

nGCS7

IDE_RST
nSCS0

IDE_CS0
IDE_CS1

C49 C50 C51 C52 C54 C55 C56 C57 C58

VCC5.0
104 104 104 104 104 104 104 104 104

+ C39 + C32 + C31 + C40

C53
10uF/16V 10uF/16V 10uF/16V 10uF/16V
104
VDD_CPU VDDIO
IDE_CS0
IDE_CS1
IDE_RST
nATA_CS
n8019_CS

nGCS4
nGCS5
nSCS0
nGCS7
/D12_CS

+ C35 + C36 + C37 + C38 + C41 + C42 + C43 + C44 + C45

nCSROM

10uF/16V 10uF/16V 10uF/16V 10uF/16V 10uF/16V 10uF/16V 10uF/16V

nWBE0
nWBE1
nWBE2
nWBE3
nOE
nWE

A 10uF/16V 10uF/16V A
EXINT2
EXINT3
KEYIN0
KEYIN1
KEYIN2
nCAS0
nCAS1
nSCAS
nSRAS

/D12_INT
ETH_INT
SCKE
SCLK
ADDR3
ADDR2
ADDR1
ADDR0

VDDIO
VDD_CPU
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9

J4
CON40

Title

Size Number Revision

A1
Date: 12-May-2003 Sheet of
File: F:\LAYOUT\ARM_DEVELOP_BOARD V1.0\ARM_DEVELOP_BOARD.Ddb
Drawn By:

1 2 3 4 5 6 7 8 9 10 11 12
 1 2 3 4 5 6 7 8

D D

U8
ADDR1 25 29 DATA0 VDD
A0 DQ0
ADDR2 24 31 DATA1
A1 DQ1
ADDR3 23 33 DATA2
A2 DQ2
ADDR4 22 35 DATA3
A3 DQ3
ADDR5 21 38 DATA4
U7 A4 DQ4
ADDR6 20 40 DATA5 C67 C68
C A5 DQ5 C
ADDR7 19 42 DATA6
A6 DQ6 104 104
ADDR1 23 2 DATA0 ADDR8 18 44 DATA7
A0 DQ0 A7 DQ7
ADDR2 24 4 DATA1 ADDR9 8 30 DATA8
A1 DQ1 A8 DQ8
ADDR3 25 5 DATA2 ADDR10 7 32 DATA9
A2 DQ2 A9 DQ9
ADDR4 26 7 DATA3 ADDR11 6 34 DATA10
A3 DQ3 A10 DQ10
ADDR5 29 8 DATA4 ADDR12 5 36 DATA11
A4 DQ4 A11 DQ11
ADDR6 30 10 DATA5 ADDR13 4 39 DATA12
A5 DQ5 A12 DQ12
ADDR7 31 11 DATA6 ADDR14 3 41 DATA13
A6 DQ6 A13 DQ13
ADDR8 32 13 DATA7 ADDR15 2 43 DATA14
A7 DQ7 A14 DQ14
ADDR9 33 42 DATA8 ADDR16 1 45 DATA15
A8 DQ8 A15 DQ15/A-1
ADDR10 34 44 DATA9 ADDR17 48 VDD
A9 DQ9 A16
ADDR11 22 45 DATA10 ADDR18 17 26 nCSROM
A10 DQ10 A17 nCE
ADDR12 35 47 DATA11 ADDR19 16 28 nOE
A11 DQ11 A18 nOE
48 DATA12 ADDR20 9 11 nWE
DQ12 A19 nWE
ADDR21 20 50 DATA13 15
BA0 DQ13 nRY/BY
ADDR22 21 51 DATA14 12 nRESET
BA1 DQ14 nRESET
53 DATA15 27 47
R27 22 DQ15 VSS0 nBYTE
nWBE0 15 46 37
R30 22 LDQM R31 22 VSS1 VDD0
nWBE1 39 19 nSCS0
UDQM nSCS R32 22
18 nSRAS
R29 22 nSRAS R33 22 HY29LV160
SCKE 37 17 nSCAS
R28 22 SCKE nSCAS R34 22
SCLK 38 16 nWE
SCLK nWE
VDD
28 1
VSS0 VDD0
41 14
VSS1 VDD1
54 27 VDD
VSS2 VDD2

B 6 3 B
VSSQ0 VDDQ0
12 9
VSSQ1 VDDQ1
46 43
VSSQ2 VDDQ2
52 49 C60 C61 C62 C63 C64 C65 C66
VSSQ3 VDDQ3
104 104 104 104 104 104 104

HY57V641620

A A

Title

Size Number Revision

A3
Date: 12-May-2003 Sheet of
File: F:\LAYOUT\ARM_DEVELOP_BOARD V1.0\ARM_DEVELOP_BOARD.Ddb
Drawn By:
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

D D

VCC5.0

C70
104
VDDADC
VDD_CPU

VCC5.0
VDD
RESET Logic
VCC VDD

2
R35

2
4K7
J5 J6
D10 R26
1N4148 10K
U11

1
LM1117-25
3 2 U17D U17C

1
VIN VOUT
LM1117 12 9
D11 11 8 nRESET

GND
Power LED LED 13 10
C69 C80
C + + C46 74HC32 74HC32 C

1
104 10uF/16V S5
10uF/16V
1 3
2 4
SW_PUSH2

VDDIO VDD

D9 U9 U10
CN2
AS1117-5.0 VCC5.0 LM1117-33
1 1 2 3 2 3 2
1 VIN VOUT VIN VOUT
2 LM1117
2
3
GND

GND
3
1N4004
Power Pins Visible
DC_JACK
1

J7
2 1

B B

C73 C82 C74 C83 C75 C84

+ C81 + + +

104 104 104

100uF/16V 100uF/16V 10uF/16V 10uF/16V

Power Connector

A A

Title

Size Number Revision

A3
Date: 12-May-2003 Sheet of
File: F:\LAYOUT\ARM_DEVELOP_BOARD V1.0\ARM_DEVELOP_BOARD.Ddb
Drawn By:
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

VDD
R62
1M

R41 R43
D 1.5K 1M D
R45
EOT
10K
J11
R38
D12 DM 1
VBUS
18R 2
ADDR0 D-
3
R40 D+
4
GND
18R 5
U15 SHIELD
DATA0 1 28
DATA0 A0 UP_CONN
DATA1 2 27
DATA1 VOUT3.3 ChassisGnd
DATA2 3 26 D12 DP R42
DATA2 D+
DATA3 4 25 1M
DATA3 D-
5 24 C29
GND VCC C85
DATA4 6 23 D12 XTAL2 Chassis Ground
DATA4 XTAL2
DATA5 7 22 D12 XTAL1
DATA5 XTAL1 0.01UF2KV
DATA6 8 21 22PF
DATA6 GL_N X3
DATA7 9 20 nRESET
DATA7 RESET_N 6MHZ
10 19 EOT
ALE EOT_N
/D12_CS 11 18 C30
R46 CS_N DMACK_N
D12SUSPD 12 17 VDD
SUSPEND DMREQ
13 16
R47 10K CLKOUT WR_N
/D12_INT 14 15 22PF
INT_N RD_N R59
nRESET
10K
PDIUSBD12_SOP R48 22
470R
VDD nOE
JP6
C nWE C
ATA_RST
1 2
DATA7 DATA8
3 4
R44 DATA6 DATA9
5 6
DATA5 DATA10
7 8
10K DATA4 DATA11
9 10
DATA3 DATA12
D12 11 12
DATA2 DATA13
LED_GREEN 13 14
DATA1 DATA14
15 16
GOODLNK DATA0 DATA15
17 18 R60
GND ATA_KeyPin nGCS4
R55 19 20
nWE ATA_DMAREQ 22
21 22
22 ATA_DIOW
23 24
ATA_DIOR
R56 25 26
USB Interface PDIUSBD12 Module nOE ATA_IoRdy
R57 27 28
EXINT3 22 ATA_DMACK
R58 29 30
EXINT2 22 ATA_INTRQ
31 32 R61
22 ADDR5 ATA_PDIAG nGCS5
33 34
ADDR4 ADDR3 22
35 36
ADDR2 ADDR1
37 38
ATA_DASP
About with D12 singal 39 40
HEADER 20X2
/D12-CS D5
D12SUSPD LED
/D12-INT
nD12-RST
D12-A0

B B
R49
330

U17A
nWE 1
3 ATA_DIOR
VCC 2
About with IDE singal 74HC32
IDE_CS0
nATA_CS
IDE_CS1
IDE_A0
IDE_A1 U17B
4
IDE_A1
6 ATA_DIOW
IDE_RST
nOE 5
nATA-BUFF-EN 74HC32
ATA-BUFF-DIR
VDD

+ C86
1.0uF16V C76 C77 C78 C79
A 104 104 104 104 A

Title

Size Number Revision

A3
Date: 12-May-2003 Sheet of
File: F:\LAYOUT\ARM_DEVELOP_BOARD V1.0\ARM_DEVELOP_BOARD.Ddb
Drawn By:
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

VCC5.0

D R21 D
4.7K

VCC5.0
VCC5.0
U4

R8 BD1/IOS2

DATA14
DATA15
300 8 1 EECS
VCC CS
7 2 EESK
NC SK
6 3 EEDI

DATA10
DATA11
DATA12
DATA13
NC DI

DATA8
DATA9
IOCS16 5 4 EEDO
XINTREQ0 VCC5.0
GND D0

9346
ETH_INT

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
U6

INT4
INT5
INT6
INT7

BD0
BD1

BD2
BD3
IOCS16B
SD8
SD9
SD10
SD11
SD12
SD13

SD14
SD15
VDD

GND

GND
1 80
INT3 BA4
2 79 EESK
INT2 BD5
3 78 EEDI
INT1 BD6
4 77 EEDO
INT0 BD7
ADDR0 5 76 EECS
SA0 EECS
6 75
VCC5.0 VDD BCSB
ADDR1 7 74 VCC5.0
SA1 BA14
ADDR2 8 73
SA2 BA15
ADDR3 9 72
SA3 BA16
ADDR4 10 71 VCC5.0
SA4 BA17 R50 R22
11 70
SA5 VDD 330 330
12 69
SA6 BA18
13 68
14
SA7
GND
BA19
BA20
67 LED
15 66 VCC5.0
SA8 BA21 R39
VCC5.0 16 65 悬空
SA9 JP
17 64 10K
C VDD AUI C
18 63 D6
SA10 LED2
19 62 D7
SA11 LED1
20 61
SA12 LED0
21 60
SA13 LEDBNC LED
22 59
SA14 TPIN+ LED
23 58 VCC5.0
SA15 TPIN-
24 57
SA16 VDD
25 56
SA17 RX+
26 55
SA18 RX-
27 54
SA19 CD+
28 53
GND CD-
nOE 29 52

SMEMWB

IOCHRDY
SMEMRB
IORB GND

RSTDRV

TPOUT+
TPOUT-
30 51
IOWB OSC2

OSC1
GND

VDD
AEN

TX+
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7

TX-
C87
R52
nWE RTL8019AS 33
22

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Y3

20MHZ
C88
R53

DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
33
VCC5.0 VCC5.0 22

RESET1
n8019_CS

R24
200

B U13 B
VCC5.0 1 16 U14
TPOUT+ TX+
2 15 1
C27 TX+
VCC5.0 3 14 2
4.7u TPOUT- TX- TX-
+ 3
RX+
6 11 4
TPIN+ RX+
RESET1 7 10 5
8 9 6
C71 C72 TPIN- RX- RX-
7
0.1u 0.1u 10K 20F001N 8
R23
RJ45
C23 C24 C25 C26
0.1u 0.1u
0.1u 0.1u

A A

Title

Size Number Revision

A2
Date: 12-May-2003 Sheet of
File: F:\LAYOUT\ARM_DEVELOP_BOARD V1.0\ARM_DEVELOP_BOARD.Ddb
Drawn By:

1 2 3 4 5 6 7 8
 1 2 3 4

D D

VCC5.0
C C
C89 VCC5.0
7

10uF C91
U22 U18
IISDO 1 8 PLOT1 1 8 J20
GND VA

SDATA LOUT IN1+ VCC

IISCLK 2 2 7 220uF
SCLK IN1- OUT1
IISLRCK 3 3 6 C92
LRCK IN2- OUT2
ENDIAN 4 5 4 5
MCLK ROUT IN2+ GND
CS4334 PLOTX2 TDA7050 220uF PHONEJACK STEREO SW
C90
6

10uF

B B

Title
A A

Size Number Revision

A4
Date: 12-May-2003 Sheet of
File: F:\LAYOUT\ARM_DEVELOP_BOARD V1.0\ARM_DEVELOP_BOARD.Ddb
Drawn By:
1 2 3 4