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8-Bit Serial-Input, Dmos Power Driver: Advance Information
8-Bit Serial-Input, Dmos Power Driver: Advance Information
ADVANCE INFORMATION
(Subject to change without notice) January 24, 2000
NO CONNECTION LOGIC SUPPLY SERIAL DATA IN OUT 0 OUT 1 OUT 2 OUT 3 REGISTER CLEAR OUTPUT ENABLE GROUND NO CONNECTION GROUND SERIAL DATA OUT OUT 7 OUT 6 OUT 5 OUT 4 CLOCK STROBE GROUND
1 2 3 4
NC VDD
NC
20 19 18 17
REGISTER
REGISTER
LATCHES
LATCHES
5 6 7 8 9 10 CLR OE
16 15 14 CLK ST 13 12 11
Dwg. PP-029-12
Note that the A6B595KA (DIP) and the A6B595KLW (SOIC) are electrically identical and share a common terminal number assignment.
FEATURES
s 50 V Minimum Output Clamp Voltage s 150 mA Output Current (all outputs simultaneously) s 5 Typical rDS(on) s Low Power Consumption s Replacements for TPIC6B595N and TPIC6B595DW
Always order by complete part number: Part Number Package A6B595KA 20-pin DIP A6B595KLW 20-lead SOIC
2.5
9 12
LOGIC SYMBOL
G3 C2 R SRG8 C1 1D 2 4 5 6
A
2.0
SU FF IX
8 13
1.5
SU FF IX
'A ', R
J A =
'LW ', R
55 C /W
1.0
=7 0 C/ W
7 14
0.5
15 16
17 18
Dwg. GS-004A
Dwg. FP-043
V DD
D-TYPE LATCHES
GROUND
GROUND
OUT 0
OUT N
Dwg. FP-013-4
Grounds (terminals 10, 11, and 19) must be connected together externally.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright 1999, Allegro MicroSystems, Inc.
V IN
DD
OUT
Dwg. EP-063
Dwg. EP-010-16
LOGIC INPUTS
OUT
Dwg. EP-063-1
R0 R1 R0 R1
R5 R6 R5 R6 R6 R7 X X
R0 R1 R2 X X X
P0 P1 P2
P6 P7
P = Present State
R = Previous State
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rDS(on)
IO = 100 mA, VDD = 4.5 V IO = 100 mA, VDD = 4.5 V, TA = 125C IO = 350 mA, VDD = 4.5 V (see note)
VDS(on) = 0.5 V, TA = 85C VI = VDD = 5.5 V VI = 0, VDD = 5.5 V IOH = -20 A, VDD = 4.5 V IOH = -4 mA, VDD = 4.5 V
VOH
VOL
tPLH tPHL
IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF IO = 100 mA, CL = 30 pF VDD = 5.5 V, Outputs OFF VDD = 5.5 V, Outputs ON fclk = 5 MHz, CL = 30 pF, Outputs OFF
Typical Data is at VDD = 5 V and is for design information only. NOTE Pulse test, duration 100 s, duty cycle 2%.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
B
50%
DATA E
OUTPUT ENABLE
tp OUT N
DATA
LOW = OUTPUT ON
Dwg. WP-029-2
t PLH t PHL
90%
tf DATA
tr
OUT N
10%
Dwg. WP-030-2
A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) .......................................... 20 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) .............................................. 20 ns C. Clock Pulse Width, tw(CLK) ............................................. 40 ns D. Time Between Clock Activation and Strobe, tsu(ST) ....................................................... 50 ns E. Strobe Pulse Width, tw(ST) .............................................. 50 ns F. Output Enable Pulse Width, tw(OE) ................................ 4.5 s NOTE Timing is representative of a 12.5 MHz clock. Higher speeds are attainable.
Serial data present at the input is transferred to the shift register on the rising edge of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. Information present at any register is transferred to the respective latch on the rising edge of the STROBE input pulse (serial-to-parallel conversion). When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches.
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TEST CIRCUITS
INPUT +15 V
10.5
OUT
VO
V(BR)DSX
VO(ON)
Dwg. EP-066
EAS = IAS x V(BR)DSX x tAV/2 Single-Pulse Avalanche Energy Test Circuit and Waveforms
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
200 mH
TERMINAL DESCRIPTIONS
Terminal No. 1 2 3 4-7 8 9 10 11 12 13 14-17 18 19 20 Terminal Name NC LOGIC SUPPLY SERIAL DATA IN OUT0-3 CLEAR OUTPUT ENABLE GROUND GROUND STROBE CLOCK OUT4-7 SERIAL DATA OUT GROUND NC Function No internal connection. (VDD) The logic supply voltage (typically 5 V). Serial-data input to the shift-register. Current-sinking, open-drain DMOS output terminals. When (active) low, the registers are cleared (set low). When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). Reference terminal for output voltage measurements (OUT0-3). Reference terminal for output voltage measurements (OUT0-7). Data strobe input terminal; shift register data is latched on rising edge. Clock input terminal for data shift on rising edge. Current-sinking, open-drain DMOS output terminals. CMOS serial-data output to the following shift register. Reference terminal for input voltage measurements. No internal connection.
NOTE Grounds (terminals 10, 11, and 19) must be connected together externally.
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20
11
0.300
BSC
0.070 0.045
10
0.005
MIN
0.210
MAX
0.015
MIN
20
11
7.62
BSC
1.77 1.15
10
0.13
MIN
5.33
MAX
0.39
MIN
NOTES:1. Exact body and lead configuration at vendors option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
0.2992 0.2914
0.419 0.394
3 0.5118 0.4961
0.050
BSC
0 TO 8
7.60 7.40
10.65 10.00
3 13.00 12.60
1.27
BSC
0 TO 8
NOTES:1. Exact body and lead configuration at vendors option within limits shown. 2. Lead spacing tolerance is non-cumulative.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
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The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000