LMS sequential logic So far we have seen only ciruuts where fhe oulpuTs at a givtn time are function of the inpuls applied at YoaT Hme (we have no “memory” of what happend in the past _). Those Kind of cércects are calle L com binationel. Z(tn > combinational legic Olen) = FL Ten note: -the vector notation is just to say fret we can hae several MpaTs aud ou7puts Cthe # of inpuTs aud the # Of ourpuls caw be oi ferent > Qur goal is now Ie build a more general dass of arewts where the outputs at a given time are frretron nel on ly. of the inpul gapplied at thal Hme , botas wek function of the vaues taken at Some time in the past by certain variables. Those Kind of cereeiT® ave called sequentral. tn 0 (tn Fo) oa OS) ecual those variables s ace usually, _ X (tn) called stat. X (tr) variables x |__| memory JeIn order to build a cireuit able & store previously applied inpuT variables we ned + establish a feedback betveen the ouTpuT aud tte input. Feeding back C Combinatoual Zop _) tha output tule the input , we Keep “re Feshing “ the value , so basically we burld a mechanism to “remember” ae through the loop we Keep re-generatin op a > wholever value 4 og preenae On the gate capaci tance. Inve of inva. . o 4 basic memorg Aement Eco ]Y ZT(t)= Goate. 4%) : - at present t A a pas Tbe) = Gate» Vltn)=Vetnr) tn - th,Combinin Transmission gales ana combinabenal gales , it is possible te build latches ad flip-flops. latch = level sensitive storage Hement flip-flop = edge-triggered storage element bata latch (2- Latch ) ae ate a D inva INv2 “D> ib LD ss the eo value D thal we want Te store, on the gate capac’ tance of Nua > (o—f>o. a Lpzo Kep cegenerating \— eo. the vale stored on Gale of m4. a INVE INV2 Done SSN meg Lo=/ pa