Schematic:

Area = 44% Delay = 8.724ns Power = 24.60 mw

Simulation:

Corrected code:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all;

entity gainfix is generic(clockfrequency : Integer := 40000000;

Insinglecycle : boolean := false ); port( clk : in std_logic; reset : in std_logic; enable_in : in std_logic; enable_out : out std_logic; enable_clr : in std_logic; xin : in std_logic_vector(31 downto 0); xout : out std_logic_vector(31 downto 0) ); end gainfix; architecture implementation of gainfix is begin process ( reset,clk,xin) begin if( reset = '1') then xout <= (others=> '0'); else if (rising_edge(clk)) then if enable_in ='1' then xout <= (xin(31) & xin(31) & xin(31 downto

2))+(xin(31) & xin(31) & xin(31) & xin(31 downto

3))-(xin(31) & xin(31) & xin(31) &xin(31) & xin(31

downto 7)); end if; end if; end if; enable_out <= enable_in; end process; end implementation;