EE 312 Exercise In the circuit shown in Figure 1, the input capacitance of the first inverter is 1 fF.

The intrinsic (unloaded) propagation delay of the first inverter is 6 ps. The circuit is driving an external capacitance of 1.3 pF. You may assume that Cint = Cg for all inverters. (Cint: self-loading or intrinsic output capacitance, Cg: Input capacitance) a. Calculate the total propagation delay of the circuit. b. If you were supposed to resize the inverters 2, 3, and 4 to obtain the minimum total propagation delay, how would you choose the transistor widths? What would the total propagation delay be then? VDD VDD VDD VDD

Wp1 = 3 m Wn1 = 1 m Cg1 = 1 fF

Wp2 = 15 m Wn2 = 5 m

Wp3 = 60 m Wn3 = 20 m

Wp4 = 180 m Wn4 = 60 m CLoad = 1.3 pF

Figure 1