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At Dip Erg TD
At Dip Erg TD
WEBC
2007
121
WebCT
2007
. ,
. , .
,
121
.
. , 121
,
.
,
.
,
.
.
.
, ,
.
:
,
,
.
,
NOT, AND, OR, XOR, NAND, NOR, Boolean
( Boole
Karnaugh), , , flip-flops
.
,
WebCT.
.
............................................................... 1
1.1
1.2
1.3
,
.......................................................... 5
2.1
2.2
2.3
2.4
11
2.5
13
........................ 16
3.1
16
3.2
17
3.3
20
3.4
22
3.5
23
..................................... 26
4.1
26
4.2
27
4.3
32
4.4
35
4.5
38
....... 40
5.1
40
5.2
41
5.3
47
5.4
54
5.5
56
......... 58
6.1
58
6.2
59
6.3
65
6.4
69
6.5
70
.................................... 72
7.1
72
7.2
73
7.3
80
7.4
88
7.5
92
10
.... 97
8.1
97
8.2
98
8.3
101
8.4
104
8.5
106
........................................ 110
9.1
110
9.2
111
9.3
113
9.4
115
9.5
116
,
............................................ 117
11
10.1
117
10.2
118
10.3
120
10.4
122
10.5
123
...................................................... 124
11.1
124
11.2
125
....................................................................................... 126
CD .......................................................................... 127
Folder:
Folder: 1
Folder: 2
Folder: 3
Folder: 4
Folder: 5
Folder: 6
Folder: 7
Folder: 8
Folder: 9
Folder: 10
Folder: 11
Folder:
1.1
1.2
1.3
1.1
. ,
, ,
.
.
.
.
,
.
. ,
,
,
...
.
1.2
.
, 121 .
,
.
1.3
:
1
.
2
,
.
3
.
4
.
5
.
6
, , BCD
.
7
flipflops, latches,
.
8
,
.
9
,
.
10
. .
11
.
.
2.1
2.2
2.3
2.4
11
2.5
13
2.1
,
. , ,
.
,
.
, .
2, 8,
10, 16
.
,
5
2.2
/ :
1. 77.510 .
. 1001101.1 ()
. 1001001.1
. 1011110.1
. 1000110.1
2. 1001.1112 .
. 10.103
. 16.511
. 12.312
. 9.875 ()
3. 170.510 .
. 98.1
. 95.5
. .8 ()
. .2
4. 1001 0001.0110BCD .
. 90.8
. 91.6 ()
. 93.2
. 90.9
5. 2 :
55F
189
. 69E ()
. 6D8
. 5E8
. 7CD
6. 2 :
111000
101001
. 011111
. 010101
. 001111 ()
. 100100
7. AB 5 SCII .
ASCII 4116 , 2016
2 3216 .
. 00101011 00101100 00010100 00100001
. 01011011 01110100 00111000 00110011
. 01000001 01000010 00100000 00110101 ()
. 01000011 01000100 00100000 00110011
2.3
/ :
1. 64.62510 .
. 1000000.100
. 1000000.001
. 1000000.101 ()
. 1000001.011
8
2. 110.1012
. 6.625 ()
. 6.1
. 5.625
. 7.1
3. 105.410
. 70.1
. 69.4 ()
. 69.2
. 71.4
4. 1010 1111.01012 (
)
. 8.1
. D.2
. E.5
. F.5 ()
5. 2 :
10001
11011
. 011111 ()
. 010101
. 001111
. 100100
6. 2 :
11110
110
. 10010100
. 10000110
. 11000010
. 10110100 ()
7. CBD ASCII
even parity bit
m.s.b (most significant bit) ASCII.
. ASCII
4116
. 1100001 11000010 010000011
. 11000011 01000010 01000100 ()
. 01000011 01000011 11000011
. 10000001 100000010 10000011
10
2.4
1.
77 /2 = 38 1
/2 = 19 0
/2 = 9 1
/2 = 4 1
/2 = 2 0
/2 = 1 1
/2 = 0 1 = 11011012
1 * 2-1 = 0.5
1101101.12
2.
11
3.
170 /2 = 85 0
/2 = 42 1
/2 = 21 0
/2 = 10 1
/2 = 5
/2 = 2
/2 = 1
/2 = 0
1 = 1010 10102
1*2-1= 0.5
1010 1010.12 = .816
.816
4.
5.
A+B
Carry 010
A
55F +
B
189
-------------6E9
6E916
12
6.
A-B
borrow 011110
A
111000 B
101001
-------------------001111
0011112
7.
2.5
1.
64 /2 = 32 0
/2 = 16 0
/2 = 8 0
/2 = 4 0
/2 = 2 0
/2 = 1 0
/2 = 0 1 = 1000000
13
0.625
|
1 | 0.25
0 | 0.5
1|0
1000000.1012
2.
3.
105 /2 = 52 1
/2 = 26 0
/2 = 13 0
/2 = 6
/2 = 3
/2 = 1
/2 = 0
0 = 0110 1001
5.
A+B
Carry 100110
A
10001 +
B
11011
----------------101100
10110
6.
A*B
A
B
11110 *
110
--------------00000
11110 +
111100
-----------------10110100
10110100
7.
15
3.1
16
3.2
17
3.3
20
3.4
22
3.5
23
3.1
,
AND, OR NOT, ,
. Boolean
Boolean
.
Minterm Maxterm
. ,
sum-of-products product-of-sums,
.
16
: literals
.
K-maps 2 4
. maps
, , sum-of-products ,
product-of-sums dont-care
. ,
, 3 .
,
, AND OR,
NAND NOR, , ,
exclusive-OR exclusive-NOR .
3.2
/ :
1. Boole
[1].
F = ABC + ABC + AC
. C + C
. B ( A + C )
. 1
. AB + AC ()
17
2. Boole [1].
F = ( A + C) (B + C) (A+ BC)
. A + B + C
. 1
. AC + BC + A (B + C)
. AC + BC + A (B + C) ()
3. [1]:
XY+YZ+XZ+XY+YZ
. XY+XZ+YZ
. XY+ XZ +YZ ()
. +
. + +
4. Venn F=
[4].
. ()
18
19
5. . ;
. : a
b = ab + ab [4].
. a
b = (a
. ab = a
b) ()
. a + b = a b
. a +a = 0
3.3
/ :
1. Boole
[1].
F = AB + BC + A + C
. 1 ()
. 0
. AB + C
. A + B
2. . = 0, +=1 + =
le [1].
F = (A + C) (A + B) (B + C)
. BC ()
. B + C
. A + B
. 0
20
3. 3 literals :
XY+XYZ+XY [1].
. +
.
. + ()
. +
4. f( ,
[4].
.
+
+
.
.
.
) = m(1,4,7) +d(2,5)
()
5. g( , ,
m(0,1,2,4,5,7,8,9,10,12,14,15) [4].
.
+
+
+
+
+
21
)=
()
3.4
1. F = ABC + ABC +AC
= AB (C + C) + AC
= AB (1) + AC
= AB + AC
2. F = ( (A + C) (B + C) (A + BC) )
= AC + BC + A(B+C)
3. XY+YZ+XZ+XY+YZ
= XY+YZ(X+X)+XZ+XY+YZ
= XY+XYZ+XYZ+XZ+XY+YZ
= XY(1 + Z)+XYZ+XZ+XY+YZ
= XY+XZ(1 + Y)+XY + YZ
= XY+XZ+XY(Z + Z)+YZ
= XY+XZ+XYZ+YZ(1 + X)
= XY+XZ(1 + Y)+YZ
= XY+XZ+YZ
4.
5.
(a b)
= (a b + ab) = (a b) (ab)
= (a+b) (a + b)
=ab + ba + aa + bb = ab +ba + 0 + 0
=ab + ba
22
=(a
=(a
b)
) = (a
: a
b = (a
b)
3.5
1.
F = + BC + AB + BC
= (A + A) B + B (C + C)
= (1) B + B (1)
= B + B
=1
2.
F = (A + C) (A+ B) (B+C)
= ( (A.A) + (AB) + (AC) + (BC) ) (B + C)
= ( (0 + 0 + (AC) + (BC) ) (B + C)
= (A + B) C (B + C)
= (A + B) (CB + C)
= (A + B) C = BC
23
3.
XY+XYZ+XY
= X+XYZ
= (X+XY)(X+Z)
= (X+X)(X+Y)(X+Z)
= (X+Y)(X+Z)
= X+YZ
4. 1 Karnaugh.
0 1.
Karnaugh :
f( ,
)=
24
5.
Karnaugh :
g( ,
)=
25
4.1
26
4.2
27
4.3
32
4.4
35
4.5
38
4.1
, :
design hierarchy top-down design. , , computeraided design hardware description languages (HDLs)
.
.
three-state buffers
transmission gates.
,
manual computer-aided
.
26
4.2
/ :
1. [1].
. 16
. 13 ()
. 20
. 7
27
2. = bd
a
c. XOR NAND
[4].
. ()
28
29
4. LED 7-
9
BCD ( MSB D).
,
NOT. [4].
.
30
. ()
31
4.3
/ :
1. NAND tpd =
0.084 ns.
[1].
. 0.336 ns ()
. 0.405 ns
. 0.42 ns
. 0.252 ns
32
2.
NAND NOR [1];
.
. ()
33
3.
BCD [1].
. F= AB + AC
. F = AB + AC ()
. F = A + B + C
. F = ABC + B
4.
AND/OR,
[4].
34
4.4
1.
( ) . : 4
(3 AND 1 OR) 9 .
: 4+9= 13.
2. X = bd
(a
b) = (ab + ab)
= (a + b) (a + b)
= a a + ab + ab + bb
= a b
= a b
a
(X) = [ ((bd)
= [(bd + z)]
z]
= [(bd)
z
= (bd)
= (bd)
[a c]
= (bd)
(a + c)
c)]
35
3. 1000 .
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F3
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
F2
0
1
1
1
1
0
0
0
0
1
X
X
X
X
X
X
4.
36
F1
1
0
0
1
1
0
0
1
1
0
X
X
X
X
X
X
F0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
karnaugh:
:
D = BCD = (B + C + D)
:
C = BC + BC
:
37
4.5
1.
4 NAND, 4 0.084.
2. X
NAND
NOR.
.
3.
BCD F
= AB + AC.
38
4. H
AND/OR,
.
39
5.1
40
5.2
41
5.3
47
5.4
54
5.5
56
5.1
, functional blocks
. decoders,
, encoders.
,
decoders, multiplexers .
OR, decoders
.
, VHDL Verilog
.
40
5.2
/ :
1.
F = ( , , , , , , , ) = ( 1,0,0,1,0,1,1,0) [1].
.
. ()
41
42
. ()
3. PLA
3-bit
[4].
. ()
43
44
4. 32 6 ROM
6-bit BCD
[1].
.
. ()
45
5. VHDL .
F [1].
. ()
begin
F <= (X and Z) or ((not Y) and Z);
end;
.
begin
F <= (Y and X) or ((not Y) and Z);
end;
.
begin
F <= (X and Z) or Z);
end;
.
begin
F <= (X or Z) or ((not Y) and Z);
end;
46
5.3
/ :
1.
F = ( , , , , , , , ) = ( A,A,0,1,A,A,1,1) [1].
.
. ()
47
2. 4-input
, , ,
,
V.
[1].
. ()
48
3. :
F(A,B,C,D) = m (1,3,4,11,12,13,14,15) 4-to-1 line
. 4
C D.
F
C D, 4
AB= 00,01,10,11.
[1].
.
. ()
49
4. :
,
MUX 4:1 NAND [4].
50
51
. ()
5.
BCD
0 [4].
.
52
. ()
53
5.4
1.
VDD 0
.
2. :
54
+
+
+
V=
= ( + )
=
.
3. PLA
3-bit .
4. 32 6 ROM 6-bit
BCD .
5. Boole
F =(((Z(X(XY))) ((Y(XY))) ( Z(Y(XY))))
Boole
F = (XZ) + ((Y) Z)
.
55
5.5
1.
.
2.
3.
F:
56
4. :
= ( + C) = (AB) (AC) = (A + B) (A + C)
= A + AC + AB + BC = A + BC
= ABC + ABC + ABC + ABC + ABC
=
. NAND G0, G1
, NAND
OR.
.
5.
BCD 0
:
57
6.1
58
6.2
59
6.3
65
6.4
69
6.5
70
6.1
. , binary adders,
carry lookahead adder.
, 2s 1s
complement,
.
, shifting.
contraction.
58
6.2
/ :
1. 0111011110
1 [1].
. 493
. 478 ()
. -305
. -10
2. 1111111110
2 [1];
. 478
. -200
. -2 ()
. -10
59
3. [1];
.
. ()
60
4.
4-bit .
AND [1].
.
61
. ()
62
5.
63
addersubtractor S
A [4].
. ()
0
0
1
1
0
1
1
0
0
1
1
1
0
0
0
1
0
1
0
0
0
1
1
1
1
0
1
1
1
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
1
1
1
1
0
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
0
0
1
1
1
1
64
.
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
1
0
1
1
0
0
1
0
1
0
6.3
/ :
1. 1011100111
1 [1];
. -100
. 478
. -280 ()
. 139
2. -95
12 bits 2 [1].
. 100001011111
. 111110100000
. 111110101001
. 111110100001 ()
65
3.
n bits Overflow [4];
. Overflow =
. Overflow =
()
. Overflow =
. Overflow =
4.
bits,
bits [4].
. ()
66
67
5. (+100) + (-5)
8-bit
2 [1].
. 01011111 ()
. 11111010
. 11010101
. 01010110
68
6.4
1. 1
MSB 0 1. 0
.
0111011110 = 478
2. 2
MSB 0 1. 1
2
- . 1111111110 = 0000000010 = -2
3.
=
A=
A
=
=
=>
=B+C
B=
C= A
= (
= (
=>
y)
)
+
+
.
4. 3 4
bit AND .
69
5.
0
0
1
1
0
1
1
0
0
1
1
1
0
0
0
:
1
0
1
0
0
0
1
1
1
1
6.5
1. 1
MSB 0 1. 1
1
-.
1011100111 = 0100011000 = -280.
2. 95 = 000001011111
-95 2 111110100001
3.
,
Cn-1, Cn .
bits , overflow 0.
.
70
4.
= +
=
=
=
+
=
=
+
=
+
=
+
+
.
5.
100
+ (- 5)
----------= 95
01100100
+ 11111011
----------------= 01011111
71
7.1
72
7.2
73
7.3
80
7.4
88
7.5
92
7.1
,
. flip-flops
D, SR, JK T. , masterslave, flip-flops.
. ,
.
, ,
,
VHDL Verilog .
72
7.2
/ :
1. 3 D flip-flops A,B C
X. :
= (BC + BC)X +(BC + BC)X
=A
=B
[1].
.
73
74
. ()
3. 7.6()
S R 1,
0.
SR
( setdominant latch)
S=R=1
( set).
[4].
To SR :
76
. ()
77
4. JK flip-flop T flip-flop
[4].
78
. ()
79
7.3
/ :
1.
3 D flip-flops A,B C
X. :
= (BC + BC)X +(BC + BC)X
=A
=B
X = 0 [1].
80
. ()
81
2.
SR NAND.
AND OR
[4].
82
. ()
83
3.
D flipflops [4].
.
84
85
. ()
4.
FF , , .
Q
FF1 (. Q1
) [1].
86
. ()
87
7.4
1.
, input
, .
:
2.
Karnaugh
:
88
.
= AB + AX + BX
= AX + BX
3.
Y1 2
. R=S=1 set dominant latch
(. 1)
:
Karnaugh Y1 Y2 .
1 = CLK S R
89
Y2 = CLK S
:
4.
T Flip-Flops JK Flip-Flop.O
JK Flip-Flop :
T Flip-Flop :
90
Flip-Flop Q(t).
arnaugh :
T = JQ + KQ
:
91
7.5
1.
, input
, .
000 100 =0.
100 110
=0. :
92
2.
NAND,
NOR NAND
, 1
2
2 AND.
Karnaugh Y1 Y2,
.
1 = Clk + S = (Clk S)
Y2 = (Clk R)
, SR
NAND .
93
3.
D flip-flops flip-flop
.
:
D1 = y1(t+1)
D2= y2(t+1)
D1(y2,y1,w) =
D2(y2,y1,w) =
Z(y2,y1,w) =
D1 = y2
y1
D2 = y2 y1 +y2w
94
z = y1 y2
,
:
95
4.
96
8.1
97
8.2
98
8.3
101
8.4
104
8.5
106
8.1
, ,
flip-flops .
flip-flops
. , shift
.
,
, . , multiplexers
.
97
8.2
/ :
1. bitwise AND, OR
XOR 8-bit 10011001 11000011 [1].
. AND : 10101001
OR: 10001001
XOR : 10101010
. AND : 10111001
OR: 10001011
XOR : 10111010
. ()
AND : 10000001
OR: 11011011
XOR : 01011010
. AND : 11011011
OR: 01011010
XOR : 10000001
2. D flip-flops
0,1,2,
[1].
. ()
=C
= BC
.
= C
= BC
=
= BC
= C
= BC
98
3.
: R2 R1, R1 R2 [1].
.
. ()
99
Carry 1, 0 (
), ,
.
Borrow, .
, Ck-Up,
Ck-Down 1. ,
Ck-Down
Ck-Up 1. PA, PB, PC, PD,
. O Load 0
MR (Master Reset) 1.
(t1, t2) Led
[4]:
. 9 11 sec.
. 5 10 sec.
. 3 8 sec.
. ()
10 15 sec.
100
8.3
/ :
1. Shift Left Shift
Right 8-bit 01010011[1].
. ()
sl 10100110
sr 00101001
. sl 10101110
sr 01101001
. sl 11101110
sr 00101001
. sl 11101100
sr 01101011
2. D flip-flops
0,1,2,3,4,5
[1].
.
= BC
= ABC
= C
. ()
= BC + AC
= ABC + BC
= C
.
= BC +
= AB
= C
= C +
= BC
= C +
101
3.
:
: R0 R1
: R3 R1, R1 R4, R4 R0
: R2 R3, R0 R2
: R2 R4, R4 R2
[1].
. ()
Destination Source Registers
R0 R1, R2
R1 R4
R2 R3, R4
R3 R1
R4 R0, R2
Source Registers Destination
R0 R4
R1 R0, R3
R2 R0, R4
R3 R2
R4 R1, R2
. Destination Source Registers
R0 R1
R1 R4
R2 R3, R4
R3 R1
R4 R0, R2
Source Registers Destination
R0 R4
R1 R0, R3
R2 R0
R3 R2
R4 R1, R2
102
103
. ()
= BC
= BC
= AC
= AC
= AB+AB
= A B+ AB
.
= BC
= BC
= AC
= AC
= AB+AB
= A B+ AB
= C
= B
= AC
= AC
= AB
= A B+ AB
= BC
= BC
= AC
= AC
= A B+ AB
8.4
1. :
1001 1001
1100 0011
--------------1000 0001
1101 1011
0101 1010
AND
OR
XOR
104
2.
.
=C
= BC
3. T
: R2 R1, R1 R2 :
C3
R1 R2.
R1 R2 R2
R1.
4.
=0101,
BORROW LOAD. ,
. , . 9
sec, 0000. BORROW 0
105
, 10 sec,
. , LED 10 15 sec.
8.5
1. shift left
1 bit 0.
shift right 1 bit
0.
:
01010011
--------------1010 0110
sl
01010011
--------------0010 1001
sr
2.
.
106
:
= BC + AC
= ABC + BC
= C
3.
,
: R0 R1
: R3 R1, R1 R4, R4 R0
: R2 R3, R0 R2
: R2 R4, R4 R2
, ,
.
, , ,
.
:
Destination Source Registers
R0 R1, R2
R1 R4
R2 R3, R4
R3 R1
R4 R0, R2
Source Registers Destination
R0 R4
R1 R0, R3
R2 R0, R4
R3 R2
R4 R1, R2
107
4. FF
, ,
MSB. :
karnaugh
.
=BC
=BC
=AC
108
=AC
=AB+AB
=A B+ AB
109
9.1
110
9.2
111
9.3
113
9.4
115
9.5
116
9.1
, 2
: random-access memory (RAM) read-only memory
(ROM).
.
read write ,
. .
DRAM ,
.
110
9.2
/ :
1. 16 x 8
bits .
- [1]:
. A = 14, D = 8 ()
. A = 11, D = 7
. A = 15, D = 4
. = 14, D= 10
2. bytes 64M x 32 [1].
.
.
.
()
111
3. 64 x 16 RAM chip
.
[1].
. = 1000
= 2
. = 501
= 1
. = 523
= 90
. ()
= 500
= 0
4. DRAM 14 pins
1 bit .
DRAM [1].
. 64
. 128 M ()
. 512
. 1024
112
9.3
/ :
1. 64 x 32
bits .
- : [1]
. A = 14, D = 8
. A = 26, D = 32 ()
. A = 20, D = 15
. = 16, D= 10
2. (835)10
(15103)10. 10 bit
16-bit [1].
Binary
0000000000
0000000001
0000000010
1111111101
1111111110
1111111111
Memory Address
Decimal
0
1
2
.
.
.
1021
1022
1023
. 11 0100 0010
0011 1010 1111 1110
. ()
11 0100 0011
0011 1010 1111 1111
113
Memory contents
10110101 01011100
10101011 10001001
00001101 01000110
.
.
.
10011101 00010101
00001101 00011110
11011110 00100100
. 11 0101 0010
0011 1110 1111 1110
. 11 0000 0010
0111 1010 1111 1110
3. 64 x 16 RAM chip
. Ram cell
AND
[1].
. ()
: 1024
: 64
AND : 1088
. : 64
: 1024
AND : 1088
. : 1048
: 32
AND : 1080
. : 512
: 32
AND : 542
4. DRAM 128 ms 4096 .
. pins
DRAM [1].
. ()
: 31.25 s
pins : 12
114
. : 30.24 s
pins : 11
. : 15.50 s
pins : 10
. : 40.25 s
pins : 9
9.4
1. 16 x 8
bits
24 x 210 214 ,
14 . bits
8, 8 .
A = 14, D = 8
2. bits 64M x 32 26 x 210 x
210 x 25 = 231. byte 8 bits, 23 bits.
bytes
231 / 23 , 228.
3. 32000 0111110100 000000.
10 bits 6
. 500
0.
4. 14 pins 13 pins
. 27 pins
= 128 .
115
9.5
1. 64M x 32
bits .
,
26 x 210 x 210
26 . bits
32, 32 .
A = 26, D = 32.
2. 835 15103 .
(835)10 = (11 0100 0011)2 (15103)10 = (0011 1010 11111111)2
3. O bits =
1024.
= 10 1024
AND
= 1024.
= 6 64 AND
= 64
AND 1024 +
64=1088.
4. 128 ms 4096
128 ms /
4096 = 31.25 s.
4096 =
12 pins.
, DRAM
116
10
,
10.1
117
10.2
118
10.3
120
10.4
122
10.5
123
10.1
, datapaths,
.
,
,
: instruction fetch instruction execution.
117
10.2
/ :
1. 32-bit
32 .
110 .
opcode,
.
. bits
opcode [1].
. Opcode : 7 bits ()
. Opcode : 9 bits
. Opcode : 10 bits
. Opcode : 20 bits
2. 32-bit
32 .
110 .
opcode,
.
. bits
[1].
. :23 bits
. : 15 bits
. : 20 bits ()
. : 7 bits
118
3. 8-bit ALU
bits N(), Z( ),
V() C() [1].
. C =
V=
Z=
N=
+ +
. ()
C=
V=
Z=( + +
N=
. C =
V=
Z=( + +
N=
. C =
V=
Z=
N=
+ + + +
+ + + + )
+ + + + )
+ + +
+ + +
119
10.3
/ :
1. 32-bit
32 .
110 .
opcode,
.
.
,
[1].
. : 220 ()
. : 230
. : 210
. : 240
2. 32-bit
32 .
110 .
opcode,
.
.
,
[1].
. : -220 220-1
. : -219 219-1 ()
. : -29 29-1
. : -23 23-1
120
3.
[1]:
=0
F=A+B()
F=A()
F=B()
F=A+B
00
01
10
11
. ()
= +A
Y = B +
. =
Y=B
+
+
. =
Y = B +
. =
Y=B
+A
+
121
=1
F=A+B+1
F=A+1()
F=B+1()
F=A+B+1()
10.4
1. 110 128
. 128 =
opcode 7 bits.
2. 110 128
. 128 =
opcode
7 bits. 32
. bits
32, 20 bits .
3. bits
: N(), Z(), V() C ()
C =
V =
+
xor Z = ( + +
+ + + + )
1. N =
bit (MSB).
.
122
10.5
1. 20 bits ,
.
2. 20 bits .
-219 219-1.
3.
:
= +A
Y = B +
123
11
11.1
124
11.2
125
11.1
.
.
,
.
.
. .
( ),
121- .
124
11.2
.
.
WebCT
.
WebCT
.
, , ,
121-
, .
.
125
[1]. M. Morris Mano and Charles R. Kime, Logic and Computer Design
Fundamentals (Third Edition), Pearson Prentice Hall, New Jersey, 2004.
[2]. Donald P. Leach and Albert Paul Malvino,
(5 ), . ., 1996.
[3]. Schaums outline series,
(2 ), . ., 1989.
[4]. ,
.
: http://www.electronics.tuc.gr/ace111_en.htm
126
CD
.
folders,
.
127