Topics

Basics of register-transfer design:

data paths and controllers; ASM charts.

Modern VLSI Design 3e: Chapter 8

Copyright 1998, 2002 Prentice Hall PTR

Register-transfer design


A register-transfer system is a sequential machine.  Register-transfer design is structural complex combinations of state machines may not be easily described solely by a large state transition graph.  Register-transfer design concentrates on functionality, not details of logic design.
Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 8

Register-transfer system example

A register-transfer machine has combinational logic connecting registers:
Q D

combinational logic

combinational logic

combinational logic

Modern VLSI Design 3e: Chapter 8

Copyright 1998, 2002 Prentice Hall PTR

Block diagrams
Block diagrams specify structure:
wire bundle of width 5

Modern VLSI Design 3e: Chapter 8

Copyright 1998, 2002 Prentice Hall PTR

Register-transfer simulation


Simulates to clock-cycle accuracy. Doesnt guarantee timing.  Important to get proper function of machine before jumping into detailed logic design. (But be sure to take into account critical delays when choosing register-transfer organization.)
Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 8

Simulation coding


Hardware description languages are typically supported by a simulation system: VHDL, Verilog, etc.
Simulation engine takes care of scheduling events during simulation.

Can hand-code a simulation in a programming language.

Must be sure that register-transfer events happen in proper order.

Modern VLSI Design 3e: Chapter 8

Copyright 1998, 2002 Prentice Hall PTR

Sample VHDL code

sync: process begin wait until CLOCKevent and CLOCK=1; state <= state_next; end process sync; combin: process begin case state is when S0 => out1 <= a + c; state_next <= S1; ... end process combin;
Modern VLSI Design 3e: Chapter 8

sync process models registers combin process models combinational logic

Copyright 1998, 2002 Prentice Hall PTR

Sample C simulator
while (TRUE) { switch (state) { case S0: x = a + b; state = S1; next; case S1: ... } }

loop executed once per clock cycle each case corresponds to a state; sets outputs, next state

Modern VLSI Design 3e: Chapter 8

Copyright 1998, 2002 Prentice Hall PTR

Data path-controller systems



One good way to structure a system is as a data path and a controller:

data path executes regular operations (arithmetic, etc.), holds registers with dataoriented state; controller evaluates irregular functions, sets control signals for data path.

Modern VLSI Design 3e: Chapter 8

Copyright 1998, 2002 Prentice Hall PTR

Data and control are equivalent



We can rewrite control into data and visa versa:

control: if i1 = 0 then o1 <= a; else o1 <= b; end if; data: o1 <= ((i1 = 0) and a) or ((i1 = 1) and b);

Data/control distinction is useful but not fundamental.

Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 8

Data operators


Arithmetic operations are easy to spot in hardware description languages:

x <= a + b;

Multiplexers are implied by conditionals. Must evaluate entire program to determine which sources of data for registers.  Multiplexers also come from sharing adders, etc.

Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR

Conditionals and multiplexers

if x = 0 then reg1 <= a; else reg1 <= b; end if;
code register-transfer
Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR

Alternate data path-controller systems

controller data path

controller data path

controller data path

one controller, one data path

two communicating data path-controller systems

Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 8

ASM charts


An ASM chart is a register-transfer description.  ASM charts let us describe function without choosing a partitioning between control and data.  Once we have specified the function, we can refine it into a block diagram which partitions data and control.
Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 8

Sample ASM chart

Modern VLSI Design 3e: Chapter 8

Copyright 1998, 2002 Prentice Hall PTR

ASM state


An ASM state specifies a machine state and a set of actions in that state. All actions occur in parallel.
s1 x=a+b y=c-d+e o1 = 1

name of state (notation only)

Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR

Actions in state


Actions in a state are unconditionally executed.  A state can execute as many actions as you want, but you must eventually supply hardware for all those actions.  A register may be assigned to only once in a state (single-assignment rule).
Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 8

Implementing operations in an ASM state

state with one addition two additions requires two adders

Modern VLSI Design 3e: Chapter 8 Copyright 1998, 2002 Prentice Hall PTR

Sequences of states


States are linked by transitions.  States are executed sequentially. Each state may take independent actions (including assigning to a variable assigned to in a previous state).
s1 x=a+b s2 x=c+d y=a+d
Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 8

Data paths from states



Maximum amount of hardware in data path is determined by state which executes the most functionality.  Function units implementing data operations may be reused across states, but multiplexers will be required to route values to the shared function units.
Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 8

Function unit sharing example

mux allows + to compute a+b, a+c

Modern VLSI Design 3e: Chapter 8

Copyright 1998, 2002 Prentice Hall PTR

Conditionals


Conditional chooses which state to execute next based on primary input or present state value.  Can be drawn in either of two ways:
F

x
00
Modern VLSI Design 3e: Chapter 8

a=b
T 10 11
Copyright 1998, 2002 Prentice Hall PTR

01

Execution of conditionals


An ASM chart describes a Moore sequential machine. If the logic associated with an ASM chart fragment doesnt correspond to a legal sequential machine, then it isnt a legal ASM chart.  Conditional can evaluate only present state or primary input value on present cycle.
Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 8

Implementing an ASM branch in a Moore machine

ASM chart

state transition graph of controller

Modern VLSI Design 3e: Chapter 8

Copyright 1998, 2002 Prentice Hall PTR

Mealy machines and ASM



Mealy machine requires a conditional output.  ASM notation for conditional output:
0

i1

y=c+d

Modern VLSI Design 3e: Chapter 8

Copyright 1998, 2002 Prentice Hall PTR

Extracting data path and controller



ASM chart notation helps identify data, control.  Once you choose what values and operations go into the data path, you can determine by elimination what goes into the controller.  Structure of the ASM chart gives structure of controller state transition graph.
Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 8

Data path-controller extraction

Modern VLSI Design 3e: Chapter 8

Copyright 1998, 2002 Prentice Hall PTR