I.

tng chung:

1. Trong cng nghip ngy nay, chun truyn thng RS232 khng th p ng c nhu cu truyn thng na v ng truyn khng cn bng (cc tn hiu u ly im chun l ng mass chung, b nh hng ca nhiu tc ng) do tc truyn v khong cch truyn b gii hn (khong cch truyn thng ti a 100m). V vy p ng nhu cu truyn thng cng nghip, ngi ta s dng chun truyn thng RS485 khi cn tng khong cch v tc truyn thng (khong cch truyn thng ti a 1200m v vn tc truyn ln n 10 Mbits/s). Nguyn nhn m RS 485 c th tng tc v khong cch truyn thng l do RS 485 s dng phng php truyn 2 dy vi sai (v 2 dy c c tnh ging nhau, tn hiu truyn i l hiu s in p gia 2 dy do loi tr c nhiu chung). Mt khc do chun truyn thng RS 232 khng cho php c hn 2 thit b truyn nhn tin trn ng dy trong khi vi chun RS 485 ta c th ni 32 thit b thu pht trn 2 dy. 2. ti ca n xut pht t tng kt hp s dng chun truyn thng RS232 v RS485 iu khin thu thp v x l d liu, thng tin trong cng nghip.Chng ti s dng vi iu khin master xut a ch n cc vi iu khin slave, vi iu khin slave s thu thp d liu thng tin c ci t sn sau truyn tn hiu tr v master. II. Linh kin s dng trong mch: 1.AT89C51: y l linh kin vi iu khin 8 bit vi 4 Kbytes b nh ni c kh nng lp trnh c v c kh nng xa chng trnh bng in. * CPU 8 bit c ti u ha cho cc ng dng iu khin * Cc kh nng x l cc bin Boole m rng * Vng a ch nh chng trnh 64K * Vng a ch nh d liu 64K * 128 byte d liu Ram trn chip * 32 ng I/O 2 chiu v c th nh a ch ring r * 2 b m,mch nh th 16 bit * UART song cng (full duplex) * Cu trc ngt 5 vector / 6 ngun vi 2 cp u tin * Mch dao ng xung nhp trong chip

Sau y l s khi ca AT89C51:

V y l s chn ca AT89C51:

ngha cc chn ca AT89C51:

*AT89C51 c tt c 40 chn trong chn 40 l chn ngun, chn 20 l chn mass, chn 18 v chn 19 c ni qua 1 thch anh 11.056Mhz to dao ng cho vi iu khin. Chn 31 EA/ c dng chn s dng Rom ni hay Rom ngoi, nu chn ny c ni ln ngun th ta s dng Rom ni cn nu ni xung mass th ta s dng Rom ngoi. * PORT 0:l 1 Port 2 chc nng ,trn cc chn 32-39. Trong cc thit k nh, n c chc nng nh cc ng I/O. i vi cc thit k ln vi b nh m rng ,n c dn knh gia bus data v bus address. * PORT 1: l cng dnh ring cho xut /nhp trn cc chn 1-8. Cng ny ch c chc nng giao tip vi cc thit b ngoi. * PORT 2:l 1 cng cng dng kp trn cc chn 21-28, c dng nh cc ng xut nhp hoc l Byte cao ca bus a ch * PORT 3: l cng cng dng kp trn cc chn 10-17 ,.vi cc chc nng: Bit P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Tn RXD TXD INT0 INT1 T0 T1 WR RD a ch bit B0H B1H B2H B3H B4H B5H B6H B7H Chc nng chuyn i D liu nhn cho Port nt D liu pht cho Port nt Ngt 0 bn ngoi Ngt 1 bn ngoi Ng vo Timer/Counter 0 Ng vo Timer/Counter 1 Xung ghi b nh data ngoi Xung c b nh data ngoi

* PSEN :l TH ra trn chn 29. N l TH iu khin cho php b nh chng trnh m rng v thng c ni n chn OE ca 1 EPROM . 2.IC to ngun p chun dng 7805: y l IC t chnh nh to ra ngun p chun dng +5V cung cp cho mch vi iu khin. Sau y l s IC 7805.Chn 1 ni mass, chn 2 l ng vo ca p ngun, chn 3 l ng ra +5V cp in cho vi iu khin v cc linh kin in t khc.

3.IC to ngun p chun m 7905: y l IC c chc nng ging nh IC 7805 nhng n to ra p chun m -5V nhm cung cp p cho cc linh kin hay cc module cn s dng ngun p m hay ngun p lng cc. Sau y l 3 dng chn cu to v chc nng tng chn ca IC 7905 ngoi th trng.

4.IC Max 232: Max 232 dng chuyn tn hiu logic +5V ca vi iu khin sang tn hiu ca chun truyn thng RS 232 v truyn i trn ng dy RS232.

Max 232 gm c 2 b pht chuyn i tn hiu TTL ng vo thnh tn hiu RS 232 ng ra v c 2 b thu nhn tn hiu RS 232 ng vo v chuyn i thnh tn hiu CMOS tng ng ng ra. 5.IC Max 485: Tht ra y n thun ch l 1 b chuyn i t tn hiu ca chun giao tip RS 232 sang tn hiu ca chun giao tip RS 485 c th truyn tn hiu i trn ng dy RS 485 v t c th truyn tn hiu i xa v nhanh c. y l s chn ca Max 485:
U 6 7 A A 8 8 R R D 1 O 2 E 3 E 4 D I VC C X 4 8 5 5 G N D M A

Max 485 gm b li v b thu, tn hiu vo b li D logic TTL i thnh 2 tn hiu A v A\ , khi tn hiu iu khin DE mc thp th 2 chn AA\ cch ly vi vi mch. Tn hiu vo b thu l A v A\ , tn hiu ra R logic TTL ty thuc hiu in p gia A v A\ , khi RE\ logic 1 th R cch ly vi vi mch. Mng 485 lm vic theo ch master-slave, master cho DE mc 1 truyn d liu, cn cc slave c DE=0, RE\=0 ch nhn d liu. Khi master mun nhn d liu th DE=0, RE\=0 cn slave pht s c DE=1, RE\=1. Ta iu khin cc ng DE, RE\ bng tn hiu RTS hay mch nh th.

III.

Cc khi mch giao tip: 1.Khi to ngun:

y l mch dng to ra ngun p chun 5V . Ta s dng IC 7805 to ra p chun +5V v IC 7905 to p chun -5V. 2Khi power:

Chn B ca transistor c ni vi chn power (P1.0) ca master. Ngun 5V ni vo qua transistor C885 ri ly dng ra chn B nhm hn dng trc khi a vo master.

3.Khi reset:

Khi nhn nt reset th p 5V c ni vo chn reset ca master khi ng li h thng.

4.Khi master:

V chng trnh s dng ROM ni nn ta ni chn EA vi ngun 5V . Dng thch anh 11.056 MHz ni vo chn XTAL1 va XTAL2 to xung clock .

5.Khi giao tip: 5.1.Max232:

Ta ni chn RXD ca master voT1OUT, ni TXD ca master vo R2IN.Cc chn T1IN, R2OUT, R1OUT, T2IN dng ni vo cc chn IN ca Max485. 5.2.Max485:

Max485 dng chuyn tn hiu trn ng dy RS232 thnh tn hiu trn ng dy RS485 v dng chun giao tip ny truyn tn hiu i xa.Chn T1In ca Max232 ni vi chn RO ca Max485 v cc chn R2OUT, R1OUT, T2In c ni tng t nh hnh v. IV. Mch hon chnh:

V.

Chng trnh phn mm: 1. Gii php x l phn mm:

Gii php x l phn mm l x l tng tc v thng qua phng php lp lch , vi s giao tip ca Master v Slave nh sau:

Ta cn to mt vng siu lp(Supper Loop) lm c s x l cho mt chng trnh nhng trong C. void main(void) { /* Chun b cho tTc v X */ X_Init(); while(1) /* 'khng bao gi kt thc' (Super Loop) */ { X(); /* Thc hin tc v */ } } Trong hm main trn c tng tc v xy ra m ta cn phi x l chng. Khi nim tc v (task) cng hay c s dng bn cnh qu trnh tnh ton. C th ni, tc v l mt nhim v x l thng tin trong h thng, c th thc hin theo c ch tun hon (periodic task) hoc theo s kin (event task). Cc dng tc v qui nh trong chun IEC 61131-3 (Programmable Controllers Part3: Programming Languages) c minh ha trn hnh sau. V d : Mt tc v thc hin nhim v iu khin cho mt hoc nhiu mch vng kn c chu k trch mu ging nhau. Hoc, mt tc v c th thc hin nhim v iu khin logic, iu khin trnh t theo cc s kin xy ra. Tc v c th thc hin di dng mt qu trnh tnh ton duy nht, hoc mt dy cc qu trnh tnh ton khc nhau.

 t chc vic thc hin cc tc v c hiu qu, mt h thng thi gian thc ta cn cc phng php lp lch. Trc ht, c ch lp lch thc hin cho cc tc v c th c thc hin theo hai cch: * Lp lch tnh: th t thc hin cc tc v khng thay i m c xc nh trc khi h thng i vo hot ng. * Lp lch ng: Hm xc nh lch sau khi h thng i vo hot ng. Sau khi xc nh c c ch lp lch, Hm cn s dng mt sch lc lp lnh (strategy) p dng i vi tng tnh hung c th. C th chn mt trong nhng cch sau: * FIFO (First In First Out): mt tc v n trc s c thc hin trc. * Mc u tin c nh/ng: ti cng mt thi im, cc tc v c t cc mc u tin c nh hoc c th thay i nu cn. * Preemptive: cn gi l sch lc chen hng, tc l chn mt tc v thc hin trc cc tc v khc. * Non-preemptive: cn gi sch lc khng chen hng. Cc tin trnh c thc hin bnh thng da trn mc u tin ca chng. Vic tnh mc u tin ca mi tin trnh c thc hin theo mt trong s cc thut ton sau: * Rate monotonic: tc v no cng din ra thng xuyn cng c u tin. * Deadline monotonic: tc v no cng gp, c thi hn cui cng sm cng c u tin.

* Least laxity: tc v no c t l thi gian tnh ton/thi hn cui cng(deadline) cng ln cng c u tin. Bn cnh phng php lp lch, c ch x l thi cn t ra nhiu vn khc na nh qun l v ng b ha vic s dng ti nguyn, giao tip lin qu trnh, ... Mi h thng iu khin l mt h thi gian thc. C th ni, tt cc cc h thng iu khin l h thi gian thc. Ngc li, mt s ln cc h thng thi gian thc l cc h thng iu khin. Khng c h thng iu khin no c th hot ng bnh thng nu nh n khng p ng c cc yu cu v thi gian, bt k l h thng iu khin nhit , iu khin p sut, iu khin lu lng hay iu khin chuyn ng. Mt b iu khin phi a ra c tn hiu iu khin kp thi sau mt thi gian nhn c tn hiu o a qu trnh k thut v trng thi mong mun. Mt mng truyn thng trong mt h thng iu khin c tnh nng thi gian thc phi c kh nng truyn tin mt cch tin cy v kp thi i vi cc yu cu ca cc b iu khin, cc thit b vo/ra, cc thit b o v thit b chp hnh. Tnh nng thi gian thc ca mt h thng iu khin phn tn khng ch ph thuc vo tnh nng thi gian thc ca tng thnh phn trong h thng, m cn ph thuc vo s phi hp hot ng gia cc thnh phn . Trong thc t, yu cu v tnh thi gian thc i vi mi ng dng iu khin cng c cc c th khc nhau, mc ngt ngho khc nhau. V d:Cu trc phng php lp lich v cc mng tc v c s dng trong ny l: void main(void) { /* To scheduler */ SCH_Init_ T2(); /* Chun b cho mt tc v*/ X_Init(); /*Np thi gian cho tc v */ SCH_Add_Task(X_Update,a, b); /* Bt u scheduler */ SCH_Start(); while(1) { SCH_Dispatch_Tasks(); } } void SCH_Update(void) interrupt INTERRUPT_Timer_2_Overflow { /* Danh sch cc tc v(task) */ ... } /* Vng lu tr d liu,nu c th c vic x l din ra nhanh Tng dung lng b nh s dng cho mt tc v(task) l 7byte */

typedef data struct { /* Con tr cho tc v( task) ('void (void)' function) */ void (code * pTask)(void); /* Khong tr cho hm k tip*/ tWord Delay; /* Khong thi gian lp li mt chu trnh k tip */ tWord Repeat; /* Set ln 1 (bi scheduler)khi tc v c thc thi */ tByte RunMe; } sTask; Cc mng tc v c ng dng trong sut phng php lp lch /* Mng tc v( task) */ sTask SCH_tasks_G[SCH_MAX_TASKS]; *Vn np cc hm trong phng php lp lch: Cu trc Sch_Add_Task(Task_Name, Initial_Delay, Task_Interval); V d: SCH_Add_Task(Do_X,1000,0); Task_ID = SCH_Add_Task(Do_X,1000,0); SCH_Add_Task(Do_X,0,1000); Hm Do_X() qui tc thc thi nh sau khong lp lch l 1000 .Tc v u tin thc thi T=300 th cc tc v tip theo l 1300;2300;th ta c cu trc lnh sau: SCH_Add_Task(Do_X,300,1000); * Hm Disphatcher SCH_Dispatch_Tasks() Hm Dispatcher c nhim v khi c mt tc v sn sng th lnh SCH_Dispatch_Tasks() s cho php n chy. Hm ny c gi trong vng lp ca hm main. void main(void) { ... while(1) { SCH_Dispatch_Tasks(); } *Vn bo li ta c cc lnh sau: tByte Error_code_G = 0; sao chp cc li ny ta dng cc lnh sau: Error_code_G = ERROR_SCH_TOO_MANY_TASKS;

Error_code_G = ERROR_SCH_WAITING_FOR_SLAVE_TO_ACK; Error_code_G = ERROR_SCH_WAITING_FOR_START_COMMAND_FROM_MA STER; Error_code_G = ERROR_SCH_ONE_OR_MORE_SLAVES_DID_NOT_START; Error_code_G = ERROR_SCH_LOST_SLAVE; Error_code_G = ERROR_SCH_CAN_BUS_ERROR; bo li ta dung hm sau: SCH_Report_Status() *Cc vn bo li khi c s c . Chng ta bit rng mi con vi x l hot ng mt nhit khc nhau,khi c s thay i v nhit tc xung clock s thay i v vy cn c mt chng trnh ng b xung clock.Trong ng dng nay ta s dng chng trnh SCU SCHEDULER (RS-485) for 8051/52.Trong chng trnh ny ta s dng mt b watchdog timer s bo trn khi chu k ca con Slave c v chm(nhanh)hn so vi cc khong thi gian ta nh ngha. Khi truyn d liu gia Master v Slave m Slave khng nhn c cc thong ip kim tra t Master th timer s trn. Khi truyn d liu gia Master v Slave th timer b trn v c ch lp lch s gi hm update.V khi mt byte d liu s c chuyn n cho tt c cc Slave (thng qua UART). void MASTER_Update_T2(void) interrupt INTERRUPT_Timer_2_Overflow { ... MASTER_Send_Tick_Message(...); ... } Khi nhn d liu cc Slave c ngt ng thi lc ny vic lp lch gi hm update l trong cc Slave.V vy cc Slave s gi li cc thng ip xc nhn cho Master(thng qua UART). void SLAVE_Update(void) interrupt INTERRUPT_UART_Rx_Tx { ... SLAVE_Send_Ack_Message_To_Master(); ... }

Cu trc ca mt chui thng ip: Mi Slave c nh ngha bng mt a ch ID(0x01 n 0xFF) Mi thng ip kim tra c gi t Master n Slave c di 2 byte c gi theo tng khong (xung) ring bit.Byte u tin cha a ch ID Slave , byte th hai cha d liu ca thng ip. Tt c cc Slave s xy ra ngt khi nhn cc thng ip t Master. Khi cc Slave nhn cc thng ip vi ng a ch ID ca mnh th khi cc Slave s tr li li bng cc thng ip xc nhn. Cc thng ip xc nhn cng c 2 byte v c chuyn i theo tng khong (xung) ring bit.Byte du cha a ch ID ca Slave ,byte th hai cha thng ip tr li. Ngoi vic chuyn mt byte d liu ta cn c th chuyn nhiu thng ip. Vic truyn d liu s dng h 8051 cho php truyn 9-bit c m t nh sau

S dng UART mode 3 truyn/nhn 11-bits.Bit th 9 c truyn thng qua bit TB8 ca thanh ghi SCON v vic nhn thng qua bit RB8. Byte a ch c nhn dng bng cch set bit chung (TB8) ln 1, byte d liu th set bit v 0. Vic truyn d liu c mt khong tr gia timer trn Master v UART l c s cho ngt trn Slave.

Vn kt ni song song hoc ni tip

Giao tip thng qua RS485

2. Phn code hon chnh: #include "Main.h" #include "Port.h" #include "SCU_Bm.H" #define PRELOAD01 (65536 - (tWord)(OSC_FREQ / (OSC_PER_INST * 1063))) #define PRELOAD01H (PRELOAD01 / 256) #define PRELOAD01L (PRELOAD01 % 256) void main(void) { SCU_B_MASTER_Init_T1_T2(9600); SCU_B_MASTER_Start(); while(1) { SCH_Dispatch_Tasks(); } } void Hardware_Delay_T0(const tWord N) { tWord ms; TMOD &= 0xF0; TMOD |= 0x01; ET0 = 0; for (ms = 0; ms < N; ms++) { TH0 = PRELOAD01H; TL0 = PRELOAD01L; TF0 = 0; TR0 = 1; while (TF0 = = 0); TR0 = 0; } }

sbit RS485_Tx_Enable = P3^2; sbit RS485_Rx_NOT_Enable = P3^3; sbit WATCHDOG_pin = P1^7; sbit Network_error_pin = P2^7; tByte Tick_message_data_G[NUMBER_OF_SLAVES] = {'1','2'}; tByte Ack_message_data_G[NUMBER_OF_SLAVES]; extern sTask SCH_tasks_G[SCH_MAX_TASKS]; extern tByte Error_code_G; static tByte Current_slave_index_G = 0; static bit First_ack_G = 1; static bit WATCHDOG_state_G = 0; static void SCU_B_MASTER_Reset_the_Network(void); static void SCU_B_MASTER_Shut_Down_the_Network(void); static void SCU_B_MASTER_Switch_To_Backup_Slave(const tByte); static void SCU_B_MASTER_Send_Tick_Message(const tByte); static bit SCU_B_MASTER_Process_Ack(const tByte); static void SCU_B_MASTER_Watchdog_Init(void); static void SCU_B_MASTER_Watchdog_Refresh(void) reentrant; static const tByte MAIN_SLAVE_IDs[NUMBER_OF_SLAVES] = {0x31,0x32}; static const tByte BACKUP_SLAVE_IDs[NUMBER_OF_SLAVES] = {0x31,0x32}; #define NO_NETWORK_ERROR (1) #define NETWORK_ERROR (0) #define SLAVE_RESET_INTERVAL 0U static tWord Slave_reset_attempts_G[NUMBER_OF_SLAVES]; static tByte Current_Slave_IDs_G[NUMBER_OF_SLAVES] = {0}; static bit Message_byte_G = 1; void SCU_B_MASTER_Init_T1_T2(const tWord BAUD_RATE) { tByte Task_index; tByte Slave_index; EA = 0; SCU_B_MASTER_Watchdog_Init(); Network_error_pin = NO_NETWORK_ERROR; RS485_Rx_NOT_Enable = 0; RS485_Tx_Enable = 1; for (Task_index = 0; Task_index < SCH_MAX_TASKS; Task_index++) { SCH_Delete_Task(Task_index); } Error_code_G = 0; for (Slave_index = 0; Slave_index < NUMBER_OF_SLAVES; Slave_index++) { Slave_reset_attempts_G[Slave_index] = 0;

Current_Slave_IDs_G[Slave_index] = MAIN_SLAVE_IDs[Slave_index]; } PCON &= 0x7F; SCON = 0xD2; TMOD = 0x20; TH1 = (256 - (tByte)((((tLong)OSC_FREQ / 100) * 3125) / ((tLong) BAUD_RATE * OSC_PER_INST * 1000))); TL1 = TH1; TR1 = 1; TI = 1; ES = 0; T2CON = 0x04; T2MOD = 0x00; TH2 = 0xEC; RCAP2H = 0xEC; TL2 = 0x78; RCAP2L = 0x78; ET2 = 1; TR2 = 1; } void SCU_B_MASTER_Start(void) { tByte Slave_ID; tByte Num_active_slaves; tByte Id, i; bit First_byte = 0; bit Slave_replied_correctly; tByte Slave_index; SCU_B_MASTER_Watchdog_Refresh(); SCU_B_MASTER_Enter_Safe_State(); Network_error_pin = NETWORK_ERROR; Error_code_G = ERROR_SCH_WAITING_FOR_SLAVE_TO_ACK; SCH_Report_Status(); for (i = 0; i < 100; i++) { Hardware_Delay_T0(30); SCU_B_MASTER_Watchdog_Refresh(); } Num_active_slaves = 0; Slave_index = 0; do { SCU_B_MASTER_Watchdog_Refresh(); First_byte = 0; Slave_ID = (tByte) Current_Slave_IDs_G[Slave_index]; TI = 0;

TB8 = 1; SBUF = Slave_ID; Hardware_Delay_T0(5); if (RI = = 1) { Id = (tByte) SBUF; RI = 0; if ((Id = = Slave_ID) && (RB8 = = 1)) { First_byte = 1; } } TI = 0; TB8 = 1; SBUF = Slave_ID; Hardware_Delay_T0(5); Slave_replied_correctly = 0; if (RI != 0) { Id = (tByte) SBUF; RI =0; if ((Id = = Slave_ID) && (RB8 = = 1) && (First_byte = = 1)) { Slave_replied_correctly = 1; } } if (Slave_replied_correctly) { Num_active_slaves++; Slave_index++; } else { if (Current_Slave_IDs_G[Slave_index] != BACKUP_SLAVE_IDs[Slave_index]) { Current_Slave_IDs_G[Slave_index] = BACKUP_SLAVE_IDs[Slave_index]; } else { Slave_index++; } } } while (Slave_index < NUMBER_OF_SLAVES); if (Num_active_slaves < NUMBER_OF_SLAVES)

{ Error_code_G = ERROR_SCH_ONE_OR_MORE_SLAVES_DID_NOT_START; SCU_B_MASTER_Shut_Down_the_Network(); } else { Error_code_G = 0; Network_error_pin = NO_NETWORK_ERROR; } Message_byte_G = 1; First_ack_G = 1; Current_slave_index_G = 0; EA = 1; } void SCU_B_MASTER_Update_T2(void) interrupt INTERRUPT_Timer_2_Overflow { tByte Task_index; tByte Previous_slave_index; TF2 = 0; SCU_B_MASTER_Watchdog_Refresh(); Network_error_pin = NO_NETWORK_ERROR; Previous_slave_index = Current_slave_index_G; if (Message_byte_G = = 0) { Message_byte_G = 1; } else { Message_byte_G = 0; if (++Current_slave_index_G >= NUMBER_OF_SLAVES) { Current_slave_index_G = 0; } } if (SCU_B_MASTER_Process_Ack(Previous_slave_index) = = RETURN_ERROR) { Network_error_pin = NETWORK_ERROR; Error_code_G = ERROR_SCH_LOST_SLAVE; if (++Slave_reset_attempts_G[Previous_slave_index] >= SLAVE_RESET_INTERVAL) { SCU_B_MASTER_Reset_the_Network();

} } else { Slave_reset_attempts_G[Previous_slave_index] = 0; } SCU_B_MASTER_Send_Tick_Message(Current_slave_index_G); for (Task_index = 0; Task_index < SCH_MAX_TASKS; Task_index++) { if (SCH_tasks_G[Task_index].pTask) { if (SCH_tasks_G[Task_index].Delay = = 0) { SCH_tasks_G[Task_index].RunMe += 1; if (SCH_tasks_G[Task_index].Period) { SCH_tasks_G[Task_index].Delay = SCH_tasks_G[Task_index].Period; } } else { SCH_tasks_G[Task_index].Delay = 1; } } } } void SCU_B_MASTER_Send_Tick_Message(const tByte SLAVE_INDEX) { tLong Timeout; tByte Slave_ID = (tByte) Current_Slave_IDs_G[SLAVE_INDEX]; if (Message_byte_G == 0) { Timeout = 0; while ((++Timeout) && (TI = = 0)); if (Timeout = = 0) { Error_code_G = ERROR_USART_TI; return; } TI = 0; TB8 = 1; SBUF = Slave_ID; }

else { Timeout = 0; while ((++Timeout) && (TI = = 0)); if (Timeout = = 0) { Error_code_G = ERROR_USART_TI; return; } TI = 0; TB8 = 0; SBUF = Tick_message_data_G[SLAVE_INDEX]; } } bit SCU_B_MASTER_Process_Ack(const tByte Slave_index) { tByte Message_contents; tByte Slave_ID; if (First_ack_G) { First_ack_G = 0; return RETURN_NORMAL; } Slave_ID = (tByte) Current_Slave_IDs_G[Slave_index]; if (RI = = 0) { Network_error_pin = NETWORK_ERROR; return RETURN_ERROR; } Message_contents = (tByte) SBUF; RI = 0; if (Message_byte_G = = 1) { if (RB8 = = 1) { if (Slave_ID = = (tByte) Message_contents) { return RETURN_NORMAL; } } Network_error_pin = NETWORK_ERROR; return RETURN_ERROR; } else {

Ack_message_data_G[Slave_index] = Message_contents; return RETURN_NORMAL; } } void SCU_B_MASTER_Reset_the_Network(void) { EA = 0; while(1); } void SCU_B_MASTER_Shut_Down_the_Network(void) { EA = 0; Network_error_pin = NETWORK_ERROR; SCH_Report_Status(); while(1) { SCU_B_MASTER_Watchdog_Refresh(); } } void SCU_B_MASTER_Watchdog_Init(void) { } void SCU_B_MASTER_Watchdog_Refresh(void) reentrant { if (WATCHDOG_state_G = = 1) { WATCHDOG_state_G = 0; WATCHDOG_pin = 0; } else { WATCHDOG_state_G = 1; WATCHDOG_pin = 1; } }

VI.

Tng kt: 1. Tng kt v tng v kh nng ng dng thc tin ca ti: Qua vic s dng kt hp 2 chun truyn thng giao tip thng dng hin nay v s dng phng thc thu thp, phn tn d liu master-slave, ta thy rng vic thu thp v phn tn thng tin c thc hin nhanh chng, d dng hn v c bit l gn nh cng 1 lc ta c th giao tip vi nhiu module trong mi quan h cht ch, c th t.Vi iu khin master c th giao tip vi khong 256 module trn ng dy truyn thng RS-485 vi thi gian thu pht d liu gia 2 module k tip nhau l khng ng k. V vy tng ca ti ny c th ng dng vo mng truyn thng trong cc nh my, x nghip gm nhiu b phn lm vic cch xa nhau m vic thu thp v phn tn thng tin theo phng thc th cng l khng kh thi. Cc b phn c trch nhim thu thp v phn tn d liu ch cn ti v tr ca master cp nht v kim sot thng tin. H ch cn thit k h thng hp l ph hp vi nhu cu v khng gian ca a im lm vic l c th giao tip vi cc b phn khc d dng v nhanh chng m li c c ni dung thng tin chnh xc. 2. Phng hng pht trin ca ti:

Ngy nay s pht trin v bo ca h thng truyn thng Internet lm bng n mt phng thc truyn thng mi nhanh hn gp nhiu ln, thng tin chnh xc v rt thun tin cho ngi lm vic. Cho nn phng hng pht trin ca ti l thng tin t vi iu khin c cp nht v truyn qua my vi tnh sau s dng h thng mng Internet thng qua a ch IP truyn thng tin n mt ngi c trch nhim cao nht bt k 1 ni no trn th gii x l v truyn thng tin ngc li. Vic ny va lm gim thiu c ngun nhn cng c nh ti ni lm vic va lm gim c khng gian nh my. Tm li phng thc ny s tr nn ph bin rng ri trong thi gian khng xa ti y.