CC M U L NH MY

L nh 1 byte khng c ton h ng OPCODE L nh 1 byte ch OPCODE Thanh ghi REG thanh ghi 1 1 REG R/M thanh ghi REG M thanh ghi MOD Ch R/M M thanh ghi ho c cch tnh d ch a ch

DISP

DATA D li u t c th i

OPCODE Thanh ghi

b nh (khng DISP) MOD REG R/M

OPCODE Thanh ghi

b nh (c DISP) MOD thanh ghi 1 1 OPCODE R/M b nh (c DISP) MOD OPCODE R/M DISP-LO DISP-HI DATA-LO DATA-HI (n u dng d li u 16-bit) DATA-LO DATA-HI (n u dng d li u 16-bit) REG R/M DISP-LO DISP-HI (n u dng DISP 16-bit)

OPCODE D li u t c th i OPCODE D li u t c th i OPCODE

M THANH GHI V CC CH
Thanh ghi REG W=1 W=0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 AX CX DX BX SP BP SI DI AL CL DL BL AH CH DH BH 0 0 0 1 1 0 1 1 SR Thanh ghi o n ES CS SS DS
MOD R/M

A CH
1 1 0 1 (BX) + (SI) + D8 (BX) + (DI) + D8 (BP) + (SI) + D8 (BP) + (DI) + D8 (SI) + D8 (DI) + D8 (BP) + D8 (BX) + D8 1 0 W=1 W=0 (BX) + (SI) + D16 (BX) + (DI) + D16 (BP) + (SI) + D16 (BP) + (DI) + D16 (SI) + D16 (DI) + D16 (BP) + D16 (BX) + D16 AX CX DX BX SP BP SI DI AL CL DL BL AH CH DH BH

0 0 (BX) + (SI) (BX) + (DI) (BP) + (SI) (BP) + (DI) (SI) (DI) D16 (BX)

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

ADD DST, SRC

REG + R/M REG ho c R/M REG R/M Khng nh t thi t (ph thu c tr DISP-LO Khng nh t thi t (ph thu c tr R/M DISP-LO Ch dng khi W = 1 DATA-HI ng MOD) DISP-HI ng MOD) DISP-HI DATA-LO Ch dng khi S:W = 01 DATA-HI

0 0 0 0 0 0 D W MOD R/M + DATA R/M

1 0 0 0 0 0 S W MOD 0 0 0 AX (ho cAL) + DATA 0 0 0 0 0 1 0 W

AX (ho c AL) DATA-LO

Hai l nh t

ng

ng th c hi n vi c c ng BH vo CL

0 0 0 0 0 0 1 0

1 1 0 0 1 1 1 1

0 0 0 0 0 0 0 0

1 1 1 1 1 0 0 1

Hai l nh ADD dng ch

a ch t

ng

ic s

0 0 0 0 0 0 0 1

1 0 0 1 0 0 0 1

0 1 0 0 0 1 0 1

0 0 1 0 0 0 1 1

1 0 0 0 0 0 1 1

1 0 0 0 0 0 0 1

0 1 0 0 0 1 0 1

0 0 1 0 0 0 1 1

1 0 0 1 0 1 1 1

D ng di v d ng ng n c a l nh c ng d li u t c th i vo AX

1 0 0 0 0 0 0 1

1 1 0 0 0 0 0 0

0 0 1 0 0 0 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 1 0 1

0 0 1 0 0 0 1 1

0 0 0 0 0 0 0 1

ADD DST, SRC

REG + R/M REG ho c R/M REG R/M Khng nh t thi t (ph thu c tr DISP-LO Khng nh t thi t (ph thu c tr R/M DISP-LO Ch dng khi W = 1 DATA-HI ng MOD) DISP-HI ng MOD) DISP-HI DATA-LO Ch dng khi S:W = 01 DATA-HI

0 0 0 0 0 0 D W MOD R/M + DATA R/M

1 0 0 0 0 0 S W MOD 0 0 0 AX (ho cAL) + DATA 0 0 0 0 0 1 0 W

AX (ho c AL) DATA-LO

MOV DST, SRC

REG R/M REG R/M Khng nh t thi t (ph thu c tr DISP-LO ng MOD) DISP-HI

1 0 0 0 1 0 D W MOD R/M DATA

1 1 0 0 0 1 1 W MOD 0 0 0 REG DATA REG DATA-LO

R/M

DISP-LO

DISP-HI

DATA-LO

DATA-HI

1 0 1 1 W Acc MEM

DATA-HI

1 0 1 0 0 0 0 W MEM Acc

ADDR-LO

ADDR-HI

1 0 1 0 0 0 1 W R/M SR

ADDR-LO

ADDR-HI

1 0 0 0 1 1 D 0

MOD 0 SR

R/M

DISP-LO

DISP-HI

IN DST, SRC
Acc Input port a ch 8-bit PORT-8 Acc Input port a ch 16-bit PORT-16

1 1 1 0 0 1 0 W

1 1 1 0 1 1 0 W

OUT DST, SRC

Input port a ch 8-bit Acc PORT-8 Input port a ch 16-bit Acc PORT-16

1 1 1 0 0 1 1 W

1 1 1 0 1 1 1 W

PORT-16 ch a trong DX