Computer Organization and Design Homework 4 Due Date: 06 Feb 2012

Take the MIPS single cycle processor developed in the textbook, and add the following instructions. Note that each instruction will require a separate datapath and control logic that extends the one in the textbook do not do one processor that does all of the following in one machine. jr ori rs rt, rs, imm16 Unconditionally jump to the instruction at the address specified by rs (see Appendix B in the textbook). Put the logical OR of register rs and the zero-extended immediate into register rt (see Appendix B in the textbook). Unconditionally jump to the instruction whose address is in register rs. Save the address of the next instruction in register rd (which defaults to 31) (see Appendix B in the textbook).

jalr rs, rd

a.)

Show the minimal changes to the single-cycle datapath (including instruction fetch) needed to support this new instruction. Show the control signal settings needed for this new instruction (Draw a table as in the textbook).

b.)