2004 9

2004

VLSI


1. VLSI
2VLSI
3. CMOS
4
5. CMOS
6.
7.
8.
9.
10LSIVLSI
2004

VLSI

2004

VLSI


DVDTV

12LSI (SoC)

2004

VLSI


RF
IEEE 1394, USB, Blue tooth, Wireless LAN

DAB
CS/BS

Ethenet

Digital TV
ITS
HII Station

Home network

ADSL, FTTH
Network
Digital TV
W-CDMA

2004

Home
Server

DVC

VLSI

DVD
5

Chip-to-Chip

10Gbps

Chip-to-Chip
Gbps

(xDSL)
10-100Mbps

10-100Mbps

2004

VLSI

8B/10B
P/S

8B-10B
10

TX
1250MHz

125MHz

Clock
Multiplier

RX

S/P

10

10B-8B

1250MHz
PLL Clock
Recovery &
Data
Retiming

2004

VLSI


I/F

Parallel
Data In
RefClk

D
P/S

Clock
Multiplier
Unit
(CMU)

CP

PD

S/P

Serial
Out

Input
Buffer

Serial
In

Tone Sig. Gen.

Parallel Data Out

2004

Kd

MUX

LPF

+
+
+

Driver

Clock Recovery Unit (CRU)

VCO

Kp

Tone_Out
VLSI

3
Gb Ethernet

ADC,

DAC
DAC
DAC

Pulse Shaping

Line
I/F

DAC,

TX1
TX2
TX3
TX4

ADC
250Mbaud ADC
(PAM-5)

FFE

Clock
Recovery

Slicer
DFE

Side-stream
Scrambler
&
Trellis,Viterbi
Symbol
Encoder
Side-stream
Descrambler
&
Trellis,
Viterbi
decoder

Echo Canceller
3-NEXTCanceller

2004

VLSI


ADSL, VDSL

OFDM, QAM
ADC, DAC

RX-in

TXout

2004

Antialiazing
Filter

Reconstr
action
Filter

ADC

DAC

Decimation
Filter

DDFS

DDFS

VLSI

Adaptive
DFE

Interpolation
Filter

Error
Correction
FEC

Error
Correction
FEC

10

I/F
Gbps

Display
(Parallel)

690Mbps

PCI

1.06Gbps

(Parallel)
SCSI
(Parallel)
1394
(Serial)
Year
2004

SVGA
(800x600)

1.36Gbps
XGA
(1024x768)

2.11Gbps

2.26Gbps

3.3Gbps

SXGA
(1280x1024)

UXGA
(1600x1200)

4.22Gbps

8.45Gbps?

32bit@33MHz 32bit@66MHz 64bit@66MHz 64bit@132MHz?

32bit@132MHz

320Mbps

640Mbps

Ultra-SCSI

Ultra-2

200Mbps

400Mbps

1394.a
1998

1999

1.28Gbps

2.56Gbps? 5.12Gbps?
Ultra-4 ?

Ultra-5 ?

1.60Gbps
800Mbps
1394.b

3.20Gbps

Ultra-3

2000

VLSI

2001

2002
11

Data rate (Mbaud), Processing : WS (MIPS)

5000
2000
1000

WS
2x/1.5year

500

1000BT

Moores Law

200
100

1394
Super Moores law

100BT

2x/0.6year

50
20

USB

10
Ethernet

10BT

5.0
88 ~89

2004

90 ~ 91

92 ~ 93

94 ~ 95

96 ~ 97

VLSI

98 ~ 99

00 ~ 01
12

(DTV, ADSL, Ethernet, USB

HDD, DVD, DVC

Variable
Gain Amp.

Analog
Filter

A to D
Converter

Voltage
Controlled
Oscillator

Data In
(Erroneous)

Digital
FIR Filter

Viterbi
Error
Correction

Data
Out

Clock
Recovery

Pickup signal

Analog circuit
Digital circuit

Data Out
(No error)

2004

VLSI

13

Mixed signal SoC for DVD RAM system

This enables high readability for weak signal from DVD RAM pickup.
World fastest and highly integrated mixed signal CMOS SoC

0.18um- eDRAM

24M Tr
16Mb DRAM
500MHz
Mixed Signal
Goto, et al., ISSCC 2001
2004

VLSI

14

Recent developed mixed signal CMOS LSIs

5G RF LAN

12b 50MHz ADC 2ch

12b 50MHz DAC 2ch

Digital network
1394b (1GHz)

AFE (Analog Front End)

AFE for Digital Camera

12b 20MHz ADC+AGC

AFE for ADLS

12b 20MHz
ADC+DAC

2GHz RF CMOS

2004

VLSI

15

CMOS technology for over GHz networking

Digital consumer needs over GHz wire line networking.
CMOS has attained 5Gbps data transfer.

World first 1394b transceiver

For 1Gbps networking
0.25um 3AL_CMOS

Test chip for 5Gbps wire line

0.18um 4AL_CMOS

5Gbps Eye pattern

2004

VLSI

16

Application area in mixed signal CMOS tech.

Almost all the products need mixed signal CMOS LSI tech.

Cellular phone: PDC, W-CDMA

Wireless
RR-Net: Bluetooth, IEEE802.11
Broad cast: STB, DTV, DAB
Network
Communication
Optical: FTTH, OC-xx
Wired

Metal: ADSL, VDSL, Power line modem

Serial: IEEE1394, USB, Ethernet
Parallel: DVI, LVDS

Recording
DVD, VDC, HDD
Output
LCD, PDP, EL, Audio drive
Input
Power supply
2004

Camera, Others
Switching supply, Every LSIs (On-chip)
VLSI

17

CMOS

2004

VLSI

18

Difficulty of analog in LSI technology

Dynamic range has been reduced with technology scaling.

Performance (Log)

New circuit technology or architecture are needed

Integration

Speed

1
2
L

1
1.5
L

L
tox
Leff

W
Xj

0.7x

Scaling Rule

Signal swing
Dynamic range =

L1.5

Scaling
1
DesignRule
2004

Noise + mismatch

(Log)
VLSI

19

CMOS as analog device

CMOS has many issues as analog device,
but also has a variety of circuit techniques
CMOS

Bipolar

Comment

Switch action

++

--

Low Input current

++

--

Only CMOS can realize

switched capacitor circuits

High gm

CMOS is of Bip.

Low Capacitance

This results in Cp issue

fT

Almost same

Voltage mismatch

--

++

CMOS is 10x of Bip.

1/f noise

--

++

CMOS is 10x to 100x of Bip.

Low Sub. effect

Offset cancel

++

--

Analog calibration

++

--

Digital calibration

++

--

Embed in CMOS

++

--

2004

VLSI

CMOS has a variety of

techniques
to address the self issues

20

GHz operation by CMOS

Cutoff frequency of MOS becomes higher than that of Bipolar.
Over several GHz operations have attained in CMOS technology
0.13um
100G

0.18um
0.25um

Frequency (Hz)

50G
20G

fT : CMOS
fT : Bipolar (w/o SiGe)
fT /10 (CMOS )

0.35 um

RF circuits

10G
5G

Cellular
Phone

CDMA

5GHz W-LAN

fT /60 (CMOS )

gm
fT
2Cin
vsat
fTpeak
2Leff

Digital circuits

2G
1G

IEEE 1394
D R/C for HDD

500M
200M
100M

1995

2004

2005

2000

VLSI

Year
21

Transistor issue: VT mismatch

Larger gate area is needed for small VT mismatch.
Scaling and proper channel structure can improve this issue.

VT (:mV)

15

0.4um Nch

Tox
VT
LW

10

Tox scaling

Larger gate area

0.13um Nch Boron w. Halo*

0.4um Pch
Channel engineering
0.13um Nch In w/o Halo*

0.1

0.2

0.3

0.4

0.5

0.6

1
( m 1 )
LW
2004

0.7

0.8

* Morifuji, et al., IEDM 2000.

VLSI

22

kT/C

ADC

SNR (dB)

N=2
95.918

kT/C

100

90

VFS=5V
VFS=3V

14bit

VFS=2V

SNRC 1 2 C
SNRC 2 2 C

nkT
C

VFS=1V

80

12bit

SNRC 3 2 C
SNRC 5 2 C

Vn2

VFS

70

CVFS2

SNR( dB ) 10 log
8nkT

10bit
60

51.938 50

0.1

0.1

0.1

10

10

100

100

100

(pF)
2004

VLSI

23

CMOS

2004

gm/Ids1/3
fT

1/f
1/f

Bi-CMOS

VLSI

24

Characteristics of gm (Basic)
Gm is proportional to Ids and inversely proportional to Veff.
Veff is proportional to square root of Ids and inversely proportional to
square root of (W/L) ratio.

Square law region

C O X W
C O X
2

V
gs

T
2 L
2
dI
W
gm ds C O X Veff
dVgs
L
Ids

2
Veff

I ds
gm
Veff

2
Veff

W
gm 2C O X Ids
L

2004

VLSI

gm
1
,

I ds Veff

2 1 L

Ids
Cox W

25

gds (=/rds)

g I ds :
gds can be reduced by using larger L and small Ids. ds
1
gds
L
Nch
-4

gds Ids0.75
log [gds ]

log [gds ]

L=0.4um

H
J

-6

J
H
1.0um
-7 2.0um
4.0um

-5

L=0.4um

0.6um

gds Ids0.75

gds Ids 1.0

1.0um

-7 2.0um

4.0um

-4

-3

-2

-6

log [Ids]
2004

-6

0.6um

-6

-5

W=10um
BB
BB
B
J
BJ
B BJ J
B JJ
B J
B J J
J

-4

JJJ
JJ
J
H
J
J J HH
J HHHH
J H
H
H

gds Ids 0.5

-5

Pch

W=10um

0.5 1.0

-5

-4

-3

log [Ids]
VLSI

26

Iout

Iout

rout
rout

Vin

M1

rds1

(a) Source grounded ckt.

2004

Iout

Vb
Vin

M2
M1

gm 2rds 2 rds1
TR2
10
(b) Cascode ckt.
VLSI

Vb

rout
+
-

M2

Vin

M1

G gm 2rds 2 rds1

(c) Super-cascode ckt.

27

CMOS
DC

VDD
M3

M4
M1 M2

VIN(-)
Vbias

I1
M5

M6

Cc

VIN(+)

I2

GDC

CL

gm 2
gm 6

gds 4 gds 2 gds 6 gds 7

Sro

I2
CL

Sri

I1
Cc

GBW
SP2

M7

gm1
I1

Cc Veff 1Cc

2I 2
gm 6

C L Veff 6C L

SP2 3GBW

(1/f

Vn2_ in

16kTVeff 1
16kT
f
f
3gm
3I1

CMOS Ids, gm, rds (gds),

2004

VLSI

28

0) gm
gm

Ids
Veff
, Ids gm
2
Veff

Veff0.2V

W/Lgm

Ids

gm

L, W

(Veff)

Ids
Veff

Veff

2n

1 L

Ids
Cox W
Veff0.2V

W
2n
Ids
8n gm2

L
Cox Veff
Cox Ids

gon

Cox W
n

Veff

W
n gon

L Cox Veff

2 Lrds, , , 1/f
2004

VLSI

29

CMOS A/D

2004

VLSI

30

Flash, Pipeline,
1000

Flash

DVD

Conversion Frequency (MHz)

HDD
Digital
I/F

100

Digital
TV
VDSL

Digital
Camera

10

Pipeline
1

ADSL

Motor
servo

GSM
handset

DVD Audio

Sigma Delta

0.1

DVD Player
Cellular
phone

Conventional
Audio

0.01
0

10

12

14

16

18

CD/MD

20

22

24

Resolutionbit)
2004

VLSI

31

ADC Architecture:Flash and pipeline

Flash is used in ultra-high speed conversion with low resolution.
Pipeline is used in high resolution with moderate conversion speed .
Flash
Deliverables;
Folding
Interpolation

+
+
+
+
+
+
+
+

vin

D2

D3

D4

D5

D6

D7

1-bit
DAP

1-bit
DAP

1-bit
DAP

1-bit
DAP

1-bit
DAP

1-bit
DAP

1-bit
DAP

2004

Digital approximater
(DAP)

S/H

vref
4
vref
4

2
Amplifier

Suitable for CMOS

Switched capacitor operation

Comparator

Ultra-high speed (-- 2GHz)

Low resolution (<8bit)
Large power consumption

LSB

D1

Comparator

Encoder

Vref Vin CLK

Pipeline

MSB

High resolution(<14bit)
Moderate speed(<100MHz)
Low power consumption
VLSI

32

ADC Architecture: Sigma delta ADC

Sigma delta ADC and DAC are widely used for high resolution (14b-24b)
and not high speed ( <1MHz) applications. All are realized with CMOS tech.

Sigma delta ADC

Sigma delta DAC

Integrator

AVDD
Comparator

x(n)

z-1

+
1bit DAC

Analog

Digital
Signal
Processing

Digital

High SNR and resolution

1 C 2
1

Digital
Filter

Integrator

vin

DAC out

M: over sampling ratio

SNR( dB ) 70log M 19.6

Small and simple low accuracy analog ckt.

vref
2

2004

vref

1bit DAC

Easy implementation in CMOS

VLSI

33

Progress in A/D converter

ADC is a key for mixed signal technology.
We have reduced the cost and power of ADC drastically;

Power consumption: 1/2,000

Price: 1/200,000

1980

1982

1993

Now

Conventional product World 1st Monolithic World lowest power SoC Core
Board Level (Disc.+Bip)
20W
$ 8,000

Bipolar (3um)
2W
$ 800

Analog Devices Inc.

CMOS (1.2um) CMOS (0.15um)

10mW
30mW
$0.04
$ 2.00
Our developed.

Our developed.

Our developed.

2004

VLSI

34

ADC
2N

2mV !!
0.2mV1%
MOS!!

LSI

Vr7

C7

Vr6
Vr5

C6
C5

Vr3
Vr2
Vr1

C4

(%)

Vr4

C3

2mV : 10bit

C2
C1

2004

VLSI

35

CMOS 10b ADC

10bADC

Kusumoto, et al.,
ISSCC 93

A/D
10b, 20MHz30mW

500mW

10

1
0 .5

0. 1

1000

0 .0 5
0. 0 1

'80

'82

'84

'86

'88

'90

'92

'94

@0.8umCMOS ADC

2004

VLSI

36

Early stage mixed signal CMOS LSI for CE

Success of CMOS ADC and DAC enabled low cost mixed signal CMOS LSI.
This also enabled low cost and low power digital portable AV products.
1993 Model: Portable VCR with digital image stabilizing

6b Video ADC

Digital Video filter

System block diagram

8b low speed ADC;DAC

2004

8b CPU

VLSI

37

Progress in high-speed ADC

High speed ADC has reduced its power and area down to be embedded.
World fastest 6b ADC
ISSCC 1991

6b, 1GHz ADC

2W,
1.5um Bipolar

6b, 800MHz ADC

400mW, 2mm2
0.25umCMOS

Pd/2N[mW]

ISSCC 2000 World fastest CMOS ADC

10

Reported Pd of CMOS ADCs

1 order down
1

ISSCC 2002 World lowest Pd HS ADC

7b, 400MHz ADC
50mW, 0.3mm2
0.18umCMOS
2004

VLSI

This Work
0.1
1

10

Conversion rate [x100Msps]

38

RF CMOS

2004

VLSI

39

LSI

Low-IF,

2005
HSDPA
(14M)

W-CDMA
(384k)
GSMGPRS
EDGE

cdma2000
cdma2000-1X EV-DV
2005
1x(144K)EV-DO(2.4M) (5.2M)

PAN
Cellular

LAN

IEEE802.20(4M)
PHS

2005

2010
4G

PDC

A-PHS
IEEE802.11b
(11M)

ZigBee

Bluetooth

802.11a/g 802.11n
(54M)
(100M)
IEEE802.15UWB

2004

VLSI

40

RF
RF
LSI

RF-TAG chip

NTT)

2004

VLSI

41

Technology edge RF CMOS LSI

Many RF CMOS LSIs have been developed for many standards
Wireless LAN, 802.11 a/b/g
0.25um, 2.5V, 23mm2, 5GHz

Discrete-time Bluetooth
0.13um, 1.5V, 2.4GHz

M. Zargari (Atheros), et al., ISSCC 2004, pp.96

2004

VLSI

K. Muhammad (TI), et al., ISSCC2004, pp.268

42

Multi-standard issue
Reconfigurable RF circuit is strongly needed for solving multi-standard issue.
Multi-standards and multi chips

Future cellular phone needs

11 wireless standard!!

IMT-2000
RF

IMT-2000
BB

Current
GSM
RF

GSM
BB

Bluetooth
RF

Bluetooth
BB

MCU

GPS
RF

GPS
BB

Power

Unification
Future
Reconfigurable
RF

DSP

Yrjo Neuvo, ISSCC 2004, pp.32

Unified wireless system

2004

VLSI

43

2004

VLSI

44

RF MEMS switch
Mechanical low-loss integrated switch enables;
Select or change inductance and capacitance
Select signals and circuits;
As a result, enables reconfigurable RF circuits

J. DeNatale, ISSCC 2004, pp. 310

2004

VLSI

45

SoC

2004

VLSI

46

Full DVD system integration in 0.13um tech.

Advanced mixed signal SoC has been successfully developed.
Okamoto, et al., ISSCC 2003

0.13um, Cu 6Layer, 24MTr

CPU2
CPU
System
Controller

Pixel
Operation
Processor

Front-End

Analog FE
+Digital R/C

VCO
ADC

PRML
Read
Channel

AV
Decode
Processor

IO
Processor

Servo DSP

Gm-C
Filter

Back -End

Analog
Front End

2004

VLSI

47

SoC

A/DD/A

2004

PVT

VLSI

48

CMOS

2004

VLSI

49

CMOS
CMOS
CMOS

DSP

2004

VLSI

50

Noise and EMI reduction

To reduce the noise generated by digital;
Increase embedded decoupling capacities in digital and analog
and also increase substrate resistance, decrease package inductances.
Noise radiation

Digital ckt.
Noise
current is
converted
to noise
voltage

C
Analog
ckt.

RC Low-pass filter

R
Package
inductance

2004

R and C forms
RC low pass filter

Embedded
decoupling
capacitance

Substrate
resistance
VLSI

Noise invasion
51

Noise simulation
Noise should be simulated on the post-layout simulation stage
Without added dec-cap.

With added dec-cap.

Peak current can be reduced to 65%

2004

VLSI

52

SoC

2004

VLSI

53

EDA
SoC
EDA

2003.7.21 pp.71
2004

VLSI

54

EDA

SoC

IP

LPE

LSI
2004

VLSI

55

ADSL Analog Front End

ADSL

Analog Front End

G.C.

12

Rx Data

ADC
15dB

External

Signal
Process
or

Tx Data

Digital Interface

Line

Digital

Tuning

Interface

LNA

12
DAC

0 31dB

VCO
DAC

2004

XTAL

VLSI

Solid lines
Dotted lines

56

LSI design using behavioral language

Example: Analog Front End chip for ADSL system.

LNA

Output driver

Buffer

Buffer

Filter

Filter

D/A
A/D

VCXO cont.

Control logic
2004

VLSI

57

Hierarchical and behavioral system design

System should be described in behavioral language, hierarchically.

Analog: Verilog-A

Logic: Verilog-D

Analog behavioral model

2004

VLSI

58

Virtual System test using Verilog AMS and Matlab

We can test the designed mixed signal system virtually,
by using Verilog AMS and Matlab.
Matlab

Matlab

DMT modulation

DMT demodulation

Target LSI
Conste
llation
ENC

IFFT

FIR

FIR

FFT

Verilog-AMS

Conste
llation
DEC

Matlab is used as a soft DSP

> 66dB

MTPR TEST (DMT Carrier hole)

2004

VLSI

QAM constellation
59

2004

VLSI

60

Vdd and CMOS scaling limits in analog

Lowest analog operating voltage must be 1.2V -1.8V.
65nm1.2V

Technology node (0.1um)

Supply voltage (V)

Analog
(Upper)

Analog
(Lower)
2

Digital
(Lower)

0
1

2004

ITRS 99

Digital
UpperTechnology

node

2
00

7
05

VLSI

10

11

12
10

13

14

15
61

vsat E
L

f t max
Eb

vsat
1

2L
Vds
L

Vds

Vsat:
Eb:

vsat Eb
ft max Vds
const
2
2004

VLSI

62

Cost up issue by analog & I/O

Cost of mixed A/D LSI will increase when using deep sub-micron
device, due to the increase of cost of non-scalable analog and I/O parts.
Large analog on SoC must be unacceptable in near future.
Wafer cost increases 1.3x
for one generation

I/O
Analog
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0

Digital

0.35um

0.25um

0.18um

0.13um

0.35um : 1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0

Chip area
2004

0.35um

0.25um

0.18um

0.13um

Chip cost
VLSI

63

Example: Analog+ digital calibration tech.

Area and power are reduced drastically, by scaled CMOS and digital tech.
Y. Cong and R. L. Geiger, Iowa state university,
ISSCC 2003
14b 100MS/s DAC
1.5V, 17mW, 0.1mm2, 0.13um
0.5 LSB INL,
SFDR=82dB at 0.9MHz, 62dB at 42.5MHz
+/- 9 LSB

+/- 0.4 LSB

Area: 1/50
Pd: 1/20
Calibration
2004

VLSI

64

Future step: Mixed signal egg.

Analog helps digital (digital network and storage).
Next step is digital must help analog.
Mixed signal egg ( Analog yolk and white with digital shell)

Digital shell

Sustain the analog egg.

Calibration and adjustment.

Analog yolk and white

Ultra-low power signal processing
Ultra-high speed signal processing

But, very delicate and fancy

2004

VLSI

65


RFLSI

LP-AFE)

RFCMOS

DAC (OEL)

ADC
10b, 2GHz ADC (UWB)
6b, 1GHz, 40mW (UWB)
14b, 400MHz ADC (Soft Radio)
2004

VLSI

(LNA, VCO, Mixer, Filter,

ADC, DAC, PA,
LSI

ZigBee
UWB

66



SoC
SoCCMOS

CMOS

SoCTAT

EDA

2004

VLSI

67