module mux(input [23:0]a,b,input clk,input [7:0]i1,j1,output reg [23:0]pro,outpu

t reg [7:0]e
);
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg

[47:0]sum;
[5:0]count=6'b0;
[46:0]acc=47'b0;
[24:0]ipr=25'b0;
[23:0]l=24'b0;
[23:0]m=24'b0;
[1:0]p=2'b0;
s;
[23:0]ipra;
[7:0]i,j;

always @ (posedge clk)

count<=count+1;
always @ (posedge clk)
begin
if(count==6'b0)
begin
ipr<={b,1'b0};
ipra<=a;
s<=1;
i<=i1;
j<=j1;
end
else
begin
i<=i;
j<=j;
ipr<=ipr>>1;
if(s==1)
if(count>6'b011001)
if(sum[47]^sum[46]==1)
s<=0;
else
s<=s;
else
s<=s;
else
s<=s;
ipra<=ipra;
end
acc<={m,acc[23:1]};
end

always @ (*)
begin
p<=ipr[1:0];
case(p[1:0])
2'b00:l<=24'b0;

2'b01:l<=ipra;
2'b10:l<=-ipra;
2'b11:l<=24'b0;
endcase
m<=l+{acc[46]&~count[5],acc[46:25],~count[5]&acc[24]};
end
always @ (posedge clk)
if(count==6'b011001)
sum<={acc[46],acc[46:0]};
else
sum<=sum<<1;
always @ (posedge clk)
begin
if(count>6'b011001)
if(s&(sum[47]^sum[46])==1)
begin
pro<=sum[47:24];
e<=-(count-i-j-6'b011010-6'b011000);
end
else
begin
pro<=pro;
e<=e;
end
else
begin
pro<=pro;
e<=e;
end
end
endmodule