Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

1. C s v c/ghi b nh EEPROM B nh d liu EEROM c th c, ghi trong khi hot ng bnh thng. B nh ny nh a ch gin tip qua cc thanh ghi chc nng c bit (SFR). C 4 thanh ghi thng dng c v ghi b nh ny: EECON1, EECON2, EEDATA, EEADR EEDATA lu tr d liu 8bit cho c, ghi. V EEADR gi a ch ca v tr EEPROM ang truy cp, n l thanh ghi 8bit nn c th truy cp ti 256 v tr ca EEPROM. EECON1 cha cc bit iu khin, trong khi EECON2 l thanh ghi s dng khi to c/ghi.

rng b nh EEPROM

Di a ch lun bt u bng 00h. B nh ny thc hin xa d liu trc khi ghi , thi gian ghi c iu khin bng timer on-chip, v thay i theo in p v nhit cng nh i vi tng chip khc nhau th c tc khc nhau. Cc thanh ghi
Thanh ghi EECON1

-Bit7

--

--

EEIF

WRERR WREN

WR

RD
Bit0

Bit 5:7: ko s dng. c l 0 Bit 4 EEIF: bit c ngt qu trnh ghi 1= Qu trnh ghi hon thnh ( phi c clear bng phn mm) 0= qu trnh ghi khng hon thnh hoc ko c bt u ghi Bit3 WRERR: bit c li
1

Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

1= qu trnh ghi kt thc sm (do reset MCLR hoc WDT) 0= qu trnh ghi hon thnh Bit2 WREN: bit cho php ghi 1= cho php ghi 0= chn ghi ti EEPROM Bit1 WR: bit iu khin ghi 1= khi to qu trnh ghi. Bit ny c clear bng phn cng khi qu trnh ghi hon thnh 0= qu trnh ghi ti EEPROM hon thnh Bit0 RD: bit iu khin c 1= khi to c EEPROM. RD c clear bng phn cng. bit ny ch c th set bng phn mm 0=khng khi to 1 qu trnh c EEPROM khi bt ngun bit WREN c clear. Khi WRERR c set khi m trong qu trnh ghi xy ra reset MCLR hoc reset WDT (watch dog timer). Khi xy ra ngt t ngt th a ch v d liu trong thanh ghi EEADR v EEDATA khng b thay i. V th ta c th tin hnh qu trnh ghi li. EECON2 khng phi l thanh ghi vt l. N c s dng khi to qu trnh ghi bng initial sequence ( ti trnh by phn ny di).

c b nh EEPROM, u tin phi ghi a ch vo thanh ghi EEADR v sau set bit iu khin RD (EECON<0>). D liu sn c s c chuyn vo thanh ghi EEDATA. V ta c th c lnh tip theo. EEDATA gi gi tr cho ti khi xut hin ln c khc hoc cho ti khi n c ghi bi user. Qu trnh trn c hin thc bng chng trnh sau

Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

Chng trnh:
c b nh
BCF MOVL W MOVW F BSF BSF BCF MOVF STATUS,RP0 CONFIG_ADDR EEADR STATUS, RP0 EECON1, RD STATUS, RP0 EEDATA, W ; ; ; ; ; ; ; Bank0 a ch c ghi a ch c vo thanh ghi EEADR Bank1 c EE Bank0 W = EEDATA

Ghi b nh d liu EEPROM ghi d liu ti b nh, u tin user phi ghi a ch ti thanh ghi EEADR v ghi d liu ti thanh ghi EEDATA. Tip theo phi km theo 1 chui khi to (initial sequence) qu trnh ghi cho mi byte (ngha l khi ghi mi byte vo b nh ta phi thc hin th tc y ht nh vy). Chng trnh:
Ghi b nh
BSF STATUS, RP0 ; Bank1

Initial sequence

BCF INTCON, GIE ; Disable INTs. BSF EECON1, WREN ; Enable Write MOVLW 55h ; MOVWF EECON2 ; 55h phi c ghi ti EECON2 MOVLW AAh ; bt u sequence MOVWF EECON2 ; ghi AAh ti thanh ghi EECON2 BSF EECON1,WR ; Set WR bit bt u ghi BSF INTCON, GIE ; Enable INTs.

Qu trnh ghi s ko khi to nu initial sequence ( ghi 55h ti EECON2, ghi AAh ti EECON2) thc hin ko ng. Trong khi thc hin initial sequence nn che tt c cc ngt li. Thm na bit WREN trong EECON1 phi c set cho php ghi. N ngn chn hng ghi d liu ti EEPROM v qu trnh thc thi m li ( i.e chng trnh

Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

li). user nn gi bit WREN clear ti mi thi im, ngoi tr khi ang update EEPROM. Bit WREN s ko clear bi phn cng. Sau khi initial sequence c thc hin, clear bit WREN s ko nh hng qu trnh ghi byte d liu . Khi hon thnh qu trnh ghi, bit WR c clear bi phn cng v bit EEIF c set. User c th cho php ngt ny hoc hi vng bit ny. EEIF phi c clear bng phn mm 2. c/ ghi b nh EEPROM trong C18 trn ta thy quy trnh c ghi d liu b nh EEPROM kh tun t v logic, tuy nhin ta phi hiu phn cng v cng vic vit tng cu lnh assembly qu l nhm chn. V vy chng ta phi ngh ti s dng cng c tin dng hn. C18 h tr cc hm cho php ta c, ghi d liu vo EEPROM kh n gin s dng. Cc hm bao gm: Hm unsigned char Read_b_eep( unsigned int badd ): s dng c d liu a ch badd v tr v gi tr c c a ch di dng s char khng du unsigned char Hm void Write_b_eep( unsigned int badd, unsigned char bdata ): ghi d liu c gi tr bdata ti a ch c gi tr badd v ko tr v gi tr. Hm void Busy_eep ( void ): l hm check bit WR v ch trong thanh ghi EECON1. Hm ny s ch cho ti khi no bit WR=0 tc l qu trnh ghi d liu vo b nh hon thnh th n s thot v thc hin cu lnh tip theo. C ngha l hm ny ch s dng cho ghi ghi d liu Vy lp trnh ghi/c d liu EEPROM t gi ta ko cn bit phn cng n lm ci g. Ch cn vit lnh c v ghi theo c phap nu trn l Ok s dng cc hm ny trong chng trnh ta ch cn khai bo: #include "EEP.h"

Nguyn Vn Hng

hung.rocket42@gmail.com

HVKTQS

V d: Ghi d liu

#include "EEP.h" . unsigned int address=0x88; unsigned int data=0xff; Write_b_eep (address, data); Busy_eep ();
// ghi d liu data ti a ch address // ch cho ti khi qu trnh ghi hon thnh

// qu trnh ghi hon thnh s thc hin cu lnh tip theo ca chng trnh

c d liu #include "EEP.h" . unsigned int address=0x88; unsigned int data; data=Read_b_eep( address )
// c d liu a ch address vo bin data

// thc hin cu lnh tip theo ca chng trnh

Tip: Trong qu trnh thc hin chng trnh i khi cn nhiu b nh nh x l AD hay i khi ch l lu tr d liu tm thi, c khi phi dng ti c b nh ngoi (external memory). Tuy nhin qu trnh truy cp b nh ngoi tc chm hn nhiu so vi b nh m c tch hp sn trong chip. V vy ta nm bt c qu trnh ghi/ c d liu trn b nh c sn ny l rt tin dng, chi ph thp (v ko phi mua thm b nh ngoi) v tc x l nhanh
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