library ieee; use ieee.std_logic_1164.

ALL; Entity comparator is port (a: in std_logic; b: in std_logic; aequab : out std_logic); end comparator; architecture RTL of comparator is begin process begin if a = b then aequab <= '1'; else aequab <= '0'; end if; end process; end RTL; timing diagram (delay keliatan)

functional diagram (delay g keliatan)

library ieee; use ieee.std_logic_1164.ALL;

Entity t is port (a: in std_logic; b: in std_logic; aequab : out std_logic; akurangb : out std_logic; alebihb : out std_logic); end t; architecture RTL of t is begin process begin if a = b then aequab <= '1'; akurangb <= '0'; alebihb <= '0'; else

if a < b then akurangb <= '1'; aequab <= '0'; alebihb <= '0'; else if a > b then alebihb <= '1'; akurangb <= '0'; aequab <= '0';

end if; end if; end if; end process; end RTL;