library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity g2 is Port ( a b c d e end g2; : : : : : in in in in out STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC);

architecture Behavioral of g2 is component and1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c :out std_logic); end component and1; component or1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c :out std_logic); end component or1; signal c1,c2 :std_logic ; begin a1:and1 port map(a,b,c1); a2:and1 port map(c,d,c2); o: or1 port map(c1,c2,e); end Behavioral; --entity or1 is --Port ( a : in STD_LOGIC; --b : in STD_LOGIC; --c : out STD_LOGIC); --end or1; architecture Behavioral of or1 is begin c<=a or b; end Behavioral; --entity and1 is --Port ( a : in STD_LOGIC; --b : in STD_LOGIC; --c :out std_logic); --end and1; architecture Behavioral of and1 is

begin c<=a and b; end Behavioral;