HC VIN CNG NGH BU CHNH VIN THNG

Tm hiu v DRAM
Ngi hng dn: TS. Nguyn Ngc Minh Nhm thc hin: V Xun Ti L Vn Dinh Nguyn nh Th Nguyn Tng Giang

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Mc lc
I. Tm hiu v DRAM
1. S lc vRAM 2. B nh DRAM

II. Cu to, chc nng cc khi v nguyn l hot ng

2.1. Cu to DRAM 2.2. Chc nng cc khi 2.3. S nguyn l 2.4. Nguyn l hot ng

III. u nhc im

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I. Gii thiu v DRAM

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1. S lc v DRAM
RAM(Random Access Memory) l b nh truy cp ngu nhin. Chng c th truy xut n bt k v tr nh no, vo bt k lc no da vo a ch ca nh . iu ny to nn s khc bit gia RAM vi cc thit b nh tun t (Sequential memory device). RAM thng thng c s dng cho b nh chnh (Main memory). Thng tin trn RAM ch l tm thi, chng s mt i khi mt ngun in cung cp

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2. B nh DRAM
y l b nh truy xut ngu nhin thng dng nht ngy nay. DRAM lu tr d liu da vo tn hiu in th trn mt t in (capacitor). in th trn t lun b r r. Do lu tr gi tn hiu th DRAM phi lin tc c lm ti. iu ny to nn phn ng cho DRAM.

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2.1 S lc v lch s DRAM

DRAM c pht minh u tin bi tin s Robert Dennard ti trung tm Thomas J.Watson IBM nm 1966. u nm 1970, Intel ch to thnh cng DRAM dng 1 cell 3 transistor c tn Intel 1102. n 10/1970 Intel cho ra i Intel 1103 c cell 1 transistor. Nm 1973 b nh DRAM u tin c nhiu a ch hng/ct l Mostek MK4096(4096x1)

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2.2. Phn loi b nh

MEMORY

ROM

RAM

SRAM

DRAM

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SD RAM (Synchronous Dynamic RAM )

c gi l DRAM ng b. SDRAM gm cc phn loi: SDR - Single Data Rate DDR - Double Data Rate

DDR2 - Double Data Rate 2

DDR3 - Double Data Rate 3

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SDR SDRAM (Single Data Rate SDRAM)

Gi t l SDR. C 168 chn. c dung trong c my tnh c, bus speed chy cng vn tc vi clock speed ca memory chip

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DDR SDRAM(Double Data Rate SDRAM)

Gi tt l DDR. C 184 chn. DDR SDRAM l ci tin ca b nh SDR vi tc truyn ti gp i SDR nh vo vic truyn ti hai ln trong mt chu k b nh. c thay th bi DDR2

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DDR2 SDRAM (double Data Rate 2 SDRAM)

Gi tt l DDR2. C 240 chn l ci tin ca DDR vi tc bus speed gp i clock speed

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DDR3 SDRAM (Double data rate 3 SDRAM)

C tc bus 800/1066/1333/1600 Mhz, s bit d liu l 64 bits, in th l 1,5v, tng s pin l 240

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RDRAM (Rambus Dynamic RAM)

Gi tt l Rambus. c thit k k thut hon ton mi so vi SDRAM. Hot ng ng b theo mt h thng lp v truyn d liu theo 1 hng. S dng mt modul gi l RIMM (Rambus inline memory module) kt ni cc DRAM

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II. Cu to chc nng cc khi v nguyn l hot ng

S cu to

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2.1 Cu to
DRAM c cu to bi hng triu t bo nh c khc ln mt bnh silicon theo cc ct (bitlines) v hng (wordlines). im giao ca bitline v wordlines to thnh a ch t bo nh DRAM c cu to nh hn SRAM nh vo cu to n gin ca t bo nh. Cng kch thc nhng DRAM c dung lng ln hn nhiu so vi SRAM Cc thnh phn chnh: b iu khin, b tin np, b khuch i, b m(m a ch, m d liu), b gii m a ch(gii m hng v ct) v ma trn nh
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2.2. Chc nng cc khi

B iu khin - Control block: To tn hiu kch hot hot ng ca DRAM. iu khin qu trnh truy xut d liu bng cch to ra cc tn hiu clock. H tr iu khin qu trnh lm ti d liu B phn tin np: Sau mi ln c d liu th tn hiu in p lu gi trong t bo nh b mt. Do cn c b phn np li in th. Np li tn hiu in p cho t trnh mt mt d liu do t r r in. chu k np li rt nhanh khong 2ms. y ch np li in p cho tt c cc bit c gi tr 1

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2.2. Chc nng cc khi

B phn khuch i - Senseamplifier : C chc nng khuych i tn hiu xc nh gi tr ca nh. Theo l thuyt th mc in p 5v i din gi tr 1, 0v i din gi tr 0. Nhng thc t mc in p lun dao ng trong khong t 0v n 5v. Do cn c b phn khuch i tn hiu. Khi mc in p trong 3v n 5v (trn 50%) th gi tr c c l mc 1. Ngc li nu in p t 0v n 2.5v (di 50%) c c l mc 0

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2.2. Chc nng cc khi

B m: o B m a ch: Cha a ch c truyn vo chip nh. Do a ch c xc nh bng mc in p nn trong qu trnh truyn c th b mt mt. B m a ch s gip khi phc li mc in p ng vi gi tr ban u. Sau khi khi phc, a ch s c truyn n cc b gii m a ch o B m d liu vo ra: Thng cc mch cht (latch) hay cc flip-flop dng lu gi d liu u vo v ra ca chp nh. Khi phc mc in p ph hp vi gi tr, trnh mt mt.
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2.2. Chc nng cc khi

B gii m a ch: Gm b gii m a ch hng v ct. s dng mt b dn knh a ch. Thng thng m ha c 16k hoc 512k, chip nh cn c 14 hoc 19 chn. Nhng vi b dn knh a ch chip nh ch cn 7 chn hoc 10 chn a ch

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M hnh mch dn knh

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Thi gian cn thit cho QT dn knh

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Ma trn nh
Gm hng triu t bo nh c sp xp theo mt ma trn hng v ct. Giao gia hng v ct l a ch ca t bo nh

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2.3.S nguyn l

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2.4. Nguyn l hot ng : D liu trong DRAM c c ghi da vo mc in p c lu trong t in ca t bo nh. c ghi d liu, ta cn c tn hiu iu khin v hai tn hiu RAS v CAS m ha a ch bng b m ha d liu.

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2.4.1. Chu k c d liu

D liu trong DRAM c c ghi da vo mc in p c lu trong t in ca t bo nh

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2.4.1. Chu k c d liu

Gi s RW ang mc cao trong sut hot ng c. Sau y l phn m t tng bc hot ng xy ra ti nhng thi im trong s tn hiu. t0: MUX b a xung mc thp nht p cc bit a ch hng vo u a ch ca DRAM t1: RAS b a xung mc thp nht np a ch hng vo DRAM t2: MUX ln mc cao t a ch ct ti cc u vo a ch ca DRAM t3: CAS xung thp np a ch ct vo DRAM t4: DRAM p ng li bng cch t d liu hp l t vo nh c chn ln ng d liu ra t5: MUX, RAS, CAS v ng d liu ra tr v trng thi ban u
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2.4.2. Chu k ghi d liu

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2.4.2. Chu k ghi d liu

t1: RAS = NGT np a ch hng vo DRAM t2: MUX ln mc cao dt a ch ct (A7-A13) ti cc u vo a ch ca DRAM t3: CAS = NGT np a ch ct vo DRAM t4: D liu cn ghi c t ln ng d liu vo t5: RW b kch xung thp ghi d liu vo nh c chn t6: D liu vo b loi b khi d liu vo t7: MUX, CAS, CAS v ng d liu trng thi ban u

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2.4.3. Qu Trnh Refresh

Vic refresh DRAM phi c xy ra mi 2ms duy tr d liu. Mi 1 hng phi c kch bi chn RAS. CAS c th mc cao trong qu trnh t lm ti gim cng sut tiu th. D c hay ghi vo 1 t bo no ca mt hng u phi lm ti ton b hng . Phng php lm ti ph bin nht l lm ti ch vi thc hin bng vic la chn mt a ch hng vi RAS trong khi Rv v CAS vn mc

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III. u im v nhc im
u im: s dng t transitor nn chi ph thp, din tch nh. C th thit k b nh vi dung lng ln Nhc im: tn thi gian lm ti d liu. hn ch tc truy xut

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