VHDL: VHSIC Hardware Description Language.

VHSIC: Very High Speed Integrated Circuit.

:
-

.
(_)
( ; ).
.
: .
.
) (buffer, in, out, inout
.port
Begin
.
port .

:
A
B
E
D

VHDL
.
.Bit
.
:
Entity [ entity_name ] is
;Port (interface_Signal_declaration
;] End [entity_name

Architecture [ Archi_name ] of ( entity_name ) is

Begin
Architecture Body.
End [ Archi_name ];
:
Entity two_gates is
Port (A, B, D : in bit; E: out bit );
End two_gates;
Architecture gates of Two_gates is
Signal C: bit;
Begin
C <= A and B;
E <= C or B;
End gates;
.);( ( entity, archi, begin )
.<=
.
:
Signal list_of_signal_name : type_name [(constraint)][:= initial_value];

:
-

( 4 down to 0 ) ( 0 up to to ) constraint .(rang o to 15 )

.signal A, B, C :Bit_vector (3 down to o):= 111 :
.111 0 3 A, B, C
signal E, F :integer range o to 15; :
.11
0

:full adder

X
0
0
0
0
1
1
1
1

Y
0
0
1
1
0
0
1
1

Cin
0
1
0
1
0
1
0
1

Sum
0
1
1
0
1
0
0
1

Cout
0
0
0
1
0
1
1
1

( X Y ) Cin
. ) ( 3
.Sum=

Cout = X.Y + X.Cin + Y.Cin

Entity Full_adder is
Port ( X, Y, Cin : in bit; Sum, Cout :out bit);
End full_adder;
Architecture Equation of Full_addel is
Begin
Sum <= ( X XOR Y ) XOR Cin;
Cout <= ( X and Y ) or ( X and Cin ) or ( Y and Cin);
End equation;
:
S0

S1

S2

S3

Cin

F.A

A0

F.A

B0

A1

F.A

B1

A2

Cout

F.A

B2

A3

B3

*************************************************