Gii thiu v C AT90S8535

GII THIU V C AT90S8535

2.1 KIN TRC TNG QUT 2.1.1 S CHN CA AT90S8535

Hnh 2.1: S chn ca vi iu khin AT90S8535. c im S dng kin trc RISC AVR. AVR kin trc RISC c ch tiu cht lng cao v tiu th t nng lng. 118 lnh mnh, hu ht c thc hin trong 1 chu k xung nhp. 8 kbytes RAM flash lp trnh c ngay trn h thng. Giao din ni tip SPI lp trnh ngay trn h thng. Chu c 100.000 ln ghi/ xo. B nh EEPROM 512 byte. B bin i ADC 8 knh, 10 bit 32x8 thanh ghi lm vic a nng. 32 ng vo ra lp trnh c. UART ni tip lp trnh c. in th hot ng: 4V- 6V. Vng tc lm vic: 0 8MHz. C mch Power- On reset. Tc x l lnh ln n 8MIPS 8MHz. Trang 1

Gii thiu v C AT90S8535 B m thi gian thc (RTC) vi b dao ng v ch m tch bit. Hai b m/ b nh thi 8 bit vi ch so snh v chia tn s tch bit. Mt b m/ b nh thi 16 bit vi ch so snh v chia tn s tch bit v ch bt mu (Capture). Ba knh PWM (bin iu rng xung). Cc ngun ngt ngoi v trong. B nh thi watchdog lp trnh c vi b dao ng trn chip. b so snh tng t c sn trn chip. C ba ch ng: ngh (Idle), tit kim nng lng (Power save) v Power down. Kho bo mt phn mm lp trnh c. M t AT90S8535 l b vi iu khin CMOS 8 bit tiu th t nng lng da trn kin trc RISC AVR. Bng vic thc hin cc lnh mnh trong 1 chu k xung nhp. AT90S8535 t c tc x l d liu ln n 1 triu lnh/giy tn s 1MHz. Vi iu khin ny cn cho php ngi thit k h thng ti u ho mc tiu th nng lng m vn m bo tc x l. im ni bt ca AVR kt hp tp lnh phong ph v s lng vi 32 thanh ghi lm vic a nng. Ton b 32 thanh ghi u c ni trc tip vi khi ALU, cho php truy cp hai thanh ghi c lp bng 1 lnh n l trong 1 chu k xung nhp. Kin trc t c c tc x l nhanh gp 10 ln vi iu khin c kin trc CISC thng thng. Nhng tnh nng ni bt ca cc vi iu khin AT90S8535 c th k ra l: b nh flash lp trnh c trong h thng 8k byte, b nh EEPROM 512 byte, b nh SRAM 512 byte, 32 ng vo ra a nng, 32 thanh ghi lm vic a nng, RTC, 3 b nh thi/ m linh hot vi ch so snh, cc ngt bn trong v ngoi, mt b UART ni tip lp trnh c, b ADC 8 knh 10 bit, b nh thi watchdog lp trnh c vi b dao ng bn trong, mt cng ni tip SPI v ba ch tit kim nng lng la chn c bng phn mm. - Ch Idle lm ngng hot ng ca CPU trong khi b nh SRAM, cc b nh thi/ b m, cng SPI v h thng ngt vn tip tc hot ng. - Ch Power down lu tr ni dung thanh ghi nhng gii phng b dao ng, cm tt c cc chc nng khc trn chip cho n khi xut hin mt ngt k tip hoc tn hiu reset cng. - Ch Power save b dao ng nh thi tip tc chy cho php ngi dng tip tc trong mt khong thi gian no y (t trc). Trong khi nhng phn cn li ch ng. - Vi iu khin c ch to vi cng ngh b nh khng t mt d liu, bo mt cao.

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Gii thiu v C AT90S8535 - Bng cch kt hp mt CPU 8 bit c kin trc RISC vi b nh flash lp trnh c trong h thng trn mt chip n l. Cc vi iu khin AT90S8535 c xp vo hng cc vi iu khin mnh nht vi tnh linh hot cao trong s dng. c bit l i vi nhiu ng dng iu khin nhng. 2.1.2 S KHI AT90S8535

Hnh 2.2: S khi vi iu khin AT90S8535.

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Gii thiu v C AT90S8535 2.2 M T CC CHN - VCC: in p ngun nui. - GND: Ni mass. - CNG A (PA7PA0): Cng A l cng vo/ ra hai hng 8 bit, cc chn ca cng c cc in tr ni ln ngun dng. Cc chn ra ca cng A c th cho php dng in 20mA i qua v trc tip iu khin LED hin th. Khi cc chn PA0 n PA7 l cc li vo v c t xung mc thp t bn ngoi, chng s l ngun dng nu cc in tr ni ln ngun dng c kch hot. Cc chn ca cng A vo trng thi c in tr cao khi tn hiu reset mc tch cc hoc ngay c khi khng c tn hiu gi nhp. Cng A cung cp cc ng a ch/ d liu vo/ ra hot ng theo kiu a hp knh khi dng b nh SRAM bn ngoi. Cng cn c thm chc nng l ng vo tng t v a n b chuyn i AD. - Cc cng B, C, D tng t nh cng A. - RESET: Li vo t li. B vi iu khin s c t li khi chn ny mc thp trong hn 50ns, cc xung ngn hn khng to ra tn hiu t li. - XTAL1: Li vo b khuch i o v li vo mch to xung nhp bn trong. - XTAL2: Li ra b khuch i o. - ICP: L chn vo cho chc nng bt tn hiu vo b timer/ counter1. - OC1B: L chn ra PWM, ng ra so snh ca timer/ counter1. - ALE: L chn tn hiu cho php cht a ch c dng khi truy nhp b nh ngoi. Xung ALE c dng cht 8 bit a ch thp vo mt b cht a ch trong chu k truy cp b nh th nht. Sau cc chn AD0-7 c dng lm cc ng d liu trong chu k truy nhp b nh th hai. - B to dao ng thch anh XTAL1 v XTAL2 ln lt l li vo v li ra ca mt b khuch i o. B khuch i ny c b tr lm b to dao ng trn chip. Mt b tinh th thch anh hoc mt b cng hng gm c th c s dng. iu khin b vi iu khin t mt ngun xung nhp bn ngoi, chn XTAL2 trng, cn chn XTAL1 c ni vi b dao ng bn ngoi.

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Gii thiu v C AT90S8535 2.3 KIN TRC CA B X L AVR AT90S8535 2.3.1 S KIN TRC B X L

Hnh 2.3: Kin trc RISC AVR AT90S8535. B x l AVR c kin trc Harvard, ngha l c b nh d liu v b nh chng trnh tch bit nhau. Hnh 2.3 minh ha mt bn phc tho kin trc bn trong ca b iu khin. Bus d liu dng cho b nh d liu l mt bus 8 bit, cho php ni hu ht cc b phn ngoi vi vi tp thanh ghi. Bus d liu dng cho b nh chng trnh c rng 16 bit v ch ni vi thanh ghi lnh. B nh chng trnh l loi b nh flash. B x l AT90S8535c 4K byte, b nh chng trnh c truy nhp theo tng chu k ng h, s c mt lnh np vo thanh ghi lnh. Thanh ghi lnh ni vi tp thanh ghi bng cch la chn xem thanh ghi no s c ALU s dng thc thi lnh. Li ra ca thanh ghi lnh c gii m bng b gii m lnh quyt nh chn tn hiu iu khin no s c kch hot hon thnh lnh hin ti. B nh chng trnh, bn cnh cc lnh lu tr, cng cha cc vect ngt bt u a ch $0000. Chng trnh hin ti s bt u v tr b nh pha bn kia vng dng cho cc vect.

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Gii thiu v C AT90S8535 B nh d liu c tt c 5 thnh phn khc nhau: 1. Mt tp thanh ghi vi 32 thanh ghi c rng 8 bit. 2. 64 thanh ghi vo/ ra mi thanh ghi c rng 8 bit, cc thanh ghi vo/ ra ny thc cht l mt phn ca b nh SRAM trn chip v c th truy nhp nh b nh SRAM vi cc a ch gia $20 v $5F hoc nh cc thanh ghi vo/ ra vi cc a ch gia $20 v $5F. Hu ht cc thanh ghi ny thng c trao i nh cc thanh ghi vo/ ra ch khng phi nh b nh SRAM. 3. B nh SRAM bn trong: AT90S8535 c dung lng b nh SRAM 512 byte, b nh SRAM c s dng cho ngn xp cng nh lu tr cc bin. Trong thi gian c ngt v gi on chng trnh, gi tr hin ti ca b m chng trnh c lu tr trong ngn xp. V tr ca ngn xp c ch th bi con tr ngn xp, con tr ngn xp c dung lng 2 byte. Con tr ngn xp cn phi c khi to sau khi reset v trc khi ngn xp c th c s dng. 4. B nh SRAM bn ngoi: Cc b x l ny c cc cng truy nhp b nh v d liu bn ngoi c th s dng bt k b nh SRAM ngoi no m ngi dng c th ty quyt nh khi thit k.

Hnh 2.4: T chc b nh ca vi iu khin AT90S8535. 5. EEPROM: B nh EEPROM c sn trn vi iu khin AT90S8535 v c truy nhp theo mt bn b nh tch bit. a ch bt u ca b nh EEPROM lun l $0000. B nh EEPROM c th c c v ghi bi bt k chng trnh no. Trang 6

Gii thiu v C AT90S8535 Vic c b nh EEPROM din ra nhanh hn vic ghi vo b nh EEPROM c th ghi vo c khong 100.000 ln. Hu ht cc lnh dng cho b iu khin AVR u c chiu di mt t (2 byte) v v th chim 1 nh chng trnh. Nhiu lnh thc thi trong mt chu k ng h n l, trong khi mt s khc c th chim 2 hoc nhiu chu k ng h. Vic thc thi trong mt chu k n l t c l do vic s dng mt kiu cu trc ng ng hai tng. ng ng lm vic theo cch tip nhn ng thi mt lnh mi t b nh chng trnh trong khi lnh trc ang c thc thi trong phn khc ca b x l. 2.3.2 TP THANH GHI Tt c cc b iu khin AVR u c 32 thanh ghi a nng. Mt s trong cc thanh ghi ny cn c cc chc nng ring, b sung. Cc thanh ghi c t tn t R0 n R31.

Hnh 2.5: Tp thanh ghi ca vi iu khin AT90S8535. Tp thanh ghi c tch thnh 2 phn: mi phn c 16 thanh ghi, nh s t R0 R15 v R16 R31. Tt c cc lnh thao tc trn cc thanh ghi u c th truy nhp trc tip v truy nhp trong chu trnh n n tt c cc thanh ghi. Cc thanh ghi R0 v R26 n R31 c cc chc nng b sung. Thanh ghi R0 c s dng trong cc lnh np b nh chng trnh LPM, trong khi cc thanh ghi R26 n R31 c s dng lm cc thanh ghi con tr, cc thanh ghi con tr ny c s dng trong nhiu lnh gin tip dng cho thanh ghi.

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Gii thiu v C AT90S8535 Khng gian I/O ca AT90S8535 $3F($5F) SREG Thanh ghi trng thi. $3E($5E) SPH Con tr ngn xp cao. $3D($5D) SPL Con tr ngn xp thp. $3B($5B) GIMSK Thanh ghi che ngt chung. $3A($5A) GIFR Thanh ghi c ngt chung. $39($59) TIMSK Thanh ghi che ngt b nh thi. $38($58) TIFR Thanh ghi c ngt b nh thi. $35($55) MCUCR Thanh ghi iu khin chung MCU $33($53) TCCR0 Thanh ghi iu khin b nh thi 0. $32($52) TCNT0 B nh thi 0 (8 bit). $2F($4F) TCCR1A Thanh ghi iu khin b nh thi 1 A. $2E($4E) TCCR1B Thanh ghi iu khin b nh thi 1 B. $2D($4D) TCNT1H Byte cao b nh thi 1. $2C($4C) TCNT1L Byte thp b nh thi 1. $2B($4B) OCR1AH Thanh ghi ng ra so snh A b nh thi 1, byte cao. $2A($4A) OCR1AL Thanh ghi ng ra so snh A b nh thi 1, byte thp. $29($49) OCR1BH Thanh ghi ng ra so snh B b nh thi 1, byte cao. $28($48) OCR1BL Thanh ghi ng ra so snh B b nh thi 1, byte thp. $25($45) ICR1H Thanh ghi ng vo Capture T/C 1byte cao $24($44) ICR1L Thanh ghi ng vo Capture T/C 1 byte thp $21($41) WDTCR Thanh ghi iu khin b nh thi watchdog $1F($3F) EEARH Thanh ghi a ch EEPROM byte cao $1E($3E) EEARL Thanh ghi a ch EEPROM byte thp $1D($3D) EEDR Thanh ghi d liu EEPROM $1C($3C) EECR Thanh ghi iu khin EEPROM $1B($3B) PORTA Thanh ghi d liu port A $1A($3A) DDRA Thanh ghi hng d liu port A $19($39) PINA Nhng chn ng vo port A $18($38) PORTB Thanh ghi d liu port B $17($37) DDRB Thanh ghi hng d liu port B $16($36) PINB Nhng chn ng vo port B $15($35) PORTC Thanh ghi d liu port C $14($34) DDRC Thanh ghi hng d liu port C $13($33) PINC Nhng chn ng vo port C $12($32) PORTD Thanh ghi d liu port c $11($31) DDRD Thanh ghi hng d liu port D $10($30) PIND Nhng chn ng vo port D $0F($2F) SPDR Thanh ghi d liu vo ra SPI $0E($2E) SPSR Thanh ghi trng thi SPI $0D($2D) SPCR Thanh ghi iu khin SPI $0C($2C) UDR Thanh ghi d liu vo ra UART $0B($2B) USR Thanh ghi trng thi UART $0A($2A) UCR Thanh ghi iu khin UART $09($29) UBRR Thanh ghi tc cao UART $08($28) ACSR Thanh ghi trng thi v iu khin b so snh analog Trang 8

Gii thiu v C AT90S8535 2.3.2.1 SREG: THANH GHI TRNG THI Thanh ghi trng thi (Status) c cha 8 bit c, ng vai tr bo hiu trng thi hin ti ca b x l. Tt c cc bit c xa khi reset v c th c c hoc ghi vo bi chng trnh. Cc a ch I/O ca thanh ghi trng thi l $3F a ch b nh l $5F.

Bit 7 I: Cho php ngt ton cc (Global Interrupt Enable). Vic thit lp bit ny ln mc cao s cho php tt c cc ngt. Vic xa bit ny s cm tt c cc ngt. Bit 6 T: Bit Copy Storage, c s dng vi lnh np bit BLD (bit load) v lu tr bit BST (bit store) np v lu tr cc bit t 1 thanh ghi v mt thanh ghi khc. Bit 5 H: Half Carry Flag ch bo cho thy s mang sang (nh) mt na trong mt s lnh s hc. Bit 4 S: C du (Sign Flag) bit ny l kt qu EX-OR gia c ph nh Nhng v c trn. Bit 3 V: C trn ly b nh phn. Bit 2 N:C ph nh. Bit 1 Z: C s khng, ch bo mt kt qu bng khng sau khi thc hin mt php tnh s hc hoc logic. Bit 0 C: C mang sang, bo hiu s mang sang trong php tnh s hc hoc logic. Thanh ghi trng thi khng c lu tr bng my trong thi gian din ra mt thao tc ngt. Lnh trong mt on chng trnh ngt c th sa i cc bit trong thanh ghi c trng thi, v v th chng trnh ca ngi dng phi lu tr v khi phc thanh ghi trng thi trong thi gian c mt ngt. 2.3.2.2 THANH GHI CON TR NGN XP SP Thanh ghi ny c rng 2 byte (c gi l SPH v SPL), thanh ghi ny c s dng ch n vng trong b nh SRAM nh ca ngn xp. Ngn xp c s dng lu tr a ch m b x l tr tr li trong thi gian c mt ngt hoc gi th tc bi v SP khi to v $0000 khi reset, nn chng trnh ngi dng cn phi khi to SP cho thch hp. Bi v a ch bt u ca b nh SRAM khng phi l $0000 m l $0060.

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Gii thiu v C AT90S8535

Ngn xp sp xp theo trnh t t trn xung di trong a ch b nh, ngha l vic y mt gi tr ln trn ngn xp s lm cho SP gim i mt gi tr, cn khi ly mt gi tr ra khi ngn xp s lm SP tng thm mt gi tr. 2.3.2.3 THANH GHI CHE NGT CHUNG GIMSK Thanh ghi GIMSK (General Interrupt Mask Register) c s dng cho php hoc cm ngt ngoi ring bit, c th bng cch t ln mc 1 hoc xo xung mc 0 nhng bit tng ng c lin quan. Tuy nhin, ngt no cn s dng th bit I trong thanh ghi trng thi phi c t ln 1.

Bit 7 INT1: External Interrupt Request 1 Enable Khi bit INT1 c set ln 1 v bit I trong thanh ghi trng thi t ln 1 th ngt ngoi INT1 c cho php. Bit 6 INT0: External Interrupt Request 0 Enable Khi bit INT1 c set ln 1 v bit I trong thanh ghi trng thi t ln 1 th ngt ngoi INT0 c cho php. Bit 5 0: bit d tr. 2.3.2.4 THANH GHI C NGT CHUNG GIFR General Interrupt Flag Register

Bit 7 INTF1: External Interrupt Flag1 Khi c mt cnh hoc mc logic thay i trn chn INT1 th c INTF1 c set ln 1, nu bit I trong thanh ghi trng thi v bit INT1 trong thanh ghi GIMSK t ln 1, lc ny MCU s nhy n chng trnh phc v ngt c a ch $002, c ny cng c th xo bng cch vit vo mc 1 cho n. Bit 6 INTF0: External Interrupt Flag0 Khi c mt cnh hoc mc logic thay i trn chn INT0 th c INTF0 c set ln 1, nu bit I trong thanh ghi trng thi v bit INT0 trong thanh ghi GIMSK t ln 1, lc ny MCU s nhy n chng trnh phc v ngt c a ch $001, c ny cng c th xo bng cch vit vo mc 1 cho n. Bit 5 0: bit d tr. Trang 10

Gii thiu v C AT90S8535 2.3.2.5 THANH GHI CHE NGT B NH THI TIMSK Timer/Counter Interrupt Mask Register.

Bit 7 OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable. Khi bit OCIE2 t ln 1 v bit I trong thanh ghi trng thi c t ln 1 khi ngt ng ra so snh timer/counter2 c cho php, c a ch vect ngt $003. Bit 6 TOIE2: Timer/Counter2 Overflow Interrupt Enable. Khi bit TOIE2 t ln 1 v bit I trong thanh ghi trng thi c t ln 1 khi ngt trn timer/counter2 c cho php, c a ch vect ngt $004. Bit 5 TICIE1: Timer/Counter1 Input Capture Interrupt Enable. Khi bit TICIE1 t ln 1 v bit I trong thanh ghi trng thi c t ln 1 khi ngt ng vo Capture timer/counter1 c cho php, c a ch vect ngt $005. Bit 4 OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable. Khi bit OCIE1A t ln 1 v bit I trong thanh ghi trng thi c t ln 1 khi ngt b so snh A timer/counter1 c cho php, c a ch vect ngt $006. Bit 3 OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable. Khi bit OCIE1B t ln 1 v bit I trong thanh ghi trng thi c t ln 1 khi ngt b so snh B timer/counter1 c cho php, c a ch vect ngt $007. Bit 2 TOIE1: Timer/Counter1 Overflow Interrupt Enable. Khi bit TOIE1 t ln 1 v bit I trong thanh ghi trng thi c t ln 1 khi ngt trn timer/counter1 c cho php, c a ch vect ngt $008. Bit 1: bit d tr. Bit 0 TOIE0: Timer/Counter0 Overflow Interrupt Enable. Khi bit TOIE0 t ln 1 v bit I trong thanh ghi trng thi c t ln 1 khi ngt trn timer/counter0 c cho php, c a ch vect ngt $009. 2.3.2.6 THANH GHI C NGT B NH THI TIFR Timer/Counter Interrupt Flag Register

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Gii thiu v C AT90S8535 Bit 7 OCF2: Output Compare Flag 2 Bit OCF2 c t ln 1 khi xut hin so snh gia b timer/counter2 vi d liu trong thanh ghi OCR2 tng ng nhau. Bit ny c xa bi phn cng, khi bit I trong SREG v bit OCIE2 v bit OCF2 c t ln 1, khi ngt so snh tng ng timer/counter2 c xut hin. Bit 6 TOV2: Timer/Counter2 Overflow Flag Bit TOV2 c t ln 1 khi php trn trong timer/counter2 xut hin. Bit ny c xa bi phn cng, khi bit I trong SREG v bit TOIE2 v bit TOV2 c t ln 1, khi ngt trn trong timer/counter2 c xut hin. Trong ch PWM, bit ny c t ln 1 khi timer/counter1 tng t $0000. Bit 5 ICF1: Input Capture Flag 1 Bit ICF1 c t ln 1 khi mt s kin c bt li, gi tr ca timer/counter1 c chuyn vo thanh ghi ICR1. Bit ny c xa bi phn cng, khi bit I trong SREG v bit TICIE1 v bit ICF1 c t ln 1, khi ngt captuer timer/counter1 c xut hin. Bit 4 OCF1A: Output Compare Flag 1A Bit OCF1A c t ln 1 khi xut hin so snh gia b timer/counter1 vi d liu trong thanh ghi OCR1A tng ng nhau. Bit ny c xa bi phn cng, khi bit I trong SREG v bit OCIE1A v bit OCF1A c t ln 1, khi ngt so snh A tng ng timer/counter1 c xut hin. Bit 3 OCF1B: Output Compare Flag 1B Bit OCF1B c t ln 1 khi xut hin so snh gia b timer/counter1 vi d liu trong thanh ghi OCR1B tng ng nhau. Bit ny c xa bi phn cng, khi bit I trong SREG v bit OCIE1B v bit OCF1B c t ln 1, khi ngt so snh B tng ng timer/counter1 c xut hin. Bit 2 TOV1: Timer/Counter1 Overflow Flag Bit TOV1 c t ln 1 khi php trn trong timer/counter1 xut hin. Bit ny c xa bi phn cng, khi bit I trong SREG v bit TOIE1 v bit TOV1 c t ln 1, khi ngt trn trong timer/counter1 c xut hin. Trong ch PWM, bit ny c t ln 1 khi timer/counter1 tng t $0000. Bit 1: bit d tr. Bit 0 TOV0: Timer/Counter0 Overflow Flag Bit TOV0 c t ln 1 khi php trn trong timer/counter0 xut hin. Bit ny c xa bi phn cng, khi bit I trong SREG v bit TOIE0 v bit TOV0 c t ln 1, khi ngt trn trong timer/counter0 c xut hin. Trong ch PWM, bit ny c t ln 1 khi timer/counter1 tng t $0000.

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Gii thiu v C AT90S8535 2.3.2.7 THANH GHI IU KHIN TON B VI IU KHIN MCUCR

Bit 7: bit d tr v lun lun c mc thp. Bit 6 SE: Sleep Enable Bit ny cho php MCU ch ng. Bits 5, 4 SM1, SM0: Sleep Mode Select Bits 1 and 0 Hai bit ny chn ch ng ca MCU.

Bng 2.1: Chn ch ng. Bit 3, 2 ISC11, ISC10: Interrupt Sense Control 1 Bits 1 and 0 Ngt ngoi 1 c tc ng bi chn INT1, nu bit I trong thanh ghi trng thi v bit INT1 trong thanh ghi GIMSK c t ln 1. Chn INT1 tc ng mc hay cnh th c nh ngha trong bng sau:

Bng 2.2: iu khin nhy cm ngt 1. Bit 1, 0 ISC01, ISC00: Interrupt Sense Control 0 Bits 1 and 0 Ngt ngoi 0 c tc ng bi chn INT0, nu bit I trong thanh ghi trng thi v bit INT0 trong thanh ghi GIMSK c t ln 1. Chn INT0 tc ng mc hay cnh th c nh ngha trong bng sau:

Bng 2.3: iu khin nhy cm ngt 0. Trang 13

Gii thiu v C AT90S8535 Ch Tit Kim Nng Lng Vi iu khin AVR c nhiu kh nng gim nng lng tiu th. chuyn sang trng thi ng th bit SE trong thanh ghi MCUCR phi c t ln 1 v lnh Sleep c thc thi. Trong khi MCU ang trng thi ng, nu c mt ngt cho php xut hin th MCU s thc dy thc thi on chng trnh ngt v li tip tc thc thi lnh k tip theo sau lnh Sleep. Lc ny ni dung ca tp thanh ghi, SRAM v b nh I/O vn c gi nguyn. Nu mt tn hiu reset xut hin trong trng thi ng th MCU s thc dy v thc thi t vect reset. Khi bit SM b xa th lnh Sleep bt buc MCU chuyn sang ch ngh, lm ngng hot ng ca CPU nhng cho php b timer/counter watchdog v ngt h thng tip tc hot ng. Bin php ny lm gim dng tiu th trong ch ngh (Idle). Khi CPU c nh thc khi ch ngh, n v CPU khi ng chng trnh chp hnh ngay lp tc. Khi bit SM c t ln 1, lnh Sleep bt buc MCU chuyn sang ch tit kim nng lng hay gim dng tiu th, lc ny b dao ng ngoi b ngng hot ng, trong khi cc ngt ngoi v mch watchdog (nu trng thi cho php hot ng) vn tip tc hot ng. Ch thao tc t li (reset) bn ngoi, thao tc t li watchdog (nu ang trng thi cho php hot ng), hoc ngt theo mc ngoi trn chn INT1 v INT0 mi c th nh thc MCU. 2.3.2.8 THANH GHI IU KHIN TIMER/COUNTER 0 TCCR0 Timer/Counter0 Control Register

Thanh ghi iu khin Timer/Counter0 c s dng iu khin cc thao tc ca b Timer/Counter0. y l mt b nh thi gian n gin dng m tin t gi tr t trc theo tng xung nhp n $FF. Bits 73: bit d tr. Bits 2, 1, 0: CS02, CS01,CS00 Clock Select0 L cc bit chn tn s xung clock cho b timer/counter0. Xem bng sau:

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Gii thiu v C AT90S8535

Bng 2.4: La chn h s chia tn s clock0. C th chn ngun xung clock t 7 trng thi trn v b timer/counter0 s ngng hot ng khi cc bits 2, 1, 0 b xo. 2.3.2.9 THANH GHI TIMER/COUNTER0 TCNT0

y l thanh ghi Timer/Counter hin thi. Mt gi tr c np vo thanh ghi ny c s dng lm gi tr xut pht (bt u), nu b Timer/Counter0 c cho php qua thanh ghi TCCR0 th gi tr xut pht ny s tng theo tng tn hiu xung nhp ca n. Sau khi b Timer/Counter0 b trn, th gi tr ny s c t v $00 v tip tc m tin theo tng tn hiu xung nhp Timer/Counter0.

Hnh 2.6: S khi b timer/counter0. Trang 15

Gii thiu v C AT90S8535 Timer/counter1 B timer/counter1 c 16 bit, c th chn nhiu tn s hot ng cho b timer/counter1, c hai ng ra so snh, PWM, ng vo capture v c ngt trn b nh thi.

Hnh 2.7: S khi b timer/counter1. 2.3.2.10 THANH GHI IU KHIN TIMER/COUNTER1A TCCR1 A

Bits 7, 6 COM1A1, COM1A0 Bit iu khin COM1A1 v COM1A0, ng ra tc ng ln chn OC1A

(PD.5). Bits 5, 4 COM1B1, COM1B0 Bit iu khin COM1B1 v COM1B0, ng ra tc ng ln chn OC1B (PD.4).

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Gii thiu v C AT90S8535

Bng 2.5: Chn ch so snh. Bits 3, 2: bit d tr. Bits 1, 0 PWM11, PWM10 Bit chn hot ng PWM ca timer/counter1.

Bng 2.6: Chn ch PWM. 2.3.2.11 THANH GHI IU KHIN TIMER/COUNTER1B TCCR1 B

Bit 7 ICNC1: Input Capture 1 Noise Canceler (4 chu k) Khi bit ICNC1 bit b xa thnh 0, th chc nng input capture trigger noise canceler b cm. Mch input capture c lt trng thi sn dng/m u tin c ly mu trn chn ICP (Input Capture Pin), nh c ch nh. Khi bit ICNC1 c t thnh 1, 4 mu c ly chn vn trn chn ICP v tt c cc mu cn phi ph hp v mc HIGH/LOW vi thng s k thut v input capture trigger quy nh cho bit ICES1. Tn s ly mu hin thi l tn s ng h XTAL. Bit 6 ICES1: Input Capture1 Edge Select. Khi bit ICES1 c xo thnh 0, th ni dung ca Timer/Counter1 c truyn n thanh ghi ICR1 (Input Capture Register), trn sn m ca chn ICP (Input Capture Pin). Khi bit ICES1 c t thnh 1, th ni dung ca Timer/Counter1 c truyn n thanh ghi ICR1 (Input Capture), trn sn dng ca chn ICP. Bit 5, 4: bit d tr. Trang 17

Gii thiu v C AT90S8535 Bit 3 CTC1: Clear Timer/Counter1 on Compare Match. Khi bit iu khin CTC1 c t thnh 1 b Timer/Counter1 c reset v $0000 trong chu trnh sau mt ln so snh. Nu bit iu khin CTC1 b xa, th b Timer/Counter1 tip tc m v khng b nh hng (tc ng) bi kt qu sau ln so snh . Bi v mi ln so snh c pht hin trong chu k ng h CPU k tip theo ln trc, nn chc nng ny s c thc hin mt cch kh khn khi s chia tn s cao hn 1 c s dng cho b nh thi. Khi s chia tn s bng 1 c s dng v thanh ghi so snh A c t thnh C, th b Timer s m nh sau nu CTC1 c t: |C-2 | C-1 | C | 0 | 1 | Khi b chia tn s c t s chia thnh 8, b nh thi s m ging nh sau y: C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 | Trong ch PWM, bit ny khng c tc dng. Bits 2, 1, 0: Clock Select1. Cc bit Clock Select1 2, 1 v 0 quy nh ngun chia tn s ca b Timer/Counter1 ging nh vi Timer/Counter0.

Bng 2.7: La chn h s chia tn s clock1. 2.3.2.12 THANH GHI TIMER/COUNTER1 TCNT1H,TCNT1L

Thanh ghi 16 ny cha gi tr c em chia tn s ca b Timer/Counter1 16 bit. m bo rng c 2 byte HIGH v LOW c c v ghi ng thi khi khi CPU truy nhp cc thanh ghi ny, vic truy nhp c thc hin bng cc thanh ghi tm thi 8 bit (TEMP). Thanh ghi tm thi ny cng c s dng khi Trang 18

Gii thiu v C AT90S8535 truy nhp OCR1A v ICR1. Nu chng trnh chnh v c on chng trnh ngt cng thc hin vic truy nhp n cc thanh ghi bng cch s dng thanh ghi TEMP, th cc ngt cn phi b cm (disable) trong khong thi gian truy nhp t chng trnh chnh hoc cc ngt truy nhp nu cc ngt c cho php li. TCNT1 Timer/Counter1 Write: Khi CPU ghi vo byte cao (HIGH) TCNT1 H, d liu ghi c t vo trong thanh ghi TEMP. Tip theo, khi CPU ghi byte LOW TCNT1L, byte d liu ny c kt hp vi byte d liu trong thanh ghi TEMP, v ton b 16 bit c ghi ng thi vo thanh ghi TCNT1 Timer/Counter1. Do , byte HIGH TCNT1H cn phi c truy nhp trc tin i vi thao tc ghi trn vn thanh ghi 16 bit. TCNT1 Timer/Counter1 Read: Khi khi CPU c byte thp (LOW) TCNT1 L, d liu ca byte LOW TCNT1L c gi ti CPU v d liu ca byte HIGH TCNT1H b thay th trong thanh ghi TEMP. Khi khi CPU c d liu trong byte HIGH TCNT1H, th CPU nhn d liu trong thanh ghi TEMP. Do , byte LOW TCNT1L cn phi c truy nhp trc tin i vi thao tc c trn vn thanh ghi 16 bit. B Timer/Counter1 c thit k hot ng nh mt b m tin hoc tin/li (trong ch PWM) vi thao tc truy nhp c v ghi. Nu b Timer/Counter1 c ghi vo v mt ngun xung nhp c la chn th b Timer/Counter1 tip tc m trong chu trnh ng h. 2.3.2.13 CC THANH GHI SO SNH TIMER/COUNTER1 A OCR1AH, OCR1AL LI RA B

2.3.2.14 CC THANH GHI SO SNH TIMER/COUNTER1 B OCR1BH, OCR1BL

LI

RA

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Gii thiu v C AT90S8535 Cc thanh ghi so snh li ra (output compare) l cc thanh ghi c/ghi 16 bit. Cc thanh ghi so snh li ra b Timer/Counter1 cha d liu c so snh lin tc vi Timer/Counter1. Din bin ca nhng ln so snh c ch nh trong thanh ghi iu khin v trng thi Timer/Counter1. Mt ln so snh ch xy ra nu Timer/Counter1 m n gi tr OCR. Mt ln so snh s t c ngt so snh trong chu k ng h CPU k tip theo s kin so snh. Bi v cc thanh ghi so snh li ra OCR1A v OCR1B l cc thanh ghi 16 bit, nn mt thanh ghi tm thi TEMP c s dng khi OCR1A/B c ghi bo m l c 2 byte c cp nht ng thi. Khi CPU ghi byte cao (HIGH) OCR1AH hoc OCR1BH, d liu c lu tr tm thi vo thanh ghi TEMP. Sau khi CPU ghi byte thp (LOW) OCR1AL hoc OCR1BL, t kt hp vi thanh ghi TEMP ghi ng thi vo OCR1AH hoc OCR1BH. Do , byte cao (HIGH) OCR1AH hoc OCR1BH cn phi c ghi trc tin i vi mt thao tc ghi trn vn thanh ghi 16 bit. Thanh ghi TEMP cng c s dng khi truy nhp TCNT1 v ICR1. Nu chng trnh chnh v cc on chng trnh ngt thc hin vic truy nhp n cc thanh ghi bng cch s dng TEMP, cc ngt cn phi b cm trong thi gian truy nhp t chng trnh chnh hoc cc ngt c truy nhp nu cc ngt c cho php. 2.3.2.15 THANH GHI TIMER/COUNTER INPUT CAPTURE ICR1H, ICR1L

Thanh ghi input capture l cc thanh ghi 16 bit ch c. Khi sn dng, sn m ca tn hiu chn input capture (ICP) c pht hin. khi gi tr hin thi ca b Timer/Counter1 c truyn n thanh ghi Input Capture (ICR1). ng thi c input capture (ICF1) c t thnh 1. Bi v cc thanh ghi input capture (ICR1) l cc thanh ghi 16 bit, nn mt thanh ghi tm thi TEMP c s dng khi ICR1 c c bo m l c 2 byte c c ng thi. Khi CPU c byte cao (LOW) ICR1L, d liu c gi n khi CPU v d liu ca byte cao (HIGH) ICR1H c t vo thanh ghi TEMP, khi khi CPU c d liu byte cao (HIGH) ICR1H th khi CPU nhn d liu t trong thanh ghi TEMP. Do , byte thp (LOW) ICR1L cn phi c truy nhp trc tin i vi mt thao tc c trn vn thanh ghi 16 bit.

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Gii thiu v C AT90S8535 Thanh ghi TEMP cng c s dng khi truy nhp TCNT1 v OCR1A. Nu chng trnh chnh v cc on chng trnh ngt thc hin vic truy nhp n cc thanh ghi bng cch s dng TEMP, th cc ngt cn phi b cm trong thi gian truy nhp t chng trnh chnh hoc cc ngt truy nhp nu cc ngt c cho php. Timer/Counter2 S khi b timer/counter2: B timer/counter2 c 8 bit, c th chn nhiu tn s hot ng cho b timer/counter2.

Hnh 2.8: S khi b timer/counter2. 2.3.2.16 THANH GHI IU KHIN TIMER/COUNTER2 TCCR2

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Gii thiu v C AT90S8535 Bit 7: bit d tr. Bit 6 PWM2: Pulse Width Modulator Enable Khi bit ny c t ln 1 th ch PWM ca timer/counter2 c cho php. Bits 5, 4 COM21, COM20: Compare Output Mode, Bits 1 and 0 Bit iu khin COM21 v COM20, ng ra tc ng ln chn OC2 (PD.7).

Bng 2.8: Chn ch so snh. Bit 3 CTC2: Clear Timer/Counter on Compare Match Khi bit iu khin CTC2 c t thnh 1 b Timer/Counter2 c reset v $00 trong chu trnh sau mt ln so snh. Nu bit iu khin CTC2 b xa, th b Timer/Counter2 tip tc m v khng b nh hng (tc ng) bi kt qu sau ln so snh . Bi v mi ln so snh c pht hin trong chu k ng h CPU k tip theo ln trc, nn chc nng ny s c thc hin mt cch kh khn khi s chia tn s cao hn 1 c s dng cho b nh thi. Khi s chia tn s bng 1 c s dng, v thanh ghi so snh 2 c t thnh C, th b Timer s m nh sau nu CTC2 c t: Khi b chia tn s c t s chia thnh 8, b nh thi s m ging nh sau y: | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C1, C-1 | C, 0, 0, 0, 0, 0, 0, 0, Trong ch PWM, bit ny khng c tc dng. Bits 2, 1, 0 CS22, CS21,CS20: Clock Select Bits 2, 1 and 0 Cc bit Clock Select2 2, 1 v 0 quy nh ngun chia tn s ca b Timer/Counter2.

Bng 2.9: La chn h s chia tn s cho timer/counter2. Trang 22

Gii thiu v C AT90S8535 2.3.2.17 THANH GHI SO SNH NG RA TIMER/COUNTER2 OCR2 L thanh ghi c/vit 8 bit.

y l thanh ghi cha d liu dng so snh vi timer/counter2. Mt so snh ch c xut hin khi timer/counter2 m trng vi gi tr trong OCR2. Ch PWM trong timer/counter2 Khi ch PWM c chn, gi tr trong timer/counter2 c so snh vi thanh ghi OCR2 v ng ra ca PWM trn chn PD7 (OC2), timer/counter2 m t $00 n $FF v m t gi tr nh v $00. Khi gi tr trong timer/counter2 bng vi gi tr trong OCR2 th ng ra trn chn PD7 s thay i. Khi ta chn ch PWM khng o, lc ny gi tr trong thanh ghi OCR2 cng ln th rng xung dng cng rng, v ngc li. Khi ta chn ch PWM o, lc ny gi tr trong thanh ghi OCR2 cng ln th rng xung dng cng hp, v ngc li. B WATCHDOG TIMER

Hnh 2.9: S khi b watchdog timer. 2.3.2.18 THANH GHI IU KHIN B NH THI WATCHDOG TIMER WDTR Bits 7..5: bit d tr. Bit 4 WDTOE: Watchdog Turn off Enable Bit ny c s dng chung vi bit WDE. Khi WDTOE =1 v WDE=0 cm b nh thi Watchdog. Trang 23

Gii thiu v C AT90S8535 Bit 3 WDE: Watchdog Enable Khi WDE= 1 b nh thi Watchdog c cho php v WDE= 0 b nh thi Watchdog b cm. cm b nh thi ny ta cn thc hin cc bc sau: - Trong mt chu k n l t WDTOE= WDE= 1. - Xa WDE= 0 trong 4 chu k ng h tip theo => b nh thi s b cm. Bits 2..0 WDP2, WDP1, WDP0: Watchdog Timer Prescaler Cc bit ny c dng chia tn s khi b nh thi Watchdog c cho php. Cc khong chia tn s khc nhau tng ng vi cc khong time-out.

Bng 2.10: La chn h s chia tn s ca b nh thi watchdog. 2.3.3 B NH EEPROM B nh EEPROM c truy nhp qua cc thanh ghi truy nhp EEPROM, c th l: thanh ghi a ch EEPROM (EEAR), thanh ghi d liu EEPROM (EEDR) v thanh ghi iu khin EEPROM (EECR). Thanh ghi EEAR l mt thanh ghi c/ghi.

Thanh ghi EEDR l mt thanh ghi d liu b nh EEPROM v l mt thanh ghi c/ghi. Khi ta mun c d liu t b nh EEPROM, th ta phi ch sau khi qu trnh ghi thc hin xong.

Thanh ghi EECR c cc bit iu khin cn thit cho vic c v ghi vo b nh EEPROM. Trang 24

Gii thiu v C AT90S8535

Bit iu khin EEWE trong thanh ghi EECR cho php ngi dng pht hin khi mt lng d liu yu cu trc c ghi vo b nh EEPROM v mt d liu byte mi c th c ghi. 2.3.4 KHI S HC LOGIC Khi s hc logic (hnh 22) thc hin cc thao tc ging nh thao tc bit, php tnh s hc v logic trn ni dung ca cc thanh ghi v ghi c kt qu vo tp thanh ghi trn thanh ghi c ch nh. Cc thao tc ny c thc hin trong mt chu k n l. Mi mt thao tc ALU u lm nh hng n cc c trong thanh ghi trng thi (Status), ty thuc vo lnh. 2.3.5 TRUY CP B NH Vic truy nhp b nh SRAM chim mt 2 chu k. Nguyn nhn l vic truy nhp b nh SRAM s dng mt thanh ghi con tr dng cho a ch b nh SRAM. Thanh ghi trong con tr ny ch l mt trong cc thanh ghi con tr (Cc thanh ghi X, Y hoc Z). Chu k ng h th nht c cn n truy nhp tp thanh ghi v thao tc trn thanh ghi con tr (cc lnh truy nhp b nh SRAM cho php gia tng a ch trc/sau thao tc trn thanh ghi con tr). thi im kt thc ca chu k ng h th nht, khi ALU thc hin php tnh ny, v sau a ch ny c s dng truy nhp nh SRAM v ghi vo nh ny (hoc c ra t vo thanh ghi ch). 2.3.6 CNG VO/RA Tt c cc b iu khin AVR u c mt lng ln cc cng vo/ra (I/O). Tt c cc li ra (c t nh cc bit) ca cc b iu khin AVR c th chu dng in n 20 mA, nn rt thch hp vi vic iu khin trc tip cc LED v khng cn n mch m b sung. Tt c cc cng vo/ra u c 3 a ch vo ra i km vi chng. Ba a ch vo ra c cn n t cu hnh cho cc bit ring bit thnh cc li vo hoc thnh li ra, a ch khc c cn n xut ra d liu ti cc bit (hoc tt c) c t cu hnh thnh li ra, v a ch th 3 c cn n c d liu t cc chn (hoc tt c) c cu hnh thnh li vo. Cc cng c nh s l DDRx, PINx, PORTx cho mt cng x cho trc. Cng DDRx l thanh ghi hng d liu. Khi ghi mt mc 1 vo mt bit DDR lm cho bit tng ng thnh bit li ra trong PORTx. Sau xut mt gi tr 1 trn bit cng, bit tng ng c th c t hoc reset bng cch s dng CBI hoc SBI hoc mt lnh OUT. Mt cch khc thay i gi tr cng l s dng cc lnh IN v OUT. Tng t c d liu trong li vo ca mt cng ta s dng thanh ghi PINx. Thanh ghi PINx c ni trc tip vi chn ca cng. Chn cng c th c Trang 25

Gii thiu v C AT90S8535 cp tn hiu duy tr trng thi theo cch to mc in p cao (pull- up) bn trong bng cch ghi gi tr 1 vo bit cng cc a ch PORTx. Cc in tr pull-up ny c gi tr trong khong t 20 k v 150 k. Cc gi tr tng ng ca dng in pull-up nm gia 160 A v 33 A. Ngc li, nu mt gi tr 0 c ghi vo bit cng a ch PORTx, th trng thi pull-up c loi b v chn li vo ri b trng thi th ni chuyn sang trng thi tr khng cao. 2.3.7 B TRUYN NHN UART

Hnh 2.10: S khi b truyn nhn UART. Vic truyn d liu c khi to bng cch ghi d liu vo thanh ghi d liu I/O UART, k hiu l UDR. D liu c truyn t UDR n thanh ghi dch truyn khi: Mt k t mi c ghi vo UDR sau khi bit stop (bit dng) t k t trc dch chuyn ra. Thanh ghi dch chuyn c np ngay lp tc. Mt k t mi c ghi vo UDR trc khi bit stop t k t trc c dch i (shifted out). Thanh ghi dch c np khi bit stop ca k t ang c truyn c dch chuyn ra. Nu thanh ghi dch b truyn 10 (11) bit ang trng th d liu c truyn t UDR n thanh ghi dch. thi im ny bit UDRE (UART Data Register Empty) trong thanh ghi trng thi UART, USR, c t. Khi bit ny c t thnh 1, b UART ang sn sng nhn k t tip theo. Vo cng thi im

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Gii thiu v C AT90S8535 khi d liu c truyn t UDR n thanh ghi dch b truyn 10 (11) bit, bit 0 ca thanh ghi dch b xo ( start bit) v bit 9 hoc 10 c t (stop bit). Nu nh mt t d liu 9 bit c la chn (bit CHR9 trong thanh ghi iu khin UART, UCR c t), bit TXB8 trong thanh ghi UCR c truyn vo bit 9 trong thanh ghi dch b truyn, theo nhp ca ng h tc Baud s din ra cuc truyn n thanh ghi dch, bit start b dch chuyn ra chn TXD. Sau k tip l d liu, LSB trc tin. Khi bit stop c dch chuyn ra, thanh ghi dch c np nu bt k d liu no c ghi vo thanh ghi UDR trong khong thi gian truyn. Trong thi gian np, bit UDRE c t thnh 1. Nu nh khng c d liu mi trong thanh ghi UDR truyn khi bit stop c dch chuyn ra, c UDRE s gi nguyn trng thi c t cho n khi thanh ghi UDR c ghi mt ln na. Khi khng c d liu mi cn c ghi, v bit stop c mt trn TxD i vi mt chiu di bit, C TX Complete, TXC, trong thanh ghi USR c t thnh 1. Bit TXEN trn thanh ghi UCR cho php b truyn UART khi t thnh 1. Khi bit ny b xo thnh 0, th chn PD1 c th s dng cho thao tc I/O chung. Khi t thnh 1, b truyn trong UART s c ni vi PD1, chn ny b bt buc thnh mt chn li ra khng m xa g n vic t ca bit 1 trong DDRD. Khi logic front-end ca b nhn ly khi tn hiu trn chn RxD tn s 16 ln tc Baud. Khi ng dn khng c tn hiu truyn (ang trong trng thi ngh), mt mu n l ca gi tr logic 0 s c dch nh sn m (dc xung) ca mt bit start, v dy pht hin bit start c khi to. Hy xem nh mu 1 l mu 0 u tin. Tip theo l s dch chuyn mc t 1 sang 0. B nhn ly mu chn RxD cc mu 8, 9 v 10. Nu nh 2 hoc nhiu hn trong 3 mu c tm thy c gi tr logic 1 th t bit start b loi b nh mt xung nhiu v b nhn bt u theo di s chuyn mc k tip t 1 sang 0. Tuy nhin mt bit start hp l c pht hin, th vic ly cc mu bit k tip bit start c thc hin. Cc bit ny cng c ly mu cc mu 8, 9 v 10. Gi tr logic c tm thy t nht 2 trong s 3 mu c ly lm gi tr bit. Tt c cc bit c dch chuyn vo thanh ghi dch chuyn vo thanh ghi dch b truyn ging nh chng ta c ly mu. Khi bit stop c a vo b nhn, th a s trong s 3 mu cn phi bng 1 tip nhn bit stop. Nu nh hai mu hoc nhiu hn l cc gi tr logic 0, th c li khung truyn (FE) trong thanh ghi trng thi UART (USR) c t thnh 1. Trc khi c thanh ghi UDR, ngi dng phi lun lun kim tra bit li FE pht hin cc li khung truyn. Tu thuc vo c hay khng c mt bit stop hp l c pht hin cui mt chu k tip nhn k t, d liu c truyn n UDR v c RXC trong thanh ghi USR c t. UDR trn thc t l hai thanh ghi tch bit v mt vt l, mt dng cho d liu c truyn v mt dng cho d liu c nhn. Khi UDR c c, thanh ghi d liu nhn (Receive Data Register) c truy nhp, v khi UDR c ghi, thanh ghi d liu truyn (Transmit Data Register) c truy nhp. Trang 27

Gii thiu v C AT90S8535 Nu d liu 9 bit c la chn (bit CHR9 (trong thanh ghi iu khin UART, UCR c t thnh 1), bit RXB8 trong thanh ghi UCR c np bng 9 bit trong thanh ghi dch truyn khi d liu c truyn ti UDR. Nu nh sau khi nhn c mt k t, thanh ghi UDR khng c c k t ln nhn cui cng, c trn OverRun (OR) trong thanh ghi UCR c t thnh 1. iu ny c ngha l byte d liu cui cng dch chuyn vo thanh ghi dch s khng c chuyn n UDR v b tht lc. Bit OR c m v c cp nht khi byte d liu hp l trong thanh ghi UDR c c. Nh vy ngi dng lun phi kim tra bit OR trc tin, sau khi c thanh ghi UDR, pht hin bt k li trn no xut hin. Khi bit RXEN trong thanh ghi UCR b xo thnh 0, th b phn b cm. iu c ngha l chn PD0 c th c s dng lm mt chn I/O chung. Khi RXEN c t thnh 1, b nhn UART s c ni vi PD0, chn ny b buc phi tr thnh mt chn li vo khng m xa g n vic t ca bit DDRD trong DDRD. Khi PD0 b bt buc tr thnh li vo bi UART, bit PORTD0 c th vn c s dng iu khin in tr pull-up trn chn. Khi bit CHR9 trong thanh ghi UCR c t, cc k t c truyn v c nhn c di 9 bit, cng thm bit start v bit stop. Bit d liu th 9 cn c truyn l bit TXB8 trong thanh ghi UCR. Bit ny cn phi c t thnh gi tr mong mun trc khi mt cuc truyn c khi to bng vic ghi vo thanh ghi UDR. Bit th 9 nhn c l bit RXB8 trong thanh ghi UCR. 2.3.7.1 THANH GHI D LIU UART UDR UART I/O Data Register

Thc t l hai thanh ghi s dng chuyn a ch vt l. Khi d liu c ghi vo a ch ny, n ghi vo thanh ghi truyn d liu. Khi c t a ch ny n c t thanh ghi nhn d liu. 2.3.7.2 THANH GHI TRNG THI UART USR UART Status Register

Bit 7 RXC: UART Receive Complete Khi bit ny c t thnh 1 c ngha l UART nhn xong mt byte t thanh ghi dch b nhn. RXC c xo bng vic c.

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Gii thiu v C AT90S8535 Bit 6 TXC: UART Transmit Complete Bit ny c t thnh 1, khi mt byte d liu y bao gm bit stop c dch chuyn ra t thanh ghi dch b truyn v khng c d liu mi c ghi vo UDR. TXC b xa thnh 0 bng phn cng bng cch thc thi trnh x l ngt tng ng hoc bng phn mm bng cch ghi gi tr 1 vo bit TXC. Bit 5 UDRE: UART Data Register Empty Bit ny c t thnh 1, khi d liu ghi vo UDR c truyn n thanh ghi dch b truyn. Bit ny cho thy UART sn sng nhn mt byte mi. Bit 4 FE: Framing Error Bit ny c t thnh 1 khi bit stop truyn n c gi tr l 0. Bit ny c xo khi bit stop c a n c gi tr l 1. Bit 3 OR: OverRun Bit ny c t thnh 1 khi d liu trong UDR khng c c trc khi d liu mi dch chuyn vo UDR t thanh ghi b nhn. Bit 2, 1, 0: bit d tr. 2.3.7.3 THANH GHI IU KHIN UART

Bit 7 RXCIE: RX Complete Interrupt Enable Bit 6 TXCIE: TX Complete Interrupt Enable Bit 5 UDRIE: UART Data Register Empty Interrupt Enable Khi bit ny c t thnh 1 v bit UDRE trong thanh ghi USR t thnh 1, th ngt UDRE s c thc thi nu bit I trong thanh ghi trng thi (ngt ton cc) c t. Bit 4 RXEN: Receive Enable Khi bit ny c t thnh 1 b nhn UART c cho php. Bit 3 TXEN: Transmit Enable Khi bit ny c t thnh 1 b truyn UART c cho php. Bit 2 CHR9: 9 bit Characters Khi bit ny c t thnh 1, ngha l k t truyn v nhn c di 9 bit bn cnh bit start v bit stop. Bit th 9 c th s dng nh bit stop ph hay bit kim tra chn l. Bit 1 RXB8: Receive Data Bit 8 Khi CHR9 c t thnh 1 th bit RXB8 l bit th 9 ca k t nhn. Bit 0 TXB8: Transmit Data Bit 8 Khi CHR9 c t thnh 1 th bit TXB8 l bit th 9 ca k t truyn. 2.3.8 CU TRC NGT B vi iu khin AVR c rt nhiu cu trc ngt. Mt lot cc s kin c th k ra khi mt ngt xut hin l: 1. Thit b ngoi vi ngt b x l. 2. Vic thc thi lnh hin ti c hon thnh. Trang 29

Gii thiu v C AT90S8535 3. a ch ca lnh tip theo c lu tr trn ngn xp (hoc mt ngn xp phn cng hoc mt ngn xp phn mm). 4. a ch ISR (on chng trnh ngt) c np vo b m chng trnh. 5. B x l thc thi ISR. 6. Vic hon thnh cc thao tc thc thi ISR c ch bo bng lnh RETI (tr li t ngt). 7. B x l np b m chng trnh vi gi tr c lu tr trn ngn xp v vic thc thi chng trnh bnh thng li tip tc. Bi v ngt c th xut hin bt c lc no nn trng thi b x l (cc c, ) cn phi c lu tr sao cho vic thc thi chng trnh bnh thng c th tip tc ngay sau khi on chng trnh ISR c hon tt. Trng thi b x l c cha trong thanh ghi SREG. Trc khi thc hin chng trnh ISR cn phi lu tr thanh ghi SREG ri mi thc thi chng trnh ngt v trc khi tr li vic iu khin chng trnh chnh, ta cn phi khi phc li thanh ghi SREG. Mt cch lu tr thanh ghi SREG l lu n trn ngn xp (bng cch s dng lnh PUSH SREG) v sau trc khi thc thi lnh RETI, gi tr thanh ghi SREG c sao chp ngc tr li t ngn xp (bng cch s dng lnh POP SREG). Trong lc mt ngt ISR1 hot ng, c mt ngt khc (ISR2) xut hin v c ngt ton cc c t thnh 1 bn trong ISR1( bng cch s dng lnh SEI). Trong trng hp ny, ngt ISR1 b ngt v ngt ISR2 c thc thi. Vic thc thi ISR1 li tip tc sau khi ISR2 kt thc, v sau khi thc thi xong ISR1 chng trnh chnh li c thc thi tip tc. Bnh thng th sau khi mt ngt xut hin v ang c phc v bi thanh ghi ISR tng ng, cc ngt ton cc t ng b cm (tng ng vi vic thc thi lnh CLI); tuy nhin vn c kh nng cho php cc ngt trong khi mt ISR ang thc thi bng vic thc thi lnh SEI trong ISR. Nu nh ngt khc xut hin trong khong thi gian khi mt ISR ang hot ng, th n s phc v bng vic ngt on chng trnh ISR ban u. Tnh u tin ca cc ngt c quy nh bi cch gn cc vect ngt. Mt vect ngt a ch thp hn trong b nh chng trnh c mc u tin cao hn. Vic thc thi ngt i vi tt c cc ngt AVR c cho php t nht l 4 chu k ng h. Bn chu k ng h sau khi c ngt c t, chng trnh vect a ch dng cho on chng trnh x l ngt hin ti c thc thi. Trong khong thi gian 4 chu k ny, b m chng trnh (2 byte) c y ln ngn xp v con tr ngn xp b gim i 2. Vect thng l mt lnh nhy tng i n on chng trnh ngt, v thao tc nhy ny chim 2 chu k ng h. Trang 30

Gii thiu v C AT90S8535 Nu nh mt ngt xut hin khi ang thc thi mt lnh chim nhiu chu k (multicycle), lnh ny c hon thnh trc khi ngt c phc v. Vic quay tr li t mt on chng trnh x l ngt chim 4 chu k ng h. Trong 4 chu k ng h ny b m chng trnh (2 byte) c y ngc tr li t ngn xp, con tr ngn xp c tng thm 2, v c I trong thanh ghi SREG c t. Khi vi iu khin AVR thot ra khi mt ngt, n s lun tr v vi chng trnh chnh v chp hnh lnh k tip trc khi bt k c ngt no ang ch c phc v. 2.3.9 B SO SNH ANALOG B so snh analog so snh cc gi tr in p li vo, c th l li vo AIN0 (AC+) v AIN1 (AC-) vi nhau. Nu nh in p li vo AIN0 ln hn li vo AIN1 th li ra ca b so snh analog ACO (Analog Comparator Out) c t ln mc 1. Li ra ny c th c s dng cho b Timer/Counter1 trig hoc xo ngt b so snh analog. B so snh analog c iu khin qua thanh ghi iu khin v trng thi b so snh analog, thng c vit tt l ACSR, a ch $08 trong vng a ch vo/ra hoc a ch $28 trong vng a ch b nh d liu.

Hnh 2.11: S khi b so snh analog.

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Gii thiu v C AT90S8535 2.3.10 TP LNH DNG CHO AVR

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Gii thiu v C AT90S8535

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