Ti liu Lp trnh h thng

Chng 1

Chng 1 KIN TRC V HOT NG CA H VI X L / MY TNH

1. Cu trc lun l
My tnh s (Digital computer) l my gii quyt cc vn bng cch thc hin cc ch th do con ngi cung cp. Chui cc ch th ny gi l chng trnh (program). Cc mch in t trong mt my tnh s s thc hin mt s gii hn cc ch th n gin cho trc. Tp hp cc ch th ny gi l tp lnh ca my tnh. Tt c cc chng trnh mun thc thi u phi c bin i sang tp lnh trc khi c thi hnh. Cc lnh c bn l: Cng 2 s. So snh vi 0. Di chuyn d liu.

Tp lnh ca my tnh to thnh mt ngn ng gip con ngi c th tc ng ln my tnh, ngn ng ny gi l ngn ng my (machine language). Tuy nhin, hu ht cc ngn ng my u n gin nn thc hin mt yu cu no , ngi thit k phi thc hin mt cng vic phc tp. l chuyn cc yu cu ny thnh cc ch th c cha trong tp lnh ca my. Vn ny c th gii quyt bng cch thit k mt tp lnh mi thch hp cho con ngi hn tp lnh ci t sn trong my (built-in). Ngn ng my s c gi l ngn ng cp 1 (L1) v ngn ng va c hnh thnh gi l ngn ng cp 2 (L2). Tuy nhin, trong thc t, c th thc hin c, cc ngn ng L1 v L2 khng c khc nhau nhiu. Nh vy, ngn ng L2 cng khng tht s gip ch nhiu cho ngi thit k. Do , mt tp lnh k tip c hnh thnh s hng v con ngi nhiu hn l my tnh, tp lnh ny s to thnh mt ngn ng v ta gi l ngn ng L3. Ta c th vit cc chng trnh trong L3 nh l tn ti my tnh s dng ngn ng L3 (my o L3). Cc chng trnh ny s c dch sang ngn ng L2 v c thc thi bng mt chng trnh dch L2. Vic xy dng ton b chui cc ngn ng, mi ngn ng c to ra s thch hp hn ngn ng trc s c th tip tc cho n khi nhn c ngn ng thch hp nht. S mt my o n cp c th biu din nh sau:

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Cp n

My o Mn dng ngn ng my Ln

Chng trnh trong Ln c dch thnh ngn ng ca my cp thp hn

Cp 3

My o M3 dng ngn ng my L3

Chng trnh trong L3 c dch thnh ngn ng L2 hay L1

Cp 2

My o M2 dng ngn ng my L2

Chng trnh trong L2 c dch thnh ngn ng my L1

Cp 1

My tnh s M1 dng ngn ng my L1

Chng trnh trong L1 c thc thi trc tip bng cc mch in t

Hnh 1.1. My o n cp

Mt my tnh s c n cp c th xem nh c n-1 my o khc nhau, mi my o c mt ngn ng my ring. Cc chng trnh vit trn cc my o ny khng th thc thi trc tip m phi dch thnh cc ngn ng my cp thp hn. Ch c my tht dng ngn ng my L1 mi c th thc thi trc tip bng cc mch in t. Mt lp trnh vin s dng my o cp n khng cn bit tt c cc trnh dch ny. Chng trnh trong my o cp n s c thc thi bng cch dch thnh ngn ng my cp thp hn v ngn ng my ny s c dch thnh ngn ng my thp hn na hay dch trc tip thnh ngn ng my L1 v thc thi trc tip trn cc mch in t.

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V c bn, my tnh gm c 6 cp:

Cp 5 Cp ngn ng hng vn Dch (chng trnh dch) Cp 4 Cp ngn ng hp dch Dch (hp dch) Cp 3 Cp h iu hnh Dch 1 phn (h iu hnh) Cp 2 Cp my quy c Thng dch (vi chng trnh) Cp 1 Cp vi lp trnh Vi chng trnh (phn cng) Cp 0 Cp logic s Hnh 1.2 Cc cp trn my tnh s

Cp 0 chnh l phn cng ca my tnh. Cc mch in t ca cp ny s thc thi cc chng trnh ngn ng my ca cp 1. Trong cp logic s, i tng quan tm l cc cng logic. Cc cng ny c xy dng t mt nhm cc transistor. Cp 1 l cp ngn ng my tht s. Cp ny c mt chng trnh gi l vi chng trnh (microprogram), vi chng trnh c nhim v thng dch cc ch th ca cp 2. Hu ht cc lnh trong cp ny l di chuyn d liu t phn ny n phn khc ca my hay thc hin vic mt s kim tra n gin. Mi my cp 1 c mt hay nhiu vi chng trnh chy trn chng. Mi vi chng trnh xc nh mt ngn ng cp 2. Cc my cp 2 u c nhiu im chung ngay c cc my cp 2 ca cc hng sn xut khc nhau. Cc lnh trn my cp 2 c thc thi bng cch thng dch bi vi chng trnh m khng phi thc thi trc tip bng phn cng. Cp th 3 thng l cp hn hp. Hu ht cc lnh trong ngn ng ca cp my ny cng c trong ngn ng cp 2 v ng thi c thm mt tp lnh mi, mt t chc b
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nh khc v kh nng chy 2 hay nhiu chng trnh song song. Cc lnh mi thm vo s c thc thi bng mt trnh thng dch chy trn cp 2, gi l h iu hnh. Nhiu lnh cp 3 c thc thi trc tip do vi chng trnh v mt s lnh khc c thng dch bng h iu hnh (do , cp ny l cp hn hp). Cp 4 tht s l dng tng trng cho mt trong cc ngn ng. Cp ny cung cp mt phng php vit chng trnh cho cc cp 1, 2, 3 d dng hn. Cc chng trnh vit bng hp ng c dch sang cc ngn ng ca cp 1, 2, 3 v sau c thng dch bng cc my o hay thc tng ng. Cp 5 bao gm cc ngn ng c thit k cho ngi lp trnh nhm gii quyt mt vn c th. Cc ngn ng ny c gi l cp cao. Mt s ngn ng cp cao nh Basic, C, Cobol, Fortran, Lisp, Prolog, Pascal v cc ngn ng lp trnh hng i tng nh C++, J++, Cc chng trnh vit bng cc ngn ng ny thng c dch sang cp 3 hay 4 bng cc trnh bin dch (compiler).

2. Giao tip ngoi vi

Ta phn bit tt c 3 phng php xut / nhp d liu: Nhp / xut bng cch hi trng thi ca thit b ngoi vi (polling) Nhp / xut bng ngt (interrupt). Nhp / xut bng cch truy xut trc tip vo b nh dng cc phn cng ph tr (DMA).

2.1. Nhp / xut d liu bng cch hi vng (polling) Ta bit rng vn iu khin nhp / xut d liu s rt n gin trong trng hp thit b ngoi vi lc no cng c th lm vic vi P. Ta c th v d nh b hin th Led 7 on lc no cng sn sng hin th d liu khi m P gi d liu ra. Tuy nhin, trong thc t, khng phi lc no P cng lm vic vi cc thit b ngoi vi c tnh nng nh trn. V d nh khi lm vic vi mt my in, P yu cu in nhng my in khng sn sng (gi s nh ht giy, kt giy, ). Khi , P phi kim tra xem mt thit b m n cn giao tip c sn sng hay khng nu thit b sn sng th mi thc hin trao i d liu. kim tra cc thit b ngoi vi, P phi s dng cc tn hiu bt tay (handshake) xc nh tun t tng thit b, xem thit b no c yu cu trao i d liu. Cc tn hiu ny ly t cc mch giao tip do ngi thit k to ra. Gi s h thng c 2 thit b ngoi vi, nu thit b 1 c d liu cn truyn n P th n s gi 1 xung cht d liu ng thi to tn hiu sn sng cho thit b. Khi P kim tra tn hiu sn sng ca thit b 1 th n s c d liu vo t mch cht v xo tn hiu sn sng. Trong trng hp P mun gi d liu ra thit b 2, n s c tn hiu sn sng ca thit b 2, nu thit b 2 c th nhn d liu th P s gi d liu ra mch cht v thit b 2 s c d liu vo.

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2.2. Ngt v x l ngt Trong cch thc thc hin trao i d liu bng cch hi vng nh trn, trc khi tin hnh thc hin th P phi kim tra trng thi sn sng ca thit b ngoi vi. Tuy nhin trong thc t ta cn phi tn dng kh nng ca P lm cc cng vic khc m khng phi tn thi gian kim tra thit b, ch khi no c yu cu trao i d liu th mi tm dng cng vic hin ti. Cch lm vic nh vy gi l ngt P, khi c mt ngt xy ra th ta phi thc hin gi cc chng trnh phc v ngt ti cc a ch xc nh ca P. Cc tn hiu ngt t thit b ngoi vi a vo P thng qua cc chn NMI hay INTR. 2.2.1. Cc loi ngt Ngt cng: l cc yu cu ngt t cc chn NMI hay INTR. Ngt cng NMI l ngt khng che c cn ngt cng INTR c th che c. Cc lnh CLI (Clear Interrupt) v STI (Set Interrupt) ch nh hng n vic P c chp nhn yu cu ngt ti chn INTR hay khng. Yu cu ngt ti chn INTR c th c cc kiu ngt t 00h FFh. Kiu ngt ny s c a vo bus d liu P xc nh kiu ngt (dng cho cc thit b ngoi vi khc nhau).
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

74LS245 VCC 1 19 9 8 7 6 5 4 3 2 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 1 2 3 4 8 5 6 11 12 DIR G A8 A7 A6 A5 A4 A3 A2 A1 B8 B7 B6 B5 B4 B3 B2 B1 11 12 13 14 15 16 17 18

VCC GND AD15 AD14 A16/S3 AD13 A17/S4 AD12 A18/S5 AD11 A19/S6 AD10 BHE/S7 AD9 MN/MX AD8 RD AD7 AD6 HOLD (RQ/GT0) AD5 HLDA (RQ/GT1) WR (LOCK) AD4 IO/M (S2) AD3 DT/R (S1) AD2 DEN (S0) AD1 ALE (QS0) AD0 INTA (QS1) NMI INTR TEST CLK READY GND RESET 8086

Hnh 1.3 Kt ni ngt n gin Ngt mm: l cc ngt thc hin bng phn mm tc ng do ngi s dng. 2.2.2. p ng ca P khi c yu cu ngt Khi c yu cu ngt n P v nu c php ngt, P s thc hin cc cng vic sau: [SP] SP 2, [SP] FR (Flag Register): ct thanh ghi c vo stack. IF 0, TF 0: khng cho thc hin cc ngt khc. SP SP 2, [SP] CS: ct a ch on m vo stack. SP SP 2, [SP] IP: ct a ch tr v sau khi phc v ngt

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IP [S_hiu_ngt*4], CS [S_hiu_ngt*4 + 2]: ly lnh ti a ch phc v ngt tng ng Sau khi kt thc chng trnh con phc v ngt (khi gp lnh IRET): + IP [SP], SP SP + 2 + CS [SP], SP SP + 2: ly li a ch trc khi gi chng trnh phc v ngt + FR [SP], SP SP + 2: ly li gi tr thanh ghi c

2.2.3. X l u tin ngt Nh ta bit trn, khi P ang thc hin lnh, nu c ngt xy ra th P s tm ngng chng trnh v thc thi chng trnh con phc v ngt. Trong thc t s c trng hp c nhiu yu cu ngt khc nhau cng mt lc, khi P s phc v cho ngt theo th t u tin vi nguyn tc l ngt no c mc u tin cao nht th s phc v cho ngt trc. Cc mc u tin ca cc ngt (t mc thp nht n mc cao nht): Ngt thc hin chy tng lnh (INT 1) Ngt che c INTR Ngt khng che c NMI Ngt ni b (INT 0: xy ra do php chia s 0, ngt mm)

2.3. Nhp / xut d liu bng DMA (Direct Memory Access) Trong cc phng thc trao i d liu nh hai phn trn trnh by th vic trao i d liu gia thit b ngoi vi v h thng thng theo trnh t sau: t ngoi vi n vi x l ri i vo b nh hay t b nh n vi x l ri ghi ra ngoi vi. Trong thc t s c trng hp ta cn thc hin trao i d liu ngay gia ngoi vi v b nh. Khi ngi ta a ra c ch truy xut b nh trc tip (DMA). thc hin c vn ny, cc h vi x l thng thng dng thm cc mch chuyn dng iu khin qu trnh truy xut b nh trc tip (DMAC Direct Memory Access Controller). C tt c 3 c ch hot ng: Tn dng thi gian CPU khng dng bus: Ta phi dng thm mch pht hin cc chu k x l ni ca CPU v tn dng cc chu k ny thc hin trao i d liu. Treo CPU trao i tng byte: CPU khng b treo trong khong thi gian di m ch b treo trong thi gian ngn trao i 1 byte d liu gia b nh v ngoi vi. Do , cng vic ca CPU khng b gin on m ch b chm i. Treo CPU mt khong thi gian trao i mt khi d liu: Trong c ch ny, CPU b treo trong sut qu trnh trao i d liu. CPU ghi t lnh v t ch lm vic vo DMAC. Khi thit b ngoi vi c yu cu trao i d liu, n gi tn hiu DRQ = 1 (DMA Request) n DMAC.
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DMAC gi tn hiu HRQ (Hold Request) n chn HOLD ca CPU yu cu treo CPU. Tn hiu ny s gi mc cao cho n ht qu trnh trao i d liu. Sau khi nhn yu cu treo, CPU s thc hin ht chu k bus ca m?nh ri treo cc bus v gi tn hiu HLDA (Hold Acknowledge) bo cho DMAC bit c th s dng cc bus. DMAC chuyn d liu t b nh n ngoi vi bng cch: a a ch byte u tin ra bus a ch v a tn hiu MEMR c 1 byte t b nh, k tip DMAC a tn hiu IOW ghi d liu ra ngoi vi. Sau , DMAC gim s byte cn truyn, cp nht a ch b nh v lp li qu trnh cho n khi ht byte cn truyn.
P Address bus Data bus

HOLD HLDA

DMAC HRQ DRQ HACK DACK

I/O DRQ DACK

Memory

Control bus

Hnh 1.4 Giao tip DMAC vi h vi x l Hai tn hiu dng yu cu treo v chp nhn yu cu treo CPU dng cho c ch DMA l HOLD v HLDA c th m t nh sau:
T4 hay T1

CLK HOLD HLDA

Hnh 1.5 Tn hiu HOLD v HLDA

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3. Bus
CPU Registers Bus h thng (system bus)

ALU

Memory board

I/O board

Bus ni (on-chip bus) Bus cc b (local bus) ng x l

Hnh 1.6 - Cc bus trong mt h thng my tnh Bus l ng truyn tn hiu in ni cc thit b khc nhau trong mt h thng my tnh. Bus thng c t 50 n 100 dy dn c gn trn mainboard, trn cc dy ny c cc u ni a ra, cc u ny c sp xp v cch nhau nhng khong quy nh c th cm vo nhng I/O board hay board b nh (bus h thng system bus). Cng c nhng bus dng cho mc ch chuyn bit, th d ni 1 vi x l vi 1 hay nhiu vi x l khc hoc ni vi b nh cc b (local bus). Trong vi x l cng c mt s bus ni cc thnh phn bn trong ca b vi x l vi nhau. Ngi thit k chip vi x l c th tu la chn loi bus bn trong n, cn vi cc bus lin h bn ngoi cn phi xc nh r cc quy tc lm vic cng nh cc c im k thut v in v c kh ca bus ngi thit k mainboard c th ghp ni chip vi x l vi cc thit b khc. Ni cch khc, cc bus ny phi tun theo 1 chun no . Tp cc quy tc ca chun cn c gi l giao thc bus (bus protocol) Thng c nhiu thit b ni vi bus, mt s thit b l tch cc (active) c th i hi truyn thng trn bus, trong khi c cc thit b th ng ch yu cu t cc thit b khc. Cc thit b tch cc c gi l ch (master) cn thit b th ng l t (slave). V d: Khi CPU ra lnh cho b iu khin a c/ghi mt khi d liu th CPU l master cn b iu khin a l slave. Tuy nhin, b iu khin a ra lnh cho b nh nhn d liu th n li gi vai tr master.

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3.1. Bus Driver v Bus Receiver Tn hiu in trong my tnh pht ra thng khng iu khin bus, nht l khi bus kh di v c nhiu thit b ni vi n. Chnh v th m hu ht cc bus master c ni vi bus thng qua 1 chip gi l bus driver, v c bn n l mt b khuch i tn hiu s. Tng t nh vy, hu ht cc slave c ni vi bus thng qua bus receiver. i vi cc thit b khi th ng vai tr master, khi th ng vai tr slave, ngi ta s dng 1 chip kt hp gi l transceiver. Cc chip ny ng vai tr ghp ni v l cc thit b 3 trng thi, cho php n c th trng thi th 3 h mch (th ni). Ging nh vi x l, bus c cc ng a ch, ng s liu v ng iu khin. Tuy nhin, khng nht thit c nh x 1 1 gia cc tn hiu cc chn ra ca vi x l v cc ng dy ca bus. Th d: mt s chp vi x l c 3 chn ra, truyn ra cc tn hiu bo chp vi x l ang thc hin cc thao tc MEMR , MEMW , IOR , IOW hay thao tc khc. Mt bus in hnh thng c 4 ng trn. Cc vn quan trng nht lin quan n thit k bus l: xung clock bus (s phn chia thi gian, hay cn gi l bus blocking), c ch phn x bus (bus arbitration), x l ngt v x l li. Cc bus c th c chia theo giao thc truyn thng thnh hai loi ring bit l bus ng b v bus khng ng b ph thuc vo vic s dng clock bus. 3.2. Bus ng b (Synchronous bus) Mi chu k bus bt u bng vic xut a ch b nh hoc I/O port (chu k xung nhp T1). Bus iu khin c 4 tn hiu tc ng mc thp l MEMR , MEMW , IOR v IOW . Cc chui s kin xy ra trong mt chu k bus c b nh: T1: P xut a ch b nh 20 bit. Cc ng d liu khng hot ng v cc ng iu khin b cm T2: ng iu khin MEMR xung mc thp. n v b nh ghi nhn chu k bus ny l qu trnh c b nh v t byte hay word c a ch ln data bus. T3: P t cu hnh cc ng data bus l nhp. Trng thi ny ch yu b nh c thi gian tm kim byte hay word d liu T4: P i d liu trn data bus. Do , n thc hin cht data bus v gii phng cc ng iu khin c b nh. Qu trnh ny s kt thc chu k bus.

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Chng 1

T1 Clk Address bus

T2

T3

T4

a ch c b nh hay I/O D liu vo a ch Ghi b nh hay I/O D liu ra

IOR hay MEMR

Data bus Address bus

IOW hay MEMW

Data bus

Hnh 1.7 nh th chu k bus ng b Trong mt chu k bus, P c th thc hin c I/O, ghi I/O, c b nh hay ghi b nh. Cc ng address bus v control bus dng xc nh a ch b nh hay I/O v hng truyn d liu trn data bus. Ch rng P iu khin tt c cc qu trnh trn nn b nh bt buc phi cung cp c d liu vo lc MEMR ln mc cao trong trng thi T4. Nu khng, P s c d liu ngu nhin khng mong mun trn data bus. gii quyt vn ny, ta c th dng thm cc trng thi ch (wait state). Truyn theo khi: Ngoi cc chu k c/ghi, mt s bus truyn d liu ng b cn h tr truyn d liu theo khi. Khi bt u thao tc c khi, bus master bo cho slave bit s byte cn c truyn i, th d truyn con s ny i trong chu k T1, sau ng l truyn i 1 byte, slave a ra trong mi chu k 1 byte cho ti khi s byte c thng bo. Nh vy, khi c d liu theo khi, n byte d liu cn n+2 chu k clock ch khng phi 3n chu k. Mt cch khc cho truyn d liu nhanh hn l gim chu k. Tuy nhin, gim chu k bus dn n kh khn v mt k thut, cc tn hiu truyn trn cc ng khc nhau khng phi lun c cng tc , dn n hiu ng bus skew. iu quan trng l thi
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gian chu k phi di hn so vi skew trnh vic nhng khong thi gian c s ho li tr thnh cc i lng bin thin lin tc. 3.3. Bus bt ng b( Asynchronous bus) Bus bt ng b khng s dng xung clock ng b, chu k ca n c th ko di tu v c th khc nhau i vi cc cp thit b khc nhau. Lm vic vi cc bus ng b d dng hn do n c nh thi mt cch gin on , tuy vy chnh c im ny cng dn n nhc im. Mi cng vic c tin hnh trong khong thi gian l bi s ca xung clock, nu 1 thao tc no ca vi x l hay b nh hon thnh trong 3.1 chu k th n cng s phi ko di trong 4 chu k. Khi chn chu k bus v xy dng b nh, I/O card cho bus ny th kh c th tn dng nhng tin b ca cng ngh. Chng hn sau khi xy bus vi s nh thi nh trn, cng ngh mi a ra cc vi x l v b nh c thi gian chu k l 100ns ch khng cn l 750ns nh c, th chng vn chy vi tc thp nh cc vi x l, b nh loi c, bi v giao thc bus i hi b nh phi a c d liu ra v n nh trc thi im cnh m ca T3. Nu c nhiu thit b khc nhau cng ni vi 1 bus, trong c th c mt s thit b hot ng nhanh hn hn cc thit b khc th cn phi t bus hot ng ph hp vi thit b c tc thp nht. Bus bt ng b ra i nhm khc phc nhng nhc im ca bus ng b. Trc ht master pht ra a ch nh m n mun truy cp, sau pht tn hiu MEMR tch cc xc nh cn truy xut b nh v yu cu qu trnh truy xut l READ xc nh chiu truyn d liu. Tn hiu MEMR c a ra sau tn hiu a ch mt khong thi gian ph thuc tc hot ng ca master. Sau khi 2 tn hiu ny n nh, master s pht ra tn hiu MSYN (master synchrization) mc tch cc bo cho slave bit rng cc tn hiu cn thit sn sng trn bus, slave c th nhn ly. Khi slave nhn c tn hiu ny, n s thc hin cng vic vi tc nhanh nht c th c, a d liu ca nh c yu cu ln bus d liu. Khi hon thnh slave s pht tn hiu SSYN (slave synchronization) tch cc.
Address

MEMR (Control)
MSYN

Data
SSYN

Hnh 1.8 nh th chu k bus bt ng b

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Ti liu Lp trnh h thng

Chng 1

Master nhn c tn hiu SSYN tch cc th xc nh c d liu ca slave sn sng nn thc hin vic cht d liu, sau o cc ng a ch cng nh cc tn hiu MEMR v MSYN . Khi slave nhn c tn hiu MSYN khng tch cc, n xc nh kt thc chu k v o tn hiu SSYN lm bus tr li trng thi ban u, mi tn hiu u khng tch cc, ch bus master mi. Trn gin thi gian ca bus bt ng b, ta s dng mi tn th hin nguyn nhn v kt qu. MSYN tch cc dn n vic truyn d liu ra bus d liu v ng thi cng dn n vic slave pht ra tn hiu SSYN tch cc, n lt mnh tn hiu SSYN li gy ra s o mc ca cc ng a ch, MEMR v MSYN . Cui cng s o mc ca MSYN li gy ra s o mc tn hiu SSYN v kt thc chu k. Tp cc tn hiu phi hp vi nhau nh vy c gi l bt tay ton phn (full handshake), ch yu gm 4 tn hiu sau: - MSYN tch cc. - SSYN tch cc p li tn hiu MSYN . - MSYN c o p li tn hiu SSYN (tch cc). - SSYN c o p li tn hiu MSYN khng tch cc. Ta c th nhn thy bt tay ton phn l c lp thi gian, mi s kin c gy ra bi 1 s kin trc ch khng phi bi xung clock. Nu 1 cp master-slave no hot ng chm th cp master-slave k tip khng h b nh hng. Tuy u im ca bus bt ng b rt r rng, nhng trong thc t phn ln cc bus ang s dng l loi ng b. Nguyn nhn l cc h thng s dng bus ng b d thit k hn. Vi x l ch cn chuyn cc mc tn hiu cn thit sang trng thi tch cc l b nh p ng ngay, khng cn tn hiu phn hi. Ch cn cc chn ph hp th mi hot ng u tri chy, khng cn phi bt tay. 3.4. X l ngt trn, ta ch kho st cc chu k bus thng thng, trong master nhn hay gi thng tin t / n slave. Mt ng dng quan trng na ca bus l dng x l ngt. Khi CPU ra lnh cho thit b I/O lm mt vic g , n thng ch i tn hiu ngt do thit b I/O pht ra khi hon thnh cng vic c CPU yu cu. Khi nhn c tn hiu ngt, CPU s p ng ngay, c th nhn d liu do thit b I/O truyn v, hay gi tip d liu ra thit b I/O, hay CPU s s dng bus cho mt thao tc khc. Nh vy chnh ngt pht ra tn hiu yu cu s dng bus. V c th nhiu thit b ngoi vi cng pht ra ngt, cho nn cn c 1 c ch phn x ging nh i vi cc bus thng thng. Gii php thng dng l gn cc mc u tin cho cc thit b v s dng 1 arbiter tp trung trao quyn u tin cho cc thit b quan trng thng xuyn c s dng. Hin trn th trng c nhng chip iu khin ngt c tiu chun ha v c s dng rng ri l chip 8259A. C th ni 8 chip iu khin I/O ti cc u IRx (Interrupt request) ca 8259A. Khi c 1 thit b no mun ngt, n t mc tch cc ln chn Irx, 8259A nhn c tn hiu tch cc 1 hay mt s
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Ti liu Lp trnh h thng

Chng 1

u vo Irx th s t mc tch cc ln u dy INT. Tn hiu INT s truyn trc tip n chn Interrupt ca CPU. Khi CPU c th x l c ngt, n gi li 1 tn hiu chp nhn ngt cho 8259A. Lc ny, CPU ch 8259A ch ra I/O no yu cu ngt, bng cch gi s hiu ca I/O ln bus d liu (D0-D7) i n CPU. Sau , phn cng CPU s s dng con s tnh ch s trong 1 bng con tr -bng vector ngt (interrupt vector) tm a ch chng trnh con, cho chy chng trnh ny phc v ngt. Cc chng trnh con ny gi l chng trnh con x l ngt.

4. Cc chip h tr cho b x l trung tm

4.1. Mch to xung clock 8284
1 2 3 4 5 6 7 8 9 VCC CSY NC X1 PCLK X2 AEN1 RDY 1 ASY NC EFI READY F/C RD2 OSC AEN2 CLK RES GND RESET 18 17 16 15 14 13 12 11 10

8284 Hnh 1.9 Mch to xung clock 8284

PCLK (Peripheral Clock): xung clock f = fX/6 (fX l tn s thch anh) vi chu k bn phn 50%. CSYNC (Clock Synchronisation): ng vo xung ng b chung khi h thng c cc 8284 dng dao ng ngoi ti chn EFI. Khi dng mch dao ng trong th phi ni GND.
AEN 1 , AEN 2 (Address Enable): cho php chn cc chn tng ng RDY1, RDY2 bo hiu trng thi sn sng ca b nh hay thit b ngoi vi.

RDY1, RDY2 (Bus ready): kt hp vi AEN1 , AEN2 to cc chu k i CPU READY: ni n chn READY ca P. CLK (Clock): xung clock f = fX/3, ni vi chn CLK ca CPU. RESET: ni vi chn RESET ca CPU, l tn hiu khi ng li ton h thng.
RES (Reset Input): chn khi ng cho 8284, c ni vi mch RC t khi ng khi bt ngun.

OSC: ng ra xung clock c tn s fX. F/ C (Frequency / Crystal): chn ngun tn hiu chun cho 8284, nu mc cao th chn tn s xung clock bn ngoi, ngc li th dng xung clock t thch anh. EFI (External Frequency Input): xung clock t b dao ng ngoi.

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Ti liu Lp trnh h thng

Chng 1

ASYNC : chn ch lm vic cho tn hiu RDY. Nu ASYNC = 1, tn hiu RDY c nh hng n tn hiu READY cho n khi c xung m ca xung clock. Ngc li th RDY ch nh hng khi xut hin xung m.

X1,X2: ng vo ca thch anh, dng to xung chun cho h thng.

18 17 16 15 14 13 12 11 10 Vcc VCC CSY NC X1 PCLK X2 AEN1 ASY NC RDY 1 EFI READY F/C RD2 OSC AEN2 RES CLK RESET GND 1 2 3 4 5 6 7 8 9

8284

Hnh 1.10 Mch khi ng cho 8284 4.2. Mch nh thi PIT 8253 / 8254 (Programmable Interval Timer)
19 20 11 14 16 9 15 18 22 23 21 A0 A1 G0 G1 G2 CLK0 CLK1 CLK2 RD WR CS 8253 OUT0 OUT1 OUT2 D0 D1 D2 D3 D4 D5 D6 D7 10 13 17 8 7 6 5 4 3 2 1

Hnh 1.11 S chn ca PIT 8253

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Ti liu Lp trnh h thng

Chng 1

D7 D0

m d liu

B m 0

OUT0 CLK0 GATE0

BUS NI

RD WR
A1 A0

iu khin c/ghi

B m 1

OUT1 CLK1 GATE1

CS
Thanh ghi t iu khin B m 2 OUT2 CLK2 GATE2

Hnh 1.12 S khi ca PIT 8253 D7 D0: bus d liu CLK0 CLK2: ng vo xung clock cho cc b m OUT0 OUT2: ng ra b m
RD , WR : cho php CPU c / ghi d liu t / n cc thanh ghi ca 8253

A1, A0: gii m chn b m hay thanh ghi iu khin, thng c ni vi bus a ch ca CPU A1 A0 Chn 0 0 1 1 0 1 0 1 B m 0 B m 1 B m 2 Thanh ghi t iu khin

G0 G2 (Gate): cho php hay cm cc b m hot ng ( =1: cho php, =0: cm). PIT 8253 c tt c 5 ch m ty thuc vo gi tr trong thanh ghi iu khin.
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Ti liu Lp trnh h thng

Chng 1

SC1 SC0 RW1 RW0 M2

M1

M0 BCD

Chn b m 00: b m 0 01: b m 1 10: b m 2 11: c CWR trong 8254 Quy nh phng thc c/ghi 00: cht b m 01: c/ghi byte thp 10: c/ghi byte cao 11: c/ghi byte thp trc, byte cao sau

nh dng m 0: m nh phn 1: m BCD (0 999)

Ch m 000: ch 0 001: ch 1 010: ch 2 011: ch 3 100: ch 4 101: ch 5

Hnh 1.13 Dng t iu khin ca 8253

PIT 8253 c 3 b m li 16 bit c th lp trnh v c lp vi nhau. Mi b m c tn hiu xung clock ring (8254 tng t nh 8253 nhng c thm lnh c thanh ghi t iu khin CWR). Cc ch m: Ch 0 (Interrupt on Terminal Count): tn hiu ng ra mc thp cho ti khi b m trn th s chuyn ln mc cao. Ch 1 (Programmable Monoflop): tn hiu ng ra chuyn xung mc thp ti cnh m ca xung clock u tin v s chuyn ln mc cao khi b m kt thc. Ch 2 (Rate Generator): tn hiu ng ra xung mc thp trong chu k u tin v sau chuyn ln mc cao trong cc chu k cn li. Ch 3 (Square-Wave Generator): tng t nh ch 2 nhng xung ng ra l sng vung khi gi tr m chn v s thm mt chu k mc cao khi gi tr m l. Ch 4 (Software-triggered Pulse): ging nh ch 2 nhng xung Gate khng khi ng qu trnh m m s m ngay khi s m ban u c np. Ng ra mc cao m v xung mc thp trong chu k xung m. Sau , ng ra s tr li mc cao. Ch 5 (Hardware-triggered Pulse): ging nh ch 2 nhng xung Gate khng khi ng qu trnh m m c khi ng bng cnh dng ca xung clock ng vo. Ng ra mc cao v xung mc thp sau mt chu k clock khi qu trnh m kt thc.

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Ti liu Lp trnh h thng

Chng 1

Ba chc nng ca 8253 trong PC: Cp nht ng h h thng: b m 0 ca PIT pht tun hon mt ngt cng qua IRQ0 ca 8259 CPU c th thay i ng h h thng. B m hot ng trong ch 2. Ng vo c cp xung clock tn s 1.19318 MHz. G0 = 1 b m lun c php m. Gi tr ban u c np l 0 cho php PIT pht ra xung chnh xc vi tn s:1.19318/65536 = 18.206Hz. Cnh dng ca mi xung ny s to ra mt ngt cng trong 8259. Yu cu ny s dn ti ngt 08h cp nht ng h h thng 18.206 ln trong 1 giy. Lm ti b nh: PIT ni vi chip DMAC dng lm ti b nh DRAM. B m 1 s nh k kch hot knh 0 ca DMAC-8237A tin hnh 1 chu trnh c gi lm ti b nh. B nh 1 hot ng trong ch 3 pht sng vung vi gi tr np ban u l 18. Do sng vung c pht ra c tn s 1,19318 MHz/18 = 66288 Hz (chu k bng 0.015s). Nh vy c sau 15 ms cnh dng ca sng vung ny s to 1 chu k c gi lm ti b nh. Pht sng m vi tn s bin i ra loa ca PC: B m 2 ca PIT c dng pht sng m ra loa ca PC. 4.3. Mch iu khin bus 8288 Mch iu khin bus 8288 ly mt s tn hiu iu khin ca CPU v cung cp cc tn hiu iu khin cn thit cho h vi x l.
1 2 3 4 5 6 7 8 9 10 IOB VCC CLK S0 S1 S2 DT/R MCE/PDEN ALE DEN AEN CEN MRDC INTA AMWC IORC MWTC AIOWC GND IOWC 20 19 18 17 16 15 14 13 12 11

8288 Hnh 1.14 Mch iu khin bus 8288

IOB (Input / Output Bus Mode): iu khin 8288 lm vic cc ch bus khc nhau. CLK (Clock): ng vo ly t xung clock h thng (t 8284) v dng ng b ton b cc xung iu khin i ra t mch 8288. DT/ R (Data Transmit/Receive): CPU truyn (1) hay nhn (0) d liu. ALE (Address Latch Enable): tn hiu cho php cht a ch, tn hiu ny thng c ni vi chn G ca 74573 iu khin cht a ch.
AEN (Address Enable): ch thi gian tr khong 150 ns s to cc tn hiu iu

khin u ra ca 8288 m bo rng a ch s dng hp l.

S 2 , S1 , S0 : cc tn hiu trng thi ly trc tip t CPU. Tu theo cc gi tr nhn

c m 8288 s a cc tn hiu theo bng:

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Ti liu Lp trnh h thng

Chng 1

S2

S1

S0

To tn hiu
INTA

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

IORC IOWC , AIOWC

Khng
MRDC MRDC MWTC , AMWC

Khng

MRDC (Memory Read Command): iu khin c b nh

MWTC (Memory Write Command): iu khin ghi b nh AMWC (Advanced MWTC),: ging nh MWTC nhng hot ng sm hn mt

cht dng cho cc b nh chm p ng kp tc CPU.

IOWC (I/O Write Command): iu khin ghi ngoi vi AIOWC (Advanced IOWC),: ging nh IOWC nhng hot ng sm hn mt cht dng cho cc ngoi vi chm p ng kp tc CPU. IORC (I/O Read Command): iu khin c ngoi vi

INTA (Interrupt Acknowledge): ng ra thng bo CPU chp nhn yu cu ngt

ca thit b ngoi vi CEN (Command Enable): cho php a ra tn hiu DEN v cc tn hiu iu khin khc ca 8288. DEN (Data Enable): iu khin bus d liu thnh bus cc b hay bus h thng. MCE / PDEN (Master Cascade Enable / Peripheral Data Enable): nh ch lm vic cho mch iu khin ngt PIC 8259 n lm vic ch master.

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Ti liu Lp trnh h thng

Chng 1

4.4. Chip iu khin ngt u tin PIC 8259A (Priority Interrupt Controller)
18 19 20 21 22 23 24 25 27 26 3 2 1 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 A0 INTA RD WR CS D0 D1 D2 D3 D4 D5 D6 D7 CAS0 CAS1 CAS2 SP/EN INT 8259A 11 10 9 8 7 6 5 4 12 13 15 16 17

Hnh 1.15 S chn ca 8259A Trong trng hp nhiu yu cu ngt cn phi phc v, ta thng dng vi mch 8259A gii quyt vn u tin. 8259A c th gii quyt c 8 yu cu ngt vi 8 mc u tin khc nhau. Cc khi chc nng: IRR (thanh ghi yu cu ngt): lu tr cc yu cu ngt ti ng vo ISR (thanh ghi phc v ngt): lu tr cc yu cu ngt ang phc v IMR (thanh ghi mt n ngt): lu tr mt n ca cc yu cu ngt ti ng vo Control logic (logic iu khin): gi yu cu ngt ti chn INTR ca CPU khi c tn hiu ngt ti ng vo ca 8259A v nhn tr li chp nhn yu cu ngt hay khng INTA t CPU a kiu ngt vo CPU. Data bus buffer (m bus d liu): giao tip gia 8259A vi bus d liu ca CPU. Cascade buffer / comparator (m ni tng v so snh): lu tr v so snh s hiu ca cc kiu ngt trong trng hp dng nhiu mch 8259A.

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Ti liu Lp trnh h thng

Chng 1

INTA

INT

Data bus buffer

Control logic

RD WR

A0

Read / Write Logic

INTERNAL BUS

ISR (Interrupt Service Register)

PR (Priority Resolver)

IRR (Interrupt Request Register)

IR0 IR1 IR7

CS

CAS0 CAS1 CAS2

SP / EN

Cascade buffer / comparator

IMR (Interrupt Mask Register)

Hnh 1.16 S khi ca PIC 8259A

Cc tn hiu iu khin: CAS0 2 (In, Out): cc ng vo chn mch 8259A t (slave) t mch 8259A ch (master) trong trng hp dng nhiu mch 8259A tng yu cu ngt.
SP / EN (In, Out) (Slave Program / Enable Buffer): nu 8259A hot ng ch khng dng m d liu th tn hiu ny dng xc nh mch 8259A l mch ch ( SP = 1) hay t ( SP = 0). Nu 8259A hot ng ch c m d liu th tn hiu ny dng cho php giao tip gia 8259A v CPU, khi mch 8259A l master hay slave phi da vo t lnh khi ng ICW4.

INT (Out): tn hiu yu cu ngt a n CPU (chn INTR).

INTA (In): nhn tr li chp nhn ngt hay khng t CPU (chn INTA )

A0: cho php chn cc t iu khin ca 8259A. 8259A cho php x l 8 ngt vi 8 mc u tin khc nhau. Trong trng hp h thng c s lng ngt ln hn th c th mc nhiu 8259A lin tng.
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Ti liu Lp trnh h thng

Chng 1

18 19 20 21 22 23 24 25

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

D0 D1 D2 D3 D4 D5 D6 D7 A0 CS RD WR SP/EN INT INTA

11 10 9 8 7 6 5 4 27 1 3 2 16 17 26

18 19 20 21 22 23 24 25

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

D0 D1 D2 D3 D4 D5 D6 D7 A0 CS RD WR SP/EN INT INTA

11 10 9 8 7 6 5 4 27 1 3 2 16 17 26

Vcc

12 13 15

CAS0 CAS1 CAS2

12 13 15

CAS0 CAS1 CAS2

8259A - Slave

8259A - Master

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND VCC AD14 AD15 AD13 A16/S3 AD12 A17/S4 AD11 A18/S5 AD10 A19/S6 AD9 BHE/S7 AD8 MN/MX AD7 RD AD6 HOLD (RQ/GT0) AD5 HLDA (RQ/GT1) AD4 WR (LOCK) AD3 IO/M (S2) AD2 DT/R (S1) AD1 DEN (S0) AD0 ALE (QS0) NMI INTA (QS1) INTR TEST CLK READY GND RESET

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

8086

Hnh 1.17 8259A mc lin tng 4.5. Chip iu khin truy nhp b nh trc tip DMAC 8237 (Direct Memory Access Controller) DMAC 8237 c th thc hin truyn d liu theo 3 kiu: kiu c (t b nh ra thit b ngoi vi), kiu ghi (t thit b ngoi vi n b nh) v kiu kim tra.

32 33 34 35 37 38 39 40 12 19 18 17 16 36 7 1 2 6 13 5 11

A0 A1 A2 A3 A4 A5 A6 A7 CLK DRQ0 DRQ1 DRQ2 DRQ3 EOP HLDA IOR IOW READY RESET VX CS 8237

DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DAK0 DAK1 DAK2 DAK3 MEMR MEMW AEN ASTB HRQ

30 29 28 27 26 23 22 21 25 24 14 15 3 4 9 8 10

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Ti liu Lp trnh h thng

Chng 1

EOP
RESET

Decrementor Temp word count register

Bus 16 bit

Incrementor Temp address register I/O buffer

A0 A3

CS
READY CLK AEN ADSTB Timing and control

Output buffer

A4 A7

Read buffer Base address

Base word count

R/W buffer Current address

Current word count

MEMW

Command control

MEMR
A8 A15

IOW

Write buffer

Read buffer

D0 D1

IOR

DRQ0 DRQ3 DACK0 DACK3 HLDA HRQ

Command Priority encoder and rotating prority logic Mask Request

RD

I/O buffer

DB0 DB7

R/W Mode

Status

Temp

Hnh 1.18 S chn v s khi ca DMAC 8237A Khi Timing and Control (nh thi v iu khin): To cc tn hiu nh thi v iu khin cho bus ngoi (external bus). Cc tn hiu ny c ng b vi xung clock a vo DMAC (tn s xung clock ti a l 5 MHz). Khi Priority encoder and rotating priority logic (m ha u tin v quay mc u tin): DMAC 8237A c 2 m hnh u tin: m hnh u tin c nh (fixed priority) v m hnh u tin quay (rotating priority). Trong m hnh u tin c nh, knh 0 s c mc u tin cao nht cn knh 3 c mc u tin thp nht. Cn i vi m hnh u tin quay th mc u tin khi khi ng ging nh m hnh u tin c nh nhng khi yu cu DMA ti mt knh no c phc v th s c t xung mc u tin thp nht. Khi Command Control (iu khin lnh): Gii m cc thanh ghi lnh (xc nh thanh ghi s c truy xut v loi hot ng cn thc hin).
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Ti liu Lp trnh h thng

Chng 1

Cc thanh ghi: DMAC 8237A c tt c 12 loi thanh ghi ni khc nhau: Tn

Thanh ghi a ch c s (Base Address Register) Thanh ghi m t c s (Base Word Count Register) Thanh ghi a ch hin hnh (Current Address Register) Thanh ghi m t hin hnh (Current Word Count Register) Thanh ghi a ch tm (Temporary Address Register) Thanh ghi m t tm (Temporary Word Count Register) Thanh ghi trng thi (Status Register) Thanh ghi lnh (Command Register) Thanh ghi tm (Temporary Register) Thanh ghi ch (Mode Register) Thanh ghi mt n (Mask Register) Thanh ghi yu cu (Request Register)

Kch thc (bit)

16 16 16 16 16 16 8 8 8 6 4 4

S lng
4 4 4 4 1 1 1 1 1 4 1 1

Chc nng cc chn ca 8237A:

CLK (Input): tn hiu xung clock ca mch. Tn hiu ny thng c ly t 8284

sau khi qua cng o.

CS (Input): thng c ni vi b gii m a ch.

RESET (Input): khi ng 8237A, c ni vi ng RESET ca 8284. Khi Reset th thanh ghi mt n c lp cn cc phn sau b xa: + Thanh ghi lnh + Thanh ghi trng thi + Thanh ghi yu cu + Thanh ghi tm + Flip-flop u/cui (First/Last flip-flop) READY (Input): ni vi READY ca CPU to chu k i khi truy xut cc thit b ngoi vi hay b nh chm. HLDA (Hold Acknowledge)(Input): tn hiu chp nhn yu cu treo t CPU vi. DRQ0 DRQ3 (DMA Request)(Input): cc tn hiu yu cu treo t thit b ngoi DB0 DB7 (Input, Output): ni n bus a ch v d liu ca CPU
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Ti liu Lp trnh h thng

Chng 1

IOR , IOW (Input, Output): s dng trong cc chu k c v ghi EOP (End Of Process)(Input,Output): bt buc DMAC kt thc qu trnh DMA

nu l ng vo hay dng bo cho mt knh bit l d liu chuyn xong (Terminal count TC), thng dng nh yu cu ngt CPU kt thc qu trnh DMA. A0 A3 (Input, Output): chn cc thanh ghi trong 8237A khi lp trnh hay dng cha 4 bit a ch thp. A4 A7 (Output): cha 4 bit a ch HRQ (Hold Request)(Output): tn hiu yu cu treo n CPU DACK0 DACK3 (DMA Acknowledge)(Output): tn hiu tr li yu cu DMA cho cc knh. AEN (Output): cho php ly a ch vng nh cn trao i ADSTB (Address Strobe)(Output): cht cc bit a ch cao A8 A15 cha trong cc chn DB0 DB7
MEMR , MEMW (Output): dng c / ghi b nh.

Cc thanh ghi ni: Cc thanh ghi ni trong DMAC 8237A c truy xut nh cc bit a ch thp A0 A3. Bit a ch A3 A2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a ch X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 XA XB XC XD XE XF Chn chc nng Thanh ghi a ch b nh knh 0 Thanh ghi m t knh 0 Thanh ghi a ch b nh knh 1 Thanh ghi m t knh 1 Thanh ghi a ch b nh knh 2 Thanh ghi m t knh 2 Thanh ghi a ch b nh knh 3 Thanh ghi m t knh 3 Thanh ghi trng thi / lnh Thanh ghi yu cu Thanh ghi mt n cho mt knh Thanh ghi ch Xa flip-flop u/cui Xa ton b cc thanh ghi / c thanh ghi tm Xa thanh ghi mt n Thanh ghi mt n R/W? R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W W/R W W

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Ti liu Lp trnh h thng

Chng 1

a ch cc thanh ghi ni dng ghi / c a ch: Knh

0

IOR IOW A3 A2 A1 A0 Thanh ghi

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh

R/W?
W R W R W R W R W R W R W R W R

a ch cc thanh ghi trng thi v iu khin:

IOR `
1 0 1 1 1 1 1 0 1 0 1 0

IOW
0 1 0 0 0 0 0 1 0 1 0 1

A3 A2 A1 A0 Thanh ghi
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 1 1 0 0 1 0 1 0 1 1 0 0 1 1 Ghi thanh ghi lnh c thanh ghi trng thi Ghi thanh ghi yu cu Ghi thanh ghi mt n Ghi thanh ghi ch Xa flip-flop u/cui Xa tt c cc thanh ghi ni a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh

Mch 8273A-5 cha 4 knh trao i d liu DMA vi mc u tin lp trnh c. 8237A-5 c tc truyn 1 MBps cho mi knh v 1 knh c th truyn 1 mng c di 64 KB. c th s dng mch DMAC 8237A, ta cn to tn hiu iu khin nh sau:

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Ti liu Lp trnh h thng

Chng 1

Vcc

RD WR
AEN IO/ M

2 3 5 6 11 10 14 13 15 1

1A 1B 2A 2B 3A 3B 4A 4B G A/B

1Y 2Y 3Y 4Y

4 7 9 12

IOR IOW MEMR

MEMW

74LS257

Hnh 1.19 Tn hiu iu khin cho h thng lm vic vi DMAC 8237A Tn hiu AEN t 8237A dng cm cc tn hiu iu khin t CPU khi DMAC nm quyn iu khin bus. 4.6. Chip iu khin mn hnh CRTC 6845 (Cathode Ray Tube Controller)
RST (Reset): khi ng li 6845.

MA0 MA13 (Memory Address): 14 a ch nh cho RAM mn hnh. DE (Display Enable): cho php (=1) hay khng (=0) cc tn hiu iu khin v a ch vng hin ln mn hnh. LPSTD (Light Pen Strobe): lu tr a ch hin hnh ca RAM mn hnh trong thanh ghi bt sng. CPU c thanh ghi v xc nh v tr bt sng trn mn hnh. CURSOR: v tr con tr qut (=1) hay cha (=0).
33 32 31 30 29 28 27 26 21 23 3 2 24 22 25 D0 D1 D2 D3 D4 D5 D6 D7 CLK E LPSTD RST RS R/W CS MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 RA0 RA1 RA2 RA3 RA4 CURSOR DE HS VS 6845 4 5 6 7 8 9 10 11 12 13 14 15 16 17 38 37 36 35 34 19 18 39 40

Hnh 1.20 S chn ca 6845

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VS (Vertical Synchronization): ng ra tn hiu ng b qut dc HS (Horizontal Synchronization): ng ra tn hiu ng b qut ngang RA0 RA4 (Row Address): phn nh hng qut ca k t trong ch vn bn (32 hng qut). Trong ch ha, chng kt hp vi MA0 MA13 to cc a ch cho cc bank RAM mn hnh. D0 D7: ng d liu.
CS : chn chip.

RS (Regigter Select): chn thanh ghi a ch (=0) hay thanh ghi d liu (=1). E: xung m kch hot bus d liu v dng nh xung clock cho 6845 c / ghi d liu vo cc thanh ghi bn trong. R/ W : c / ghi d liu vo cc thanh ghi. CLK: dng ng b vi tn hiu ca mn hnh v thng bng tc hin k t trn mn hnh. 4.7. Chip ng x l ton hc 8087/80287/80387 (Mathematical co-processor) Cc b ng x l ton 80x87 h tr CPU trong vic tnh ton cc biu thc dng du chm ng nh cng, tr, nhn, chia cc s du chm ng, cn thc, logarit, Chng cho php x l cc php ton ny nhanh hn nhiu so vi CPU. Thi gian x l gia 8087 v 8086 nh sau (dng xung clock 8 MHz): Php ton Cng / tr Nhn Chia Tang Ly tha Lu tr 8087: 8087 gm mt n v iu khin (CU Control Unit) dng iu khin bus v mt n v s hc (NU Numerical Unit) thc hin cc php ton du chm ng trong cc mch tnh ly tha (exponent module) v mch tnh phn nh tr (mantissa module). Khc vi 8086, thay v dng cc thanh ghi ri rc l mt ngn xp thanh ghi.
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8087 [s] 8086 [s] 10.6 11.9 24.4 56.3 62.5 13.1 1000 1000 2000 12250 8125 10680 750

Cn bc hai 22.5

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n v iu khin nhn v gii m lnh, dc v ghi cc ton hng, chy cc lnh iu khin ring ca 8087. Do , CU c th ng b vi CPU trong khi NU ang thc hin cc cng vic tnh ton. CU bao gm b iu khin bus, b m d liu v hng lnh.
CU - Control Unit T iu khin T trng thi B iu khin s NU - Numerical Unit Module ly tha Module nh tr

Bus d liu

m d liu T th Thanh ghi ngn xp

a ch trng thi

iu khin bus

Hnh 1.21 S khi ca 8087

16 15 14 13 12 11 10 9 19 23 25 24 22 31 33 21 34 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 CLK BUSY QS0 QS1 READY RQ/GT0 RQ/GT1 RST BHE/S7 8087 8086 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16/S3 A17/S4 A18/S5 A19/S6 S0 S1 S2 INT 8 7 6 5 4 3 2 39 38 37 36 35 26 27 28 32 INT (8259) 16 15 14 13 12 11 10 9 19 18 33 17 22 31 30 21 23 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 CLK INTR MX NMI READY RQ/GT0 RQ/GT1 RST TEST AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16/S3 A17/S4 A18/S5 A19/S6 S0 S1 S2 BHE/S7 LOCK QS0 QS1 RD 8 7 6 5 4 3 2 39 38 37 36 35 26 27 28 34 29 25 24 32

CLK (8284)

IRx (8259)

Hnh 1.22 S kt ni 8087 v CPU 8086

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Ngn xp thanh ghi c tt c 8 thanh ghi t R0 R7, mi thanh ghi di 80 bit trong bit 79 l bit du, bit 64 78 dng cho s m v phn cn li l phn nh tr. D liu truyn gia cc thanh ghi ny c thc hin rt nhanh do 8087 c rng bus d liu l 84 bit v khng cn phi bin i nh dng. Ngay sau khi reset PC, b ng x l kim tra xem n c c ni vi PC hay khng bng cc ng BHE /S7. 8087 s iu chnh di ca hng lnh cho ph hp vi CPU (nu dng 8086 th di l 6 byte). 8087 c mt thanh ghi trng thi l thanh ghi t th (tag word) gm cc cp bit Tag0 Tag7 lu tr cc thng tin lin quan n ni dung ca cc thanh ghi R0 R7 cho php thc hin mt s tc v nhanh hn. Mi thanh ghi t th c 2 bit xc nh 4 gi tr khc nhau ca cc thanh ghi Ri. Tag = 00: xc nh Tag = 01: zero Tag = 10: NAN, gi tr bt thng Tag = 11: rng 80287:
S0 S1 15 16 7 8 1 17 5 6 11 2 3 10 13 4 12 S0 S1 2 1 32 37 29 31 3 39 38 34 33 27 28 36 40 35 S0 S1 CLK CLK286 CMD0 CMD1 COD/INTA CKM HLDA NPS1 NPS2 NPRD NPWR PEACK READY RESET D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 ERROR BUSY PEREQ 23 22 21 20 19 18 17 16 15 14 12 11 8 7 6 5 26 25 24 36 38 40 42 44 46 48 50 37 39 41 43 45 47 49 51 52 31 54 53 64 57 59 61 63 29 34 33 32 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 8 7 1 66 65 68 67 6 5 4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CAP CLK BUSY ERROR HOLD INTR NMI PEREQ READY RST A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 BHE COD/INTA HLDA LOCK M/IO PEACK S0 S1

S0 S1 X1 X2 ARDY AYEN EFI F/C RES SRDY SYEN

CLK PCLK READY RESET

82284 19 3 18 2 15 14 7 6 1 13 12 11 8 9 5 16 17 4

S0 S1

S0 S1 M/IO CLK

82288 INTA IORC IOWC MRDC MWTC ALE DEN DT/R MCE

CEN/AEN CENL CMDLY MB READY

80287

S0 S1

80286

15 16 7 8 1 17 5 6 11 2 3

S0 S1 X1 X2 ARDY AYEN EFI F/C RES SRDY SYEN 82284

CLK PCLK READY RESET

10 13 4 12

Hnh 1.23 S kt ni gia 80286 v 80287

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Do 80286 c ch mch bo v nn mch ghp ni gia 80286 v 80287 c thit k khc 8087 n v iu khin CU. B ng x l y khng thc hin truy xut b nh trc tip. truy xut c b nh, 80287 khng nhng cn mt c v nh a ch n gin ca n m cn phi c tng cng thm chc nng qun l b nh ca 80286. Cu trc bn trong ca 80287 cng tng t nh 8087, ch c n v bus thay i cho ph hp vi 80286. Khc vi 8087, 80287 hot ng khng ng b vi CPU nn c th dng xung clock ring. 80387: u im ca 80387 so vi 80287 l c th thc hin cc php ton s hc nhanh hn. No c bus d liu 32 bit nh CPU v s dng cng ngh CMOS nn cng sut tiu th thp hn.

5. B thanh ghi
P 8086/8088 c tt c 14 thanh ghi ni. Cc thanh ghi ny c th phn loi nh sau: Thanh ghi d liu (data register) Thanh ghi ch s v con tr (index & pointer register) Thanh ghi on (segment register) Thanh ghi trng thi v iu khin (status & control register)

5.1. Cc thanh ghi d liu Cc thanh ghi d liu gm c cc thanh ghi 16 bit AX, BX, CX v DX trong na cao v na thp ca mi thanh ghi c th nh a ch mt cch c lp. Cc na thanh ghi ny (8 bit) c tn l AH v AL, BH v BL, CH v CL, DH v DL. Cc thanh ghi ny c s dng trong cc php ton s hc v logic hay trong qu trnh chuyn d liu. Bng 2.8: Thanh ghi S dng trong AX MUL, IMUL (ton hng ngun kch thc word) DIV, IDIV (ton hng ngun kch thc word) IN (nhp word) OUT (xut word) CWD Cc php ton x l chui (string) AL MUL, IMUL (ton hng ngun kch thc byte) DIV, IDIV (ton hng ngun kch thc byte) IN (nhp byte) OUT (xut byte) XLAT AAA, AAD, AAM, AAS (cc php ton ASCII) CBW (i sang word)
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AH BX CX CL DX

DAA, DAS (s thp phn) Cc php ton x l chui (string) MUL, IMUL (ton hng ngun kch thc byte) DIV, IDIV (ton hng ngun kch thc byte) CBW (i sang word) XLAT LOOP, LOOPE, LOOPNE Cc php ton string vi tip du ng REP RCR, RCL, ROR, ROL (quay vi s m byte) SHR, SAR, SAL (dch vi s m byte) MUL, IMUL (ton hng ngun kch thc word) DIV, IDIV (ton hng ngun kch thc word)

AX (ACC Accumulator): thanh ghi tch lu BX (Base): thanh ghi c s CX (Count): m DX (Data): thanh ghi d liu 5.2. Cc thanh ghi ch s v con tr Bao gm cc thanh ghi 16 bit SP, BP, SI v DI, thng cha cc gi tr offset ( lch) cho cc phn t nh a ch trong mt phn on (segment). Chng c th c s dng trong cc php ton s hc v logic. Hai thanh ghi con tr (SP Stack Pointer v BP Base Pointer) cho php truy xut d dng n cc phn t ang trong ngn xp (stack) hin hnh. Cc thanh ghi ch s (SI Source Index v DI Destination Index) c dng truy xut cc phn t trong cc on d liu v don thm (extra segment). Thng thng, cc thanh ghi con tr lin h n on stack hin hnh v cc thanh ghi ch s lin h n don d liu hin hnh. SI v DI dng trong cc php ton chui. 5.3. Cc thanh ghi on Bao gm cc thanh ghi 16 bit CS (Code segment), DS (Data segment), SS (stack segment) v ES (extra segment), dng nh a ch vng nh 1 MB bng cch chia thnh 16 on 64 KB. Tt c cc lnh phi trong on m hin hnh, c nh a ch thng qua thanh ghi CS. Offset ( lch) ca m c xc nh bng thanh ghi IP. D liu chng trnh thng c t on d liu, nh v thng qua thanh ghi DS. Stack nh v thng qua thanh ghi SS. Thanh ghi on thm c th s dng nh a ch cc ton hng, d liu, b nh v cc phn t khc ngoi on d liu v stack hin hnh. 5.4. Cc thanh ghi iu khin v trng thi Thanh ghi con tr lnh IP (Instruction Pointer) ging nh b m chng trnh (Program Counter). Thanh ghi iu khin ny do BIU qun l nhm lu tr offset t bt u on m n lnh thc thi k tip. Ta khng th x l trc tip trn thanh ghi IP.
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Thanh ghi c (Flag register) hay t trng thi 16 bit cha 3 bit iu khin (TF, IF v DF) v 6 bit trng thi (OF, SF, ZF, AF, PF v CF) cn cc bit cn li m 8086/8088 khng s dng th khng th truy xut c. 15 X 14 X 13 X 12 X 11 10 9 OF DF IF 8 TF 7 SF 6 ZF 5 X 4 3 AF X 2 PF 1 X 0 CF

OF (Overflow - trn): OF = 1 xc nh trn s hc, xy ra khi kt qu vt ra ngoi phm vi biu din DF (Direction- hng): xc nh hng chuyn string, DF = 1 khi P lm vic vi string theo th t t phi sang tri. IF (Interrupt - ngt): cho php hay cm cc interrupt c mt n TF (Trap - by): t P vo ch tng bc, dng cho cc chng trnh g ri (debugger). SF (Sign - du): dng ch cc kt qu s hc l s dng (SF = 0) hay m (SF = 1). ZF (Zero): = 1 nu kt qu ca php ton trc l 0. AF (Auxiliary nh ph): dng trong cc s thp phn ch nh t na byte thp hay mn t na byte cao. PF (Parity): PF = 1 nu kt qu ca php ton l c tng s bit 1 l chn (dng kim tra li truyn d liu) CF (Carry): CF = 1 nu c nh hay mn t bit cao nht ca kt qu. C ny cng dng cho cc lnh quay.

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