___________________________________________Chng 4 Truyn

IV - 1

ni tip bt ng b

CHNG 4

TRUYN NI TIP BT NG B
H THNG TRUYN D LIU
Vn hnh Dung lng knh truyn

MU TN HIU TRONG TRUYN BT NG B

VI IC THC HIN GIAO THC BT NG B
6402 ca INTERSIL 6850 ca MOTOROLA 8251 ca INTEL __________________________________________________________________________________________ ____

Nh bit, trong cc h thng truyn d liu c hai cch a tn hiu ln ng truyn: ni tip v song song. Cch truyn song song thng c truyn trn mt khong cch ngn, v d gia cc thit b trong cng mt phng nh t my tnh sang my in. Cch truyn ni tip thng c thc hin khi khong cch truyn kh xa. Ngoi ra, trong cch truyn ni tip, da vo cch thc hin s ng b gia ni pht v thu ta c hai ch hot ng: ng b v bt ng b. Trong ch bt ng b, xung ng h c to ra mt cch ring r my pht v my thu da vo tn s danh nh tng ng vi vn tc truyn (bit rate hoc baud rate). Trong ch ng b, ni pht c th gi xung ng h ti ni thu theo mt knh truyn song song vi knh truyn d liu hoc ni thu t to ra xung ng h bng cch tch tn hiu thi gian t dng d liu. Chng ny bn n ch truyn ni tip bt ng b. Chng ta s ln lt gii thiu tnh cht chung ca h thng truyn d liu, cc giao thc ca h thng truyn bt ng b. Chng ta cng s kho st vi IC thc hin chc nng bin i song song ni tip trong cc thit b thu pht .

4.1 H THNG TRUYN D LIU

4.1.1 Vn hnh
Mt mu h thng truyn d liu gm 3 b phn chnh (H 4.1) - Mt cp thit b x l tn hiu (Terminal, vd my tnh), mt ca my pht (chuyn thng tin thnh tn hiu s) v mt ca my thu (chuyn d liu s thnh thng tin). - Mt cp giao din ni tip, c gi l thit b u cui (Data Terminal Equipment, DTE) m nhim v chnh l bin i chui d liu song song thnh ni tip my pht v ni tip thnh song song my thu, ng thi thc hin mt s chc nng khc theo yu cu ca ngi s dng. - Mt cp giao din truyn d liu, c gi l thit b truyn d liu (Data Communication Equipment, DCE), thc hin s giao tip gia DTE v mi trng truyn.

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ni tip bt ng b
Giao din truyn d liu DCE Knh truyn Giao din truyn d liu DCE

Bo nhn My tnh hay Terminal thu

My tnh hay Terminal pht

Bn tin

Giao din ni tip DTE

Bn tin

Giao din ni tip DTE

(H 4.1)

Vn hnh ca h thng nh sau : My tnh gi bn tin di dng mt chui k t song song ti DTE. y bn tin c chuyn sang dng ni tip pht i tng bit tng thi im . i vi cc h thng bt ng b, thit b DTE s thm vo cc bit Start v Stop mi k t ni tip ny v nu c yu cu, bit kim tra chn l cng c thm vo y . y l mt dng ni tip cc tn hiu nh phn tng thch vi cc chun v in ca EIA nh RS232C (D), RS-422A hoc 423A. DCE l b phn chuyn tn hiu ra knh truyn. Dng chnh xc ca DCE ty thuc vo knh truyn, v d, cc DCE c dng thc ng dy hin nay l RS-422A hoc 423A c th thch hp truyn tn hiu di nn vi khong cch ti a l 1200m cn nu dng ng dy in thoi truyn th DCE tng thch phi l cc Modem. my thu b phn giao tip bin i chui k t ni tip thnh song song c c bi my tnh hay thit b truyn tin u cui khc. Mt bn tin bo nhn c phn hi ti my pht bo nhn ng thi bo li, nu c li bn tin s c pht li sau khi sa li. Trong trng hp ny my thu tr thnh my pht.

4.1.2 Dung lng ca knh truyn

Kh nng v phm cht ca mt knh truyn xc nh bi dung lng ca n. Nhc li, mt tn hiu tn s x , tn hiu ly mu phi c tn s ti thiu l 2x, yu cu mt bng thng ti thiu l x truyn , nu dng n bit m ha tn hiu ny th vn tc truyn s l 2nx, ta gi C = 2nx l dung lng ca knh truyn. V d, trong in thoi tn s tn hiu l 2,7kHz nu dng 1 bit (n = 1) m ha tn hiu th dung lng knh truyn C = 5,4kbps, nu dng s 2 bit ( n = 2) th C = 10,8kbps ..... Nh vy dung lng ca knh truyn t l vi s bit dng m ha tn hiu v bng thng ca n. Nhng khi bng thng ca knh truyn cng ln th tnh min nhiu ca h thng cng km nn gia tng dung lng knh truyn ngi ta thng tng s bit dng m ha tn hiu v dng phng php iu ch a pha.

4.2 Mu tn hiu trong ch truyn bt ng b

Trong ch truyn bt ng b thng tin c truyn i di dng tng k t v khong cch cc k t l ngu nhin. Tuy nhin to s ng b gia my pht v thu, giao thc tng 2 (Data link protocol) c qui nh c th v mu tn hiu trong h thng truyn bt ng b nh sau : - Mi k t gm mt s bit gi l k t d liu, s ny c th l 5 i vi m Baudot, 7 nu l m ASCII (American Standard Code for Information Interchange) v 8 nu l m EBCDIC (Extended Binary-Coded Decimal Information Code, m BCD m rng)

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IV - 3

ni tip bt ng b

- Ngoi ra, to s ng b, km theo cc bit m k t cn c cc bit Start trc mi k t v cc bit Stop sau mi k t. . Cc bit Start l cc bit 0 v cc bit Stop l bit 1. S bit Start lun lun l 1 bit cn s bit Stop c th l 1, 1,5 hoc 2 bit. - Nu c thm bit kim sot chn l (parity bit) th bit ny nm trc bit Stop. - trng thi ngh my pht lun pht i bit 1 gi l bit ngh (idle bit), nh vy my thu d ra bit Start khi c s bin i t 1 xung 0, sau l mt chui bit c s lng theo qui nh ca giao thc. Lu l trong truyn d liu, bit LSB ca k t lun c truyn i trc v c hai cch vit (v c) mt bn tin: theo chiu mi tn hng v bn phi v theo chiu hng v bn tri - Vit theo chiu mi tn hng v bn phi : bit LSB ca k t u tin s nm bn phi ca bn tin. Th d bn tin dng m ASCII gm 3 k t ABC c m ln lt l 41H (1000001), 42H (1000010) v 43H (1000011), bit LSB ca k t u tin (A) c pht i trc v phi nm bn phi ca bn tin nn chui d liu c pht i c dng: C B A p1000011 p1000010 p1000001. Vi cch vit ny, mi mu m ha ca mi k t c gi nguyn chiu ca n nhng th t cc k t trong bn tin b o. - Vit theo chiu mi tn hng v bn tri : bit LSB ca k t u tin s nm bn tri ca bn tin. Vi th d trn, bit LSB ca k t u tin (A) c pht i trc v phi nm bn tri ca bn tin nn chui d liu c pht i c dng: A B C 1000001p 0100001p 1100001p. Vi cch vit ny, th t cc k t trong bn tin c gi nguyn nhng cc bit trong mi k t b o chiu. Bit kim tra chn l (parity bit), nu c, s c thm vo sau mi k t (bit p trong cc th d trn) my pht thanh ghi dch bin i tn hiu song song thnh ni tip, c iu khin bi tn hiu Load/Shift, cc bit Start v Stop c t ng thm vo khi mch hot ng . my thu khi b phn d pht hin bit Start bi s thay i t 1 xung 0, s to ra tn hiu iu khin thanh ghi dch, sau khi dch s bit qui nh ca tn hiu k c bit parity v bit Stop, k t d liu c c ra di dng song song t thanh ghi dch.

(H 4.2)

(H 4.2) m t dng ca tn hiu trn ng truyn bt ng b (tn hiu l mu ch C vi parity chn v mt bit Stop) v b phn bin i song song ni tip trong my pht v thu. B phn ny chnh l cc thanh ghi dch.
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IV - 4

ni tip bt ng b

S ng b cc thanh ghi dch pht v thu c to bi xung ng h my pht v xung ng h my thu. D nhin cc xung ng h ny phi c cng tn s, l tn s tng ng vi vn tc truyn bit ca h thng. Nu xung ng h ni thu khng ph hp vi xung ng h ni pht, li do lch thi gian c th xy ra. C hai loi li : Li khi c bit v li do sai khung. Li do sai khung c to ra bi s tch ly cc lch thi gian, bit cui cng b sai a ti sai khung.

(H 4.3)

(H 4.3) l mt v d, gi s thi gian cho mt bit l 0,1 s (T = 0,1s =100ms) v s sai lch l 7% sm hn my thu, nh vy my thu c bit u tin thi im 93 ms thay v 100ms, bit th hai 186ms ..... cho n thi im 744ms my thu ang c bit th 7 nhng nhm l bit th 8, nh vy bit cui cng ca tn hiu b c sai, nu bit th 8 l bit 1 th my thu nhm l bit Stop v kt qu l c s sai khung. Bit Stop l bit kim tra lch thi gian tng i chnh xc, nu my pht hin bit Stop khng phi l bit 1 th s bo li khung ta ni bit Stop l khong bo v ti thiu gia cc khung k t. Ngoi ra bit parity cng gii hn c sai st ny v cc sai st do nhiu, tuy nhin phng php pht hin li ny khng t tin cy 100% v nu s bit sai l s chn th my thu khng pht hin c.

4.3 Vi IC thc hin TRUYN ni tip bt ng b

Trc y vic thu pht bt ng b c thit k da trn cc IC loi SSI v MSI. V d, to v kim tra chn l, ngi ta c th dng cc cng EX-OR . Hin nay s pht trin ca cng ngh ch to IC cho php s dng cc vi mch LSI thc hin cc chc nng thu pht tha mn giao thc truyn bt ng b. Chng ta gii thiu di y vi IC thu pht bt ng b (Universal Asynchronous Receiver,Transmitter, UART) hoc IC iu hp giao tip thng tin bt ng b (Asynchronous Communication Interface Adapter, ACIA), l cc IC : - UART 6402 ca Intersil - ACIA 6850 ca Motorola - USART 8251A ca Intel

4.3.1. UART 6402 ca Intersil

4.3.1.1 - Tnh nng k thut tng qut
6402 l UART loi IC CMOS/LSI dng giao tip vi my tnh hoc P qua knh d liu ni tip bt ng b.
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- My pht i d liu song song thnh ni tip v t ng thm vo cc bit Start v Stop. - My thu chuyn i cc bit Start, k t d liu, bit parity v bit Stop thnh d liu song song, kim tra li. Chiu di ca cc k t d liu c th l 5, 6, 7 hoc 8 bit. Parity c th l chn hay l, vic kim tra v to bit parity c th b qua, nu khng c yu cu. C th dng 1, 1,5 hoc 2 bit Stop.

4.3.1.2 - M hnh (H 4.4)

(H 4.4)

- ngha cc chn ca IC :

TRE : Transmit Reg. Empty : Ng ra, bo thanh ghi pht trng. TBRL : Trans. Buf. Reg. Load : Ng vo, np d liu vo thanh ghi m pht & pht TBRE : Trans. Buf. Reg. Empty : Ng ra, mc cao bo thanh ghi m pht trng, sn sng nhn d liu TBR7 - TBR0 : Trans. Buf. Reg. Data : D liu np vo thanh ghi m pht DR : Data Received : Ng ra, ln cao bo thu c mt k t d liu DRRST : Data Received Reset : Reset thanh ghi thu
ROE : Receive Buffer Output Enable : Cho php thu tn hiu t thanh ghi m thu RBR7 - RBR0 : Receive Buf.Reg. Data : D liu thu t thanh ghi m thu CRL : Control Reg. Load : Ng vo, mc cao cho php np t iu khin vo thanh ghi iu khin CR4 - CR0 : Control Reg. Data : T hp 5 bit to thnh mt t iu khin PE,FE,OVE : Parity, Framing, Overflow flags : C bo li chn l, li khung, li trn SOE : Status O/P Enable : Cho php ng ra trng thi

MRST : Master Reset : t li IC

RC,TC : Receive Clock, Trans. Clock : Xung ng h Thu, Pht

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RxD, TxD : Receive Data, Trans. Data : D liu thu pht. Vic chn cc chun trong giao thc theo qui nh ca bng 4.1 di y

Bng 4.1 : 6402 control word

CR4 CR3 CR2 CR1 CR0

Chn chiu di k t Character Length Select CLS1 CLS0 C Kim Tra chn l ? PI (Parity Inhibit) Chn Kim Tra chn EPE (Even Parity Enable) Chn s bit stop SBS Stop Bit Select

00 = 5 bit 01 = 6 bit 10 = 7 bit 11 = 8 bit 1 = khng kim tra chn l v PE = 0 0 = c kim tra chn l 1 = kim tra chn 0 = kim tra l 0 = 1 bit stop 1 = 1,5 (k t 5 bit) 1 = 2 (k t 6, 7, 8 bit)

4.3.1.3 - Vn hnh
- Vn hnh ca IC c thc hin qua cc thao tc sau y : - Khi ng : khi ng 6402, ln lt thc hin 3 bc : - t t iu khin vo cc chn CR4 - CR0 chn giao thc truyn. - a chn CRL ln cao np t iu khin vo thanh ghi iu khin. - a chn MRST ln cao reset my thu v my pht. - Pht mt k t : np mt k t vo thanh ghi pht v pht i, ln lt thc hin cc bc : - Chn TBRE ln cao bo thanh ghi m pht trng. - Cc bt ca k t c np vo chn TBR7 - TBR0. - a TBRL ln cao np data vo thanh ghi m. - Tn hiu pht i khi TBRL xung thp. - Thu mt k t : thu mt k t, ln lt thc hin cc bc sau : - Chn DR ln cao bo thu mt k t mi - a ROE xung thp c k t t ng ra ca b m vo CPU - c cc trng thi li cc ng PE, FE v OVE (Cc chn ny cho php bi SOE trng thi thp). Mc cao ca cc chn ny cho bit pht hin li. PE cho bit li chn l, FE cho bit li khung v OVE cho bit li trn (Overrun) l li do tc thu k t ln hn tc c k t. - Reset thanh ghi thu bng cch a chn DRRST xung mc thp Tc pht v thu bit ty thuc vo xung ng h trn hai chn TC v RC. 6402 c mch chia 16 c nh tn s xung clock vo phi bng 16 ln tc baud mong mun. Tc c th ln ti 250 kbps.

4.3.1.4 Giao tip ca 6402 vi vi x l

Giao tip gia 6402 v b vi x l c phn phc tp (H 4.5), nhng t s dng phn mm khi thc hin cc chc nng thu pht

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ni tip bt ng b

(H 4.5)

- Vic thc hin giao thc bt ng b (tc to t iu khin) nh vo kha chuyn mch in t. - Vic bo li thc hin nh mt led. - Mch c Reset bi c phn cng v phn mm. - Mch n n thc hin chc nng Reset thanh ghi thu t ng sau khi thu k t. - Vic c k t thu tc ng bi tn hiu RD CPU v tn hiu select UART t mch gii m a ch. - Tng t cho vic np d liu vo thanh ghi m pht pht : tc ng bi tn hiu WR ca CPU v tn hiu select UART. - Cc ngt ring bit ca P c to ra bi tn hiu DR v TBRE

4.3.2 . ACIA 6850 ca Motorola

4.3.2.1 - c tnh tng qut
V tnh cht vt l, 6850 thuc loi NMOS c 24 chn, c thit k giao tip vi bus ca h P 6800 ca Motorola. 6850 c th lp trnh phn mm v ch c mt thanh ghi iu khin Ngoi ra, vi 6850 ta c th thit lp cc giao thc sau y : - C th truyn 8 hoc 9 bit - C th chn parity chn hoc l - Kim tra li parity, overrun, v framing - C th chn cc mode hot ng vi tn s xung ng h chia cho h s 1, 16 hoc 64 - Tc truyn d liu ln ti 500 kbps - C cc chc nng iu khin ngoi vi/modem - C 1 hoc 2 bit Stop - C thanh ghi d liu i.

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4.3..2.2 - M hnh v s khi (H 4.6)

(H 4.6)

* ngha cc chn : - CS2 , CS1, CS0 : Chip slect : chn chip - RS : Reg. Select : Chn thanh ghi (1: D liu; 0: iu khin) - R/ W : Read/Write
- IRQ : Interrupt request : Yu cu ngt

- D7-D0 : Data Bus I/O : Bus d liu vo/ra - E : Data I/O Enable and Clkng (iu khin xut nhp d liu vo/ra bus) - RxCLK, TxCLK : Ng vo xung ng h thu, pht - CTS : Clear To Send
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- RTS : Request To Send - CD : Carrier Detect : D sng mang - RxD, TxD : D liu thu, pht - VSS : Mass ngun (GND) - VDD : Ngun dng (+5 V) Cc chi tit ca giao thc c chn bng cch ghi 1 byte vo thanh ghi iu khin da theo bng 4.2. Trng thi thu pht v trng thi li c c t thanh ghi trng thi, da vo bng 4.3 Thanh ghi iu khin hoc thanh ghi trng thi c chn khi chn RS xung thp v thanh ghi d liu thu hoc pht c chn khi RS ln cao. Thanh ghi d liu pht v iu khin ch c th ghi (write). Thanh ghi d liu thu v trng thi ch c th c (read)
Bng 4.2 6850 Control Register Word Bits
D7 D6 D5 Cho php ngt thu C7 iu khin ngt pht - pht C6 C5 1 = IRQ thp khi thanh ghi m thu y 0 = Khng cho php ngt thu 00 = RTS low. Khng cho php ngt pht 01 = RTS low. Cho php ngt pht

10 = RTS high. Khng cho php ngt pht 11 = RTS low. Khng cho php ngt pht & Pht bit 0 (break level) D4 Chn chiu di k t, KTchn 000 = 7 bit + Chn + 2 Stop l, S bit stop 001 = 7 bit + L + 2 Stop C4 010 = 7 bit + Chn + 1 Stop D3 C3 011 = 7 bit + L + 1 Stop 100 = 8 bit + 2 Stop 101 = 8 bit + 1 Stop D2 C2 110 = 8 bit + Chn + 1 Stop 111 = 8 bit + L + 1 Stop D1 Chon h s chia tn xung CK 00 = : 1 C1 01 = : 16 D0 C0 10 = : 64 11 = Master Reset Ghi ch : * Master reset, thanh ghi iu khin c bt C1 C0 = 11, Reset tt c cc bt ca thanh ghi trng thi v a chn RTS v IRQ ln cao * Bt C7 = 1, CPU b ngt nu: - Thanh ghi d liu thu y - B trn - C mt bin i t thp ln cao chn CD (modem khng d ra sng mang)

Bng 4 .3 6850 Status Register Bits

D7 D6 D5 D4 D3 D2 D1

Trng thi pin IRQ IRQ Li chn l PE Li trn (Overrun) OVRN Li khung FE Xa pht CTS D sng mang CD Thanh ghi pht trng TDRE

1 = IRQ low Reset bi vic c thanh ghi m thu hay vit vo thanh ghi pht 1 = C li chn l Set/Reset khi chuyn d liu thu 1 = Bo li trn v gi bit RDRF = 1 Set/Reset khi chuyn d liu thu 1 = C li khung Set/Reset khi chuyn d liu thu Ty trng thi chn CTS Chn CTS mc cao s v hiu ha bit TDRE 1 = chn CD mc cao (no carrier) ( xem ghi ch) 1= Phn pht ch nhn k t. Reset bi vic ghi vo thanh ghi pht

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ni tip bt ng b

Thanh ghi thu y 1 = Phn thu ch c k t. RDRF Reset bi vic c thanh ghi m thu Ghi ch : bit CD ln 1 lm cho chn IRQ xung thp khi bit C7 set = 1. Bit CD vn gi 1 sau khi pin

CD xung thp v b xa sau khi c thanh ghi trng thi, v thanh ghi d liu thu, hoc cho n khi MRST xy ra.

Thng tin trong thanh ghi trng thi c c bi CPU v cho bit trng thi hin hnh ca 6850 Bit D0 : (RDRF) Bt ny set 1 sau khi data nhn c truyn t thanh ghi dch thu ti thanh m thu v n c xa sau khi CPU c data Bit D1 : (TDRE) Bt ny c set khi data chuyn t thanh ghi m pht n thanh ghi dch pht, n c xa khi CPU vit t mi vo thanh ghi m pht Bit D2 : (CD) Bt ny c set nu Modem khng d ra sng mang Bit D3 : (CTS) Bt ny c reset ( =0) nu c tn hiu tc ng xa gi Bit D4 : (FE) Bt ny set nu my thu khng d ra bt stop ( sai khung) Bit D5 : (OVRN) Bt ny set nu 6850 chuyn data thu c t thanh ghi dch thu vo thanh ghi m thu trc khi CPU c ni dung trong thanh ghi ny, n ch rng c mt phn bn tin b mt. Bt ny c reset khi CPU c thanh ghi m thu
Bit D6 : (PE) Bt ny set khi my thu d ra li parity

Bit D7 : (IRQ) Bt ny set khi c tn hiu tc ng trn ng ra IRQ ti CPU

4.3.2.3 Vn hnh
Vn hnh 6850 c m t qua cc bc : Khi ng, pht mt k t v thu mt k t - Khi ng : Ch rng 6850 khng c reset phn cng. Vic reset chip c iu khin bng cch ghi byte iu khin vo thanh ghi iu khin (lp cc bit C0 = C1 = 1) - Reset chip: cc bit trong thanh ghi trng thi v 0 v hai chn RTS v IRQ ln cao - Lp trnh t iu khin chn giao thc hot ng. - Pht mt k t Khi khi ng chip ta ch cn 2 bc pht mt k t - Chn CTS phi mc thp - i cho n khi bt TDRE = 1 (trong thanh ghi trng thi) - Ghi k t cn pht vo thanh ghi d liu pht Mt v d thy hot ng pht ca 6850. T iu khin ghi vo thanh ghi c dng 10101101. Do bit D6 v D5 l 0 v 1, mt tn hiu mc thp tc ng cho bi chn RTS gi ti modem, sau mt thi gian tr xc nh, modem gi tn hiu tc ng mc thp ti chn CTS , bo d liu sn sng gi i. CPU c thanh ghi trng thi v nu bit D1 (TDRE) ln 1 n s gi t k tip n thanh ghi m pht, t ny c cht vo thanh ghi khi chn E chuyn t mc cao xung thp, iu ny khin cho bit TDRE reset xung 0. Mch logic bn trong to bit kim tra l theo yu cu v chuyn d liu cng vi bit start, bit parity v bit stop vo thanh ghi dch pht. D liu c chuyn ra ngoi trn ng TxD vi bit rate bng 1/16 tn s xung ng h chn TxCLK . Khi d liu chuyn vo thanh ghi dch pht bit TDRE ca thanh ghi trng thi ln 1, mt ln na v bit D6 v D5 ca thanh ghi iu khin l 0 v 1 nn khi TDRE ln 1 mt tn hiu ngt t ng gi n CPU ng ra IRQ . CPU tr li bng cch gi t th 2 ti thanh ghi m pht mc d t th nht c th cha hon ton chuyn ra ngoi. S d c nh vy v 6850 dng thanh ghi i v vic ny lm gia tng vn tc truyn.
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- Thu mt k t C 3 bc cn thit thu mt k t

- Chn CD phi mc thp - i cho n khi bit RDRF = 1 - c trng thi li t thanh ghi trng thi - c k t thu t thanh ghi d liu thu Cc ngt pht v/hoc thu c th c cho php bi t iu khin (xem bng 4.2) Chn IRQ s mc thp bt c khi no cc bit trng thi TDRE v/hoc RDRF l 1. Trong khi chn IRQ thp bit trng thi IRQ l 1.
Di y l qu trnh thu mt k t

Tn hiu ni tip ti chn RxD ca ACIA. Thng thng chn ny mc cao khi khng c tn hiu vo. Khi c tn hiu ti bit u tin l bit start (bit D0) lm chn RxD chuyn t cao xung thp. Gi s tn s xung ng h thu bng 16 ln vn tc bit, th sau 8 chu k ng h k t khi chn RxD chuyn t cao xung thp, ng vo ny c kim tra mt ln na v nu n vn cn mc thp, bit start mi c gi tr, nu khng ACIA xem tn hiu nhn c l nhiu v tip tc gim st s thay i chn ny tm ra bit start. Dng 8 chu k ng h sau khi c s thay i trng thi ca chn RxD khin cho data c ly mu ng ngay im gia v c chuyn vo thanh ghi dch thu sau mi 16 xung ng h. Vic kim tra li c thc hin v khi c li xy ra cc bit bo li tng ng trong thanh ghi trng thi s c set. Sau khi s bit d liu mong mun nhn c, bn tin c chuyn song song t thanh ghi dch thu ti thanh ghi m thu v bit 0 (RDRF) ca thanh ghi trng thi c set ln 1. Nu bit 7 ca thanh ghi iu khin c set (a ln 1) trong sut thi gian khi ng, mt ngt ti CPU c t ng to ra do chn IRQ xung thp. CPU thc hin chng trnh phc v ngt v c thanh ghi trng thi bit nguyn nhn ngt. Nu CPU tm thy bit RDRF set n s c d liu trong thanh ghi m thu. Hnh ng ny xa bit RDRF ca thanh ghi trng thi. Phn thu ca 6850 cng dng thanh ghi i cho php t k tip chuyn vo thanh ghi dch trong khi t trc cha hon ton c c vo CPU nhm tng vn tc truyn nh ni trn.

4 .3.2.4 Giao tip ca 6850 vi vi x l

ACIA 6850 c th giao tip vi h vi x l 6800 hoc 6502 (H 4.7)

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Ghi ch:

Trong mch (H 4.7) - 2 l tn hiu xung ng h chun cho tt c thit b ngoi vi ca 6800. - VMA : Valid memory address, ng ra ch bo cho cc thit b ngoi vi ca 6800 bit c mt a ch c hiu lc trn bus a ch. - Mch giao tip trn khng truyn qua modem (cc chn CTS v CD ni mass) - Vic gii m a ch c thc hin t bn ngoi cho ng vo CS2 - Chn CS1 v CS0 phi ni ln mc cao - Cc ngt c bo cho CPU t chn IRQ bo cho CPU bit cc thanh ghi thu hoc pht sn sng. Cc thao tc ny cng c th chn la bi vic lp trnh thch hp cho cc bit cho php ngt trong thanh ghi iu khin.

4.3.3. USART 8251A ca Intel :

4 .3.3.1 - Tnh nng tng qut :
8251A l mt chun cng nghip USART, c ch to t k thut NMOS, c 28 chn, c thit k truyn d liu tc ln n 64 kbps tng thch vi h P ca Intel nh MCS-48, 80, 85 v iAPX-86, 88.....8251A c dng nh mt thit b ngoi vi v c lp trnh bi CPU truyn d liu ni tip. USART nhn cc k t d liu t P dng song song, sau i chng thnh dng ni tip pht i. ng thi, 8251A c th thu dng d liu ni tip v i chng thnh cc k t d liu song song gi n P. USART s bo cho P bit khi no c th nhn mt k t t P pht, hoc khi no thu c mt k t cho P c. P c th c trng thi ca USART bt c lc no. Nhng trng thi ny bao gm cc li truyn d liu v cc tn hiu iu khin nh l RxRDY (Receiver Ready) v TxRDY (Transmitter Ready)

4.3.3.2 - M hnh v s khi (H 4.8)

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8251A c thanh ghi d liu i v cc thanh ghi iu khin v trng thi ring bit, iu ny lm n gin vic lp trnh v tng hiu qu s dng thi gian ca CPU (tng vn tc thu, pht). - ch truyn bt ng b my thu d v ngng hot ng t ng m khng cn s iu khin ca CPU - Kt thc mt cuc lin lc, TxD line lun tr v trng thi ngh (mark state), tc pht tn hiu 1, tr khi bit D3 (SBRK) trong thanh ghi iu khin c set = 1 - Trng thi logic ca bit D0 (Tx Enable) cho php my truyn xong cc k t np vo thanh ghi mc d c lnh dng. 8251A c kh nng thc hin giao thc truyn ng b v bt ng b. y ta ch bn n kh nng truyn bt ng b. - Trong ch truyn bt ng b, chiu di k t c th t 5 n 8 bit vi tn s xung clock bng 1, 16, 64 ln gi tr baud - C kh nng pht k t Break v 1, 1,5 hoc 2 bit Stop - D c cc li chn l, sai khung v li trn - Ng vo v ra tng thch TTL. - Chc nng cc khi v ngha cc chn IC :
- Data Bus Buffer :

L b m 8 bit, hai chiu, 3 trng thi c dng giao tip 8251A vi Bus d liu ca h thng. D liu c pht hay thu ty thuc lnh Input hay Output ca CPU. T iu khin, t lnh v thng tin trng thi cng c truyn qua Data Bus. Khi chc nng ny nhn tn hiu t Bus iu khin ca h thng v pht tn hiu iu khin hot ng ca c IC, n cha thanh ghi t iu khin ch hot ng (control word), thanh ghi t iu khin vn hnh (command word) l cc thanh ghi xc nh nhng chc nng ca IC Khi ny gm cc chn :
D0 - D7 : Data bus I/O : bus d liu vo/ra

RST : Reset : t li : mc cao ca ng vo ny a 8251A vo trng thi ngh cho ti khi c mt t control mi c vit vo xc inh ch vn hnh ca n. CLK : System Clock : Xung ng h h thng : ng vo dng nh thi bn trong IC, tn s xung Clock phi ln hn 30 ln tc thu pht bit WR : Write : CPU ghi d liu hay t control vo 8251A, y l ng vo tc ng mc thp. RD : Read : CPU c d liu hay thng tin v trng thi t 8251A CS : Chip select : chn chip C/ D : Control/Data : iu khin/D liu. y l ng vo, lin kt vi WR v RD bo cho 8251A bit t ang Data bus l k t d liu, t control hay thng tin v trng thi. Bng 4.4 di y cho thy kt qu ca s phi hp cc ng vo ni trn :

Bng 4 .4

C/ D RD WR CS

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0 0 1 1 x x

0 1 0 1 1 x

1 0 1 0 1 x

0 0 0 0 0 1

8251A DATA DATA BUS DATA BUS 8251A DATA STATUS DATA BUS DATA BUS CONTROL DATA BUS 3-STATE DATA BUS 3-STATE

- Modem Control : 8251A c mt tp hp ng vo/ra iu khin c dng n gin s giao tip vi hu ht cc Modem, gm cc chn : DSR : Data Set Ready : Ng vo iu khin bi bit D7 ca thanh ghi trng thi (D7 = 1 chn DSR xung thp). Trng thi ca n c th c test bi CPU nh tc v c trng thi. DTR : Data Terminal Ready : Ng ra iu khin bi bit D1 ca thanh ghi iu khin vn hnh (command; D1 = 1 chn DTR xung thp). Trng thi ca n c th c kim sot bi t command. C th dng test chn DTR ca modem . RTS : Request To Send : Ng ra iu khin bi bit D5 trong thanh ghi iu khin (D5 = 1 chn RTS xung thp). C th c dng test chn RTS ca modem. CTS : Clear To Send : Ng vo, mc thp cho php 8251A pht d liu ni tip nu bit Tx Enable trong thanh ghi t command (D0 mc 1). Khi phn pht Tx ang pht nu bit TxEnable = 0 hoc chn CTS ln cao, Tx s pht tt c Data trong USART trc khi ngh. - Transmitter buffer : Nhn Data song song t Data bus buffer, i sang ni tip, thm cc bit c bit v xut tn hiu hn hp ra ng TxD khi c cnh xung ca xung Clock pht TxC . - Transmitter Control :
TxC qun l tt c hot ng lin quan n vic pht tn hiu

TxRDY : Trans. Ready, ng ra ny bo cho CPU bit my pht sn sng nhn d liu. Chn TxRDY c th dng nh l mt ngt cho h thng, v n c che bi Tx Enable, hoc i vi tc v hi vng (polling), CPU c th kim sot TxRDY bng tc v c trng thi (bit D0 trong thanh ghi trng thi). TxRDY t ng reset bi cnh xung (leading edge) ca WR khi k t d liu c np t CPU TxE : Trans. Reg. Empty : thanh ghi pht trng : Khi 8251A khng c g pht, ng ra TxE ln cao. TxE c th c dng ch lc chm dt pht sao cho CPU bit lc phi i sang ng dy khc trong cch truyn bn song cng (HDM) TxC : Transmitter Clock : Xung ng h pht c tn s l mt bi ca vn tc iu ch (Baud rate), ty theo lp trnh, bi ny c th l 1, 16, 64 (ch dng cho ch bt ng b). Th d: Vn tc iu ch l 110 baud th: - TxC = 110 Hz khi ch x1 (B1B0 = 01) - TxC = 1,72 KHz khi ch x1 (B1B0 = 10) - TxC = 7,04 KHz khi ch x1 (B1B0 = 11) - Receiver Buffer : Nhn d liu ni tip i thnh song song, kim tra li v gi k t ti CPU. D liu ni tip vo ng vo RxD bi cnh ln ca tn hiu RxC . - Receiver Control :
Qun l tt c hot ng thu ca IC
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RxRDY : Ng ra ny bo 8251A cha mt k t sn sng c vo CPU. RxRDY c th ni vo cu trc ngt ca CPU hay i vi tc v hi vng, CPU c th kim sot trng thi ca RxRDY bng cch dng tc v c trng thi (bit D1). Bit RxE (Receive Enable, D2) trong thanh ghi iu khin vn hnh (command) c tc dng iu khin chn RxRDY, khi RxE = 0 th RxRDY iu kin khng c php. RxC : Receiver Clock : Xung ng h thu c tn s l bi ca vn tc iu ch: x1, x16 v x64 SYN/BRK : Sync detect/Break detect : D ng b/ Ngng: - Khi hot ng ch truyn ng b chn ny c th l ng vo hoc ng ra ty vo t control lp trnh * Khi l ng ra ( ch ng b bn trong) chn ny ln cao khi phn thu d ra t ng b. * Khi l ng vo ( ch ng b bn ngoi) tn hiu mc cao ti khin 8251A bt du thu d liu khi c cnh ln ca xung ng h k tip. - Khi hot ng ch truyn bt ng b chn ny l ng ra v ln cao khi my thu ngng nhn tn hiu trong khong thi gian tng ng 2 k t. Chn ny c reset bi tn hiu MRST hay chn RxD ln cao. Break Detect cng c th c c nh mt bit trng thi. Khc vi 6402, 8251A tt c d liu n v t P u i qua bus d liu (data bus) ni vi cc chn D0-D7. a ch thanh ghi c nh bi chn C/ D (Control/Data). Khi chn ny ln cao cho php chn nhm thanh ghi iu khin (mode, command, status). Khi chn ny xung thp cho php chn cc thanh ghi d liu (l cc b m thu v pht). B m pht v thanh ghi iu khin ch c th ghi(write), tri li b m thu v thanh ghi trng thi ch c th c (read). Thanh ghi chn ch (mode) ch c th c truy xut sau khi chip c reset.

Bng 4 .5 T chn ch v iu khin vn hnh (Mode Control and Command word bits)
D7 D6 D5 D4 D3 D2 D1 D0 Chn s bit stop S1 S0 Chn KT chn EP Cho php KT chn l PEN Chn chiu di k t L1 L0 Chn h s chia xung CK B1 B0 00 = khng 01 = 1 bit Stop 10 = 1,5 bit Stop 11 = 2 bit Stop 1 = Chn 0 = l 1 = C bit chn l 0 = Khng 00 = 5 Bits 01 = 6 Bits 10 = 7 Bits 11 = 8 Bit 00 = Sync. Mode 01 = : 1 10 = : 16 Vo ch tm t SYNC. EH Reset ni 1 = Cho php tm t SYN. 1 = Reset 1 = Chn RTS thp 0 = Cao 1 = Reset c li PE,OE,FE v 0 1 = Chn TxD thp 0 = Vn hnh bnh thng 1 = Enable 0 = Disable 1 = Chn DTR thp 0 = Cao 1 = Cho php 0 = Khng

IR
Yu cu pht

RTS
Reset li

ER
Pht k t Break

SBRK
Cho php thu

RxEN
DTE sn sng

DTR
Cho php pht

11 = : 64

TxEN

T chn ch (mode control)

T iu khin vn hnh (command)

S dng 8251A i hi cc on chng trnh ngn np t chn mode (mode control word) v t iu khin (command word) cho cc thanh ghi iu khin, cng nh c nh k thanh ghi trng thi (status). Chi tit ca 3 thanh ghi ny c cho trong bng 4.5 v 4.6
Bng 4 .6 Thanh ghi trng thi 8251A (Status Register)
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IV - 16 D7 D6 D5 D4 D3 D2 D1 D0 DCE sn sng DSR D t SYN SYNDET Li khung FE Li trn OE Li chn l PE Thanh ghi pht trng TxEmpty Phn thu sn sng RxD Phn pht sn sng TxD

ni tip bt ng b

1 = Chn DSR thp 0 = Cao 1 = D ra t SYN (Synchronous only) 1 = C li khung, reset bng cch ghi ER = 1 (Asynchronous only) 1 = C li trn 1 = C li chn l 1 = Trng 0 = Bn 1 = Sn sng thu k t mi 1 = Sn sng ghi k t mi pht

Ghi ch: bit TxD c ngha hi khc vi chn TxRDY. Bt TxD khng km theo iu kin ca chn CTS v TxEN trong lc chn TxRDY km theo c 2 iu kin ny

4.3.3.3 - Vn hnh
Ton b hot ng ca 8251A c lp trnh bi phn mm h thng. Mt tp t iu khin c pht ra t CPU khi ng 8251A, cc t iu khin ny s qui nh cc gi tr vn tc thu pht, chiu di k t, s bit stop, chn parity, ng b hay bt ng b (bit parity khng c xem l bit d liu khi lp trnh chiu di t). Trong trng hp chiu di t < 8 bit, nhng bit thp (t LSB) l d liu, nhng bit khng dng (bit cao) th khng cn quan tm (don't care) khi vit d liu vo 8251A v l 0 khi c d liu t 8251A). Vn hnh ca USART 8251A c m t qua cc bc : khi ng, pht mt k t v thu mt k t.
- Khi ng 8251A

- Reset chip - Ghi vo thanh ghi chn ch mt byte (t CPU) chn giao thc mong mun (bng 4.5) Sau khi thit lp ch hot ng, vic pht v thu c iu khin bng cch ghi nh k t iu khin vo thanh ghi iu khin bao gm cc bc sau : - Reset chip - Ghi t chn ch vo thanh ghi mode (mode register) - Ghi t iu khin vo thanh ghi command (command register). i vi 8251A, t i sau t mode lun lun l t command v t command c th ghi vo thanh ghi bt c lc no trong khi d liu trong lc 8251A ang hot ng. tr li vi t chn ch , bit master reset (D6) trong t command c th c set khi ng reset ni v a 8251A tr v trng thi khi ng, v t iu khin ghi vo lc ny phi l t mode.
- Pht mt k t

pht mt k t, bit TxEN trong thanh ghi iu khin phi logic 1 v chn CTS phi mc thp : - i cho n khi chn TxRDY ln cao hoc cho n khi bit TxRDY trong thanh ghi trng thi l 1. - Ghi k t cn pht vo thanh ghi m pht.

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USART t ng thm cc bit start, stop, kim tra chn l. K t c pht i ni tip trn ng TxD vi bit LSB c pht trc, cc bit c di ra ngai mi khi c cnh xung ca xung ng h TxC vi vn tc bng 1, 1/16, 1/64 tn s xung ng h.
- Thu mt k t

thu mt k t ng thi kim tra li ca k t ny, cn thc hin cc bc sau : - i cho n khi chn RxRDY ln cao hoc cho n khi bit RxRDY trong thanh ghi trng thi l 1 - c trng thi li t thanh ghi trng thi - c k t t thanh ghi m thu - Reset trng thi li bng cch ghi bit ER = 1 (D4) trong thanh ghi command. Tc pht v thu bit c quyt nh bi tn s ca xung clock a vo chn RxC / TxC chia theo h s 1, 16 hoc 64 chn trong t chn mode. Hot ng thu ca 8251A ging nh 6850 ca Motorola, bt u sau khi hiu lc ha bit start, d liu c ly mu khi c cnh ln ca xung ng h RxC .

4..3.3.4 Giao tip vi CPU ca 8251A

(H 4.9) m t kt ni gia 8251A v CPU

Giao tip gia 8251A v CPU s dng c tnh xut nhp ca b tch ly (accumulator I/O) ca Intel 8085

(H 4.9)

- Thu mt k t Vic thu mt k t thc hin khi chn RxRDY hoc bit RxRDY trong thanh ghi trng thi ln mc cao to ngt a ti P bo sn sng thu. - Pht mt k t Quyt nh bi bit TxRDY trong thanh ghi trng thi, trong trng hp ny CPU phi thc hin vic hi vng (ch khng to ngt), khi nhn c mc cao ca bit TxRDY (hoc chn TxRDY ln cao), CPU ghi k t cn pht vo thanh ghi m pht.

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