Adder

Aim: VHDL code for Full Adder library ieee; use ieee.std_logic_1164.all; entity full is port ( a,b,c : in std_logic ; sum , carry : out std_logic); end full ; architecture fulladder of full is begin sum <= a xor b xor c ; carry <= (a and b) or ( b and c) or (c and a); end fulladder ;

Aim: Verilog code for full Adder module fa (a, b, cin, s, cout); input a, b, cin; output s, cout; assign s = (a ^ b ^ cin); assign cout = (a & b) | (b & cin) | (cin & a); endmodule

Aim: VHDL code for half adder library ieee; use ieee.std_logic_1164.all; entity half is port ( a,b, : in std_logic ; sum , carry : out std_logic); end half ;

architecture halfadder of full is begin sum <= a xor b ; carry <= (a and b); end fulladder; Aim: Verilog code for Half adder module ha(a,b,s,c); input a,b; output s,c; assign s=a^b; assign c=a&b; endmodule

Multiplexers
Aim: VHDL code for 16 to 1 Multiplexer library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity mux is port(s:in std_logic_vector(3 downto 0); i:in std_logic_vector(15 downto 0); y: out std_logic); end mux; architecture mux of mux is begin process(s,i) begin case s is when "0000"=>y<=i(0);

when "0001"=>y<=i(1); when "0010"=>y<=i(2); when "0011"=>y<=i(3); when "0100"=>y<=i(4); when "0101"=>y<=i(5); when "0110"=>y<=i(6); when "0111"=>y<=i(7); when "1000"=>y<=i(8); when "1001"=>y<=i(9); when "1010"=>y<=i(10); when "1011"=>y<=i(11); when "1100"=>y<=i(12); when "1101"=>y<=i(13); when "1110"=>y<=i(14); when others=>y<=i(15); end case; end process; end architecture mux Aim: Verilog code for 16 to 1 multiplexer module mux (i, s, y); input [15:0] i; input [1:0] s; output y; reg y; always@(i or s) begin case(s) 4'b0000: y = i [0]; 4'b0001: y = i [1]; 4'b0010: y = i [2];

4'b0011: y = i [3]; 4'b0100: y = i [4]; 4'b0101: y = i [5]; 4'b0110: y = i [6]; 4'b0111: y = i [7]; 4'b1000: y = i [8]; 4'b1001: y = i [9]; 4'b1010: y = i [10]; 4'b1011: y = i [11]; 4'b1100: y = i [12]; 4'b1101: y = i [13]; 4'b1110: y = i [14]; 4'b1111: y = i [15]; endcase end endmodule

Aim: VHDL code for 8 to 1 multiplexer library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity mux is port(s:in std_logic_vector(2 downto 0); i:in std_logic_vector(7 downto 0); y: out std_logic); end mux; architecture mux of mux is begin process(s,i) begin case s is

when "000"=>y<=i(0); when "001"=>y<=i(1); when "010"=>y<=i(2); when "011"=>y<=i(3); when "100"=>y<=i(4); when "101"=>y<=i(5); when "110"=>y<=i(6); when others=>y<=i(7); end case; end process; end architecture mux

Aim: Verilog code for 8 to 1 multiplexer module mux (i, s, y); input [7:0] i; input [1:0] s; output y; reg y; always@(i or s) begin case(s) 3'b000: y = i [0]; 3'b001: y = i [1]; 3'b010: y = i [2]; 3'b011: y = i [3]; 3'b100: y = i [4]; 3'b101: y = i [5]; 3'b110: y = i [6]; 3'b111: y = i [7]; endcase end

endmodule Aim: VHDL code for 4:1 multiplexer library ieee; use ieee.std_logic_1164.all; entity Mux is port( S: O: i: in std_logic_vector(3 downto 0);

in std_logic_vector(1 downto 0); out std_logic_vector);

end Mux; architecture behv1 of Mux is begin process(i,S) begin case S is when "00" => O <= i0; when "01" => O <= i1; when "10" => O <=i2; when others =>O <= "i(3)"; end case; end process; end behv1;

Aim: Verilog code for 4 to 1 multiplexer module mux (i, s, y); input [3:0] i; input [1:0] s; output y; reg y; always@(i or s) begin case(s)

2'b00: y = i [0]; 2'b01: y = i [1]; 2'b10: y = i [2]; 2'b11: y = i [3]; endcase end endmodule

Aim: VHDL code for 2 to 1 multiplexer library ieee; use ieee.std_logic_1164.all; entity Mux is port( i: S: O: end Mux; architecture behv1 of Mux is begin process(i,S) begin case S is when "0" => O <= i0; in std_logic_vector(1 downto 0); in std_logic_vector out std_logic_vector);

when others =>O <= "i(2)"; end case; end process; end behv1;

Aim: Verilog code for 2 to 1 multiplexer module mux (i, s, y); input [1:0] i; input s;

output y; reg y; always@(i or s) begin case(s) 1'b0: y = i [0]; 1'b1: y = i [1]; endcase end endmodule

Decoders
Aim: Vhdl code for 2:4 Decoder library ieee; use ieee.std_logic_1164.all; entity DECODER is port( I: O: ); end DECODER; architecture behv of DECODER is begin process (I) begin case I is when "00" => O <= "0001"; when "01" => O <= "0010"; when "10" => O <= "0100"; when "11" => O <= "1000"; when others => O <= "XXXX"; end case; in std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0)

end process; end behv; architecture when_else of DECODER is begin O <= "0001" when I = "00" else "0010" when I = "01" else "0100" when I = "10" else "1000" when I = "11" else "XXXX"; end when_else;

Aim: Verilog code 2 to 4 decoder module deco(a, en, y); input [1:0]a; input en; output [3:0]y; reg [3:0]y; begin always@(a) if(en==0) y=8'b0000; else case(a) 0:y=8'b1000; 1:y=8'b0100; 2:y=8'b0010; 3:y=8'b0001; endcase end endmodule

Aim: Vhdl code for 3:8 Decoder

library ieee; use ieee.std_logic_1164.all; entity DECODER is port( I: O: ); end DECODER; architecture behv of DECODER is begin process (I) begin case I is when "000" => O <= "00000001"; when "001" => O <= "00000010"; when "010" => O <= "00000100"; when "011" => O <= "00001000"; when "100" => O <= "00010000"; when "101" => O <= "00100000"; when "110" => O <= "01000000"; when "111" => O <= "10000000"; when others => O <= "XXXX"; end case; end process; end behv; in std_logic_vector(2 downto 0); out std_logic_vector(7 downto 0)

Aim: Verilog code 3 to 8 decoder

module deco(a,en,y); input [2:0]a; input en; output [7:0]y;

reg [7:0]y; begin always@(a) if(en==0) y=8'b00000000; else case(a) 0:y=8'b10000000; 1:y=8'b01000000; 2:y=8'b00100000; 3:y=8'b00010000; 4:y=8'b00001000; 5:y=8'b00000100; 6:y=8'b00000010; 7:y=8'b00000001; endcase end endmodule

Encoder
Aim: Vhdl code for priority encoder library ieee; use ieee.std_logic_1164.all; entity priority_encoder_1 is port ( sel : in std_logic_vector (7 downto 0); code :out std_logic_vector (2 downto 0)); end priority_encoder_1; architecture archi of priority_encoder_1 is begin code <= "000" when sel(0) = '1' else "001" when sel(1) = '1' else

"010" when sel(2) = '1' else "011" when sel(3) = '1' else "100" when sel(4) = '1' else "101" when sel(5) = '1' else "110" when sel(6) = '1' else "111" when sel(7) = '1' else "---"; end archi;

Aim: verilog code for priority encoder program:

module priorityen(w,y,z); input [3:0]w; output [1:0]y; reg [1:0]y; output z ; reg z; always @ (w) begin if(w==0) y=0; else if (w[0]==1) y=2'b00; else if (w[1]==1) y=2'b01; else if (w[2]==1) y=2'b10; else y=2'b11; if (w==0) z=1'b0; else z=1'b1; end endmodule

Aim: verilog code for 8 to 3 encoder module encoder (code,data);

output [2:0] code; input [7:0] data; reg [2:0] code; always @(data) begin if (data==8'b00000001) code=0;else if (data==8'b00000010) code=1;else if (data==8'b00000100) code=2;else if (data==8'b00001000) code=3;else if (data==8'b00010000) code=4;else if (data==8'b00100000) code=5;else if (data==8'b01000000) code=6;else if (data==8'b10000000) code=7; else code=3'bxxx; end endmodule Aim: VHDL code for 8 to 3 encoder Library ieee; Use ieee std_logic_1164.all; Use ieee std_logic arith.all; Use ieee std_logic_unsigned.all; Entity encoder8_3 is Port ( enable: in std_logic; D_in: in std_logic_vector(7 downto 0); D_out: out std_logic_vector(2 downto 0)); End encoder8_3; Architecture encoder_arch of encoder8_3 is Begin Process(enable, D_in) Begin If (enable = 1) then D_out<=000; Else Casr D_in is When 00000001 => D_out <= 000; When 00000010 => D_out <= 001; When 00000100 => D_out <= 010; When 00001000 => D_out <= 011;

When 00010000 => D_out <= 100; When 00100000 => D_out <= 101; When 01000000 => D_out <= 110; When 10000000 => D_out <= 111; When others => null; End case; End if; End process; End encoder_arch;

Comparators
Aim: vhdl code for comparator library ieee; use ieee.std_logic_1164.all; entity Comparator is generic(n: natural :=2); port( A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0); less: out std_logic; equal: out std_logic; greater: out std_logic ); end Comparator; architecture behv of Comparator is begin process(A,B) begin if (A<B) then less <= '1'; equal <= '0'; greater <= '0'; elsif (A=B) then less <= '0'; equal <= '1'; greater <= '0'; else less <= '0'; equal <= '0'; greater <= '1';

end if; end process; end behv; Aim: verilog code for comparators program module comp(a,b,a_gt_b,a_lt_b,a_eq_b); parameter bus =8; parameter eq=5,lt=8,gt=8; input [bus-1:0]a,b; output a_gt_b,a_lt_b,a_eq_b; assign a_eq_b = a==b; assign a_gt_b = a>b; assign a_lt_b = a<b ; endmodule

Flip Flops
Aim: Verilog Code For SR-Flip Flop Program: module srff( q,s,r,res,clk); input s,r,clk,res; output q; reg q; always @(negedge clk) begin if(res) q=1'b0; else if (s==0 && r==0) q=q; else if(s==0 && r==1) q=0; else if (s==1 && r==0) q=1; else q=1'bz; end endmodule Aim: Verilog Code For T-Flipflop module dff1(clk,t,q); input t,clk; output q; reg q; always @(posedge clk)

begin q<=~t; end endmodule Aim: Verilog Code For JK-Flip Flop module jkff( q,j,k,clk); input j,k,clk; output q; reg q; always @(posedge clk) begin if(j==1'b0 && k==1'b1); q=1'b0; else if (j==1'b1 && k==1'b0) q=1'b1; else if (j==1'b1 && k==1'b1) q=~q; else q=q; end endmodule Aim: VHDL Code For JK Flip-Flop library ieee; use ieee.std_logic_1164.all; entity JK_FF is port ( clock: in std_logic; J, K: in std_logic; reset: in std_logic; Q, Qbar: out std_logic ); end JK_FF; architecture behv of JK_FF is signal state: std_logic; signal input: std_logic_vector(1 downto 0); begin input <= J & K; p: process(clock, reset) is begin if (reset='1') then

state <= '0'; elsif (rising_edge(clock)) then case (input) is when "11" => state <= not state; when "10" => state <= '1'; when "01" => state <= '0'; when others => null; end case; end if; end process; Q <= state; Qbar <= not state; end behv; Aim: Verilog Code For D-Flip Flop module classicD(D, clk, Q, Qn); input D, clk; output Q, Qn; reg Q, Qn; always@(D or clk) if(clk) begin Q <= D; Qn <= ~D; end endmodule Aim: VHDL Code For D-Flip Flop library ieee ; use ieee.std_logic_1164.all; use work.all; entity dff is port( data_in: in std_logic; clock: in std_logic; data_out: out std_logic );

end dff; architecture behv of dff is begin process(data_in, clock) begin if (clock='1' and clock'event) then data_out <= data_in; end if; end process; end behv;

Counters
Aim: Verilog code for up-down counter. module counter (clk, clr, up_down, q); input clk, clr, up_down; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4'b0000; else if (up_down) tmp <= tmp + 1'b1; else tmp <= tmp - 1'b1; end assign q = tmp; endmodule Aim: Vhdl code for ring counter Library IEEE; use IEEE.std_logic_1164.all; Entity rn is port ( clk : in std_logic; reset : in std_logic; qout : out std_logic_vector(15 downto 0); wr_data : out std_logic;

wr_data1 : out std_logic ); end rn; Architecture A_rn of rn is signal qout_s : std_logic_vector(15 downto 0); signal tem_data : std_logic:='1'; begin qout <= qout_s; random_gen : process(clk) variable temp : std_logic; begin if (reset = '1') then qout_s <= "1111111111111111"; elsif (clk'event and clk = '1') then temp := tem_data; wr_data <= temp; wr_data1 <= tem_data; temp := tem_data; qout_s(0) <= qout_s(0) xor qout_s(15); for i in 15 downto 1 loop qout_s(i) <= qout_s(i - 1); end loop; end if; end process; end A_rn;

Carry Look Ahead Adder

Aim: vhdl code for carry look ahead adder library ieee; use ieee.std_logic_1164.ALL; entity c_l_addr IS port ( x_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); y_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); carry_in : IN STD_LOGIC; sum : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); carry_out : OUT STD_LOGIC

); END c_l_addr; ARCHITECTURE behavioral OF c_l_addr IS SIGNAL h_sum : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL carry_generate : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL carry_propagate : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL carry_in_interna : STD_LOGIC_VECTOR(7 DOWNTO 1); BEGIN h_sum <= x_in XOR y_in; carry_generate <= x_in AND y_in; carry_propagate <= x_in OR y_in; PROCESS (carry_generate,carry_propagate,carry_in_internal) BEGIN carry_in_internal(1) <= carry_generate(0) OR (carry_propagate(0) AND carry_in); inst: FOR i IN 1 TO 6 LOOP carry_in_internal(i+1) <= carry_generate(i) OR (carry_propagate(i) AND carry_in_internal(i)); END LOOP; carry_out <= carry_generate(7) OR (carry_propagate(7) AND carry_in_internal(7)); END PROCESS; sum(0) <= h_sum(0) XOR carry_in; sum(7 DOWNTO 1) <= h_sum(7 DOWNTO 1) XOR carry_in_internal(7 DOWNTO 1); END behavioral;

Universal Shift Register

Aim: Verilog Module Code For Universal Shift Register module Universal_shift_reg (data_out, msb_out, lsb_out, data_in, msb_in, lasb_in, s1, s0, clk, rst); output [3:0] data_out; // Hold output msb_out, lsb_out; // Serial shift from msb input [3:0] data_in; // Serial shift from lsb input msb_in, lsb_in; // Parallel load input s1, s0, clk, rst; reg data_out; assign msb_out= data_out[3]; assign lsb_out= data-out[0]; always @ (posedge clk) begin

if (rst) data_out<=0; else case ({s1, s0}) 0 : data_out <= data_out; 1 : data_out <= {msb_in, data_out[3:1]}; 2 : data_out <= {data_out[2:0], lsb_in}; 3 : data_out <= data_in; endcase end endmodule

Barrel shifter
Aim: VHDL Code Barrel shifter LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY barrel IS PORT ( inp: IN STD_LOGIC_VECTOR (7 DOWNTO 0); shift: IN STD_LOGIC_VECTOR (2 DOWNTO 0); outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END barrel; ARCHITECTURE behavior OF barrel IS BEGIN PROCESS (inp, shift) VARIABLE temp1: STD_LOGIC_VECTOR (7 DOWNTO 0); VARIABLE temp2: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN ---- 1st shifter ----IF (shift(0)='0') THEN temp1 := inp; ELSE temp1(0) := '0'; FOR i IN 1 TO inp'HIGH LOOP temp1(i) := inp(i-1); END LOOP; END IF; ---- 2nd shifter ----IF (shift(1)='0') THEN temp2 := temp1;

ELSE FOR i IN 0 TO 1 LOOP temp2(i) := '0'; END LOOP; FOR i IN 2 TO inp'HIGH LOOP temp2(i) := temp1(i-2); END LOOP; END IF; ---- 3rd shifter ----IF (shift(2)='0') THEN outp <= temp2; ELSE FOR i IN 0 TO 3 LOOP outp(i) <= '0'; END LOOP; FOR i IN 4 TO inp'HIGH LOOP outp(i) <= temp2(i-4); END LOOP; END IF; END PROCESS; END behavior;

Shift Register
Aim: Verilog code for Serial to Parallel shift register module shiftsp (clk, si, po); input clk, si; output [7:0] po; reg [7:0] tmp; always @(posedge clk) begin tmp <= {tmp[6:0], si}; end assign po = tmp; endmodule Aim: VHDL Code For Serial To Parallel Shift Register library ieee; use ieee.std_logic_1164.all;

entity shift_registers_5 is port(C, SI : in std_logic; PO : out std_logic_vector(7 downto 0)); end shift_registers_5; architecture archi of shift_registers_5 is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then tmp <= tmp(6 downto 0)& SI; end if; end process; PO <= tmp; end archi; Aim: Verilog Code For Serial To Serial Shift Register module shiftss (clk, load, si, d, so); input clk, si, load; input [7:0] d; output so; reg [7:0] tmp; always @(posedge clk or posedge load) begin if (load) tmp <= d; else tmp <= {tmp[6:0], si}; end assign so = tmp[7]; endmodule

Aim: VHDL Code For Serial To Serial Shift Register library ieee; use ieee.std_logic_1164.all; entity shift_registers_1 is port(C, SI : in std_logic; SO : out std_logic);

end shift_registers_1; architecture archi of shift_registers_1 is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then for i in 0 to 6 loop tmp(i+1) <= tmp(i); end loop; tmp(0) <= SI; end if; end process; SO <= tmp(7); end archi; Aim: Verilog Code For Parallel To Parallel Shift Register module pp (din, dout, clk, enable); parameter n = 8; input [n-1:0] din; input clk, enable; output [n-1:0] dout; reg [n-1:0] dout; reg [n-1:0] state; always@ (enable) begin if (enable) dout = state; else dout = 4'bz; end always@ (posedge clk) state <= din; endmodule

Random number generator

Aim: VHDL CODE FOR Random number generator library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity random is generic ( width : integer := 32 ); port ( clk : in std_logic; random_num : out std_logic_vector (width-1 downto 0) --output vector ); end random; architecture Behavioral of random is begin process(clk) variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0'); variable temp : std_logic := '0'; begin if(rising_edge(clk)) then temp := rand_temp(width-1) xor rand_temp(width-2); rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0); rand_temp(0) := temp; end if; random_num <= rand_temp; end process;

Memory design - ROM and RAM

Aim: VHDL Code for RAM library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity SRAM is generic( width: integer:=4; depth: integer:=4; addr: integer:=2); port( Clock: in std_logic; Enable: in std_logic; Read: in std_logic; Write: in std_logic; Read_Addr: in std_logic_vector(addr-1 downto 0);

Write_Addr: in std_logic_vector(addr-1 downto 0); Data_in: in std_logic_vector(width-1 downto 0); Data_out: out std_logic_vector(width-1 downto 0) ); end SRAM; architecture behav of SRAM is type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0); signal tmp_ram: ram_type; begin process(Clock, Read) begin if (Clock'event and Clock='1') then if Enable='1' then if Read='1' then Data_out <= tmp_ram(conv_integer(Read_Addr)); else Data_out <= (Data_out'range => 'Z'); end if; end if; end if; end process; process(Clock, Write) begin if (Clock'event and Clock='1') then if Enable='1' then if Write='1' then tmp_ram(conv_integer(Write_Addr)) <= Data_in; end if; end if; end if; end process; end behav; Aim: VHDL Code for ROM library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ROM is

port( Clock : in std_logic; Reset : in std_logic; Enable : in std_logic; Read : in std_logic; Address : in std_logic_vector(4 downto 0); Data_out: out std_logic_vector(7 downto 0) ); end ROM; architecture Behav of ROM is type ROM_Array is array (0 to 31) of std_logic_vector(7 downto 0); constant Content: ROM_Array := ( 0 => "00000001", 1 => "00000010", 2 => "00000011", 3 => "00000100", 4 => "00000101", 5 => "00000110", 6 => "00000111", 7 => "00001000", 8 => "00001001", 9 => "00001010", 10 => "00001011", 11 => "00001100", 12 => "00001101", 13 => "00001110", 14 => "00001111", OTHERS => "11111111" ); begin process(Clock, Reset, Read, Address) begin if( Reset = '1' ) then Data_out <= "ZZZZZZZZ"; elsif( Clock'event and Clock = '1' ) then if Enable = '1' then if( Read = '1' ) then Data_out <= Content(conv_integer(Address)); else Data_out <= "ZZZZZZZZ";

end if; end if; end if; end process; end Behav;

implementation using RAM

Aim: VHDL code for Stack implementation using RAM library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity stack is port( Clk : in std_logic. Enable : in std_logic; Data_In : in std_logic_vector(15 downto 0); Data_Out : out std_logic_vector(15 downto 0); . PUSH_barPOP : in std_logic; Stack_Full : out std_logic; Stack_Empty : out std_logic ); end stack; architecture Behavioral of stack is type mem_type is array (255 downto 0) of std_logic_vector(15 downto 0); signal stack_mem : mem_type := (others => (others => '0')); signal stack_ptr : integer := 255; signal full,empty : std_logic := '0'; begin Stack_Full <= full; Stack_Empty <= empty; PUSH : process(Clk,PUSH_barPOP,Enable) begin if(rising_edge(Clk)) then if (Enable = '1' and PUSH_barPOP = '1' and full = '0') then stack_mem(stack_ptr) <= Data_In; if(stack_ptr /= 0) then stack_ptr <= stack_ptr - 1; end if; if(stack_ptr = 0) then

full <= '1'; empty <= '0'; elsif(stack_ptr = 255) then full <= '0'; empty <= '1'; else full <= '0'; empty <= '0'; end if; end if; if (Enable = '1' and PUSH_barPOP = '0' and empty = '0') then if(stack_ptr /= 255) then Data_Out <= stack_mem(stack_ptr+1); stack_ptr <= stack_ptr + 1; end if; if(stack_ptr = 0) then full <= '1'; empty <= '0'; elsif(stack_ptr = 255) then full <= '0'; empty <= '1'; else full <= '0'; empty <= '0'; end if; end if; end if; end process; end Behavioral;

Digital FIR filter

Aim: VHDL code for Digital FIR filter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity DFF is port( Q : out signed(15 downto 0); --output connected to the adder

Clk :in std_logic; -- Clock input D :in signed(15 downto 0) -- Data input from the MCM block. ); end DFF; architecture Behavioral of DFF is signal qt : signed(15 downto 0) := (others => '0'); begin Q <= qt; process(Clk) begin if ( rising_edge(Clk) ) then qt <= D; end if; end process; end Behavioral;