Gii thiu cch to mi d n cho vi x l ARM Cortex-M3 STM32F103RC bng Keil ARM.

Cng vi l cch tch hp b th vin chun CMSIS ca ST dnh cho dng ARM ny. 1. B th vin CMSIS ST cung cp cho ngi dng b th vin chun lp trnh giao tip vi thit b ngoi vi tng thch vi chun CMSIS. Thng qua b th vin ny, lp trnh vin d dng giao tip vi cc thit b phn cng chun ca cc dng Cortex-M3 ca ST. Th vin c chia lm 2 phn: + phn h tr nhn Cortex-M3: bao gm m giao tip vi nhn CPU, v on m start up code. + phn h tr cc thit b ngoi vi: cha ton b cc hm th vin iu khin thit b ngoi vi ca ST. Cu trc th vin CMSIS nh sau: Code:
Library + CMSIS + CM3 + CoreSupport Cortex-M3 + DeviceSupport + ST + STM32F10X + startup + Documentation + STM32F10x_StdPeriph_Driver ngoi vi + inc + src

//th mc cha hm h tr nhn

//System startup code //Start up code //ti liu h tr //th mc cha hm h tr thit b //th mc cha header file //th mc cha m ngun

* Lu : Cc hm c vit v t tn theo chun CMSIS, lp trnh vin cn tun theo cc quy tc ca CMSIS khi s dng hm, trnh vit li cc hm truy cp thng vo phn cng khi khng cn thit. 2. Khi to d n mi + M Keil IDE, chn menu Project->New uVision Project to d n mi. Gi d t tn d n mi ny l 24h_Led. * Lu : Thng khi to project mi h thng file qun l d n ca Keil hay b tr th mc d n, iu ny d b ln ln vi cc file ngun, ta nn to mt th mc con qun l cc file d n ny. Chn chip STM32F103RC cho board GEMv0.1

Hnh 1: Khi to d n + Sau khi d n mi c to, ta nn t chc li h thng m ngun d dng theo di.

Hnh 2: T chc th mc m ngun

Nh hnh 2 trn ta to 4 nhm file, cc nhm CMSIS, StdPeriph_Driver v Start up s l cc files t th vin CMSIS ca ST. * Lu : Khi to mi d n, Keil s hi ngi dng c s dng "start up code" sn c khng. Chng ta khng s dng "start up code" ny ca Keil m s dng ca ST c trong b th vin chun. + Tch hp th vin CMSIS vo chng trnh

Chng ta s ln lt tch hp cc th mc trong th vin vo d n nh sau: + Nhm CMSIS: thm file core_cm3.c th mc \Libraries\CMSIS\CM3\CoreSupport v system_stm32f10x.c th mc \Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x + Nhm StdPeriph_Driver: thm cc file lin quan n iu khin ngoI vi, d n ny chng ta cn iu khin cng GPIO, UART nn cn thm cc file: stm32f10x_gpio.c,[B] stm32f10x_usart.c[/B] v stm32f10x_rcc.c th mc \Libraries\STM32F10x_StdPeriph_Driver\src. + Nhm Start up: thm file startup_stm32f10x_hd.s th mc Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\ startup\arm. + Nhm User: cha file ca ngi dng, gi s thm file main.c ca ta vo y.

* Lu : i vi nhm StdPeriph_Driver, nn cn c vo nhu cu iu khin ngoi vi thm vo cc file tng ng, trnh thm cc file d tha v lm tng thi gian bin dch v tn ti nguyn h thng. + Khai bo th mc th vin cho d n Sau khi thm cc file cn thit cho d n, chng ta cha th bin dch thnh cng c v cn thiu ng dn ti cc file khai bo th vin CMSIS M khung iu khin cu hnh d n

Chn tab C/C++

Thm cc ng dn th mc sau vo d n: + \Libraries: th mc cha Libraries CMSIS + \Libraries\CMSIS\CM3\CoreSupport + \Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x + \Libraries\STM32F10x_StdPeriph_Driver\inc * Lu : Ngi dng c th thm vo cc ng dn th mc khc ca d n. 3. Cu hnh project Sau khi thm cc file cn thit cho d n, chng ta phi thit lp cc thng s c bn Keil c th bin dch ra file thc thi. + np chng trnh xung board GEMv0.1, chng ta cn cu hnh Keil bin dch ra file hex(hoc bin). M khung cu hnh d n, chn tab Output, check v Create HEX File

+ tin sp xp ti nguyn ca d n, ta nn xp cc file tm c sinh ra bI Keil vo cc th mc ring

Tng ng vi cc file object(tab Output) v linker(tab Listing) ta lu trong th mc Obj v

Lst cho tin theo di sau ny. + Cn lu l vi b th vin CMSIS, chng ta s dng kh nhiu k thut macro trong lp trnh. C mt s macro cn khai bo define sn trong d n c th bin dch thnh cng.

* Lu : Nu s dng b th vin chun cho thit b ngoi vi, nn khai bo macro: USE_STDPERIPH_DRIVER. 4. Trnh din + Nu c sn board GEMv0.1, chng ta c th np trc tip file .hex sau khi bin dch xung chp thng qua Flash Downloader ca ST bng cng COM. + Nu khng c board, chng ta c th xem bng cch dng Debug Simulator ca Keil

+ Chy Debug chng trnh, m ca s theo di cc thit b ngoi vi menu Peripherals chn ngoi vi tng ng, gi s l Port C ca GPIO.

Bm F10(hoc F11) chy debug tng dng lnh ng thi theo di gi tr ca Port C thay i.