S.R.

MOS DIFFERENTIAL PAIR-1

Common Mode and differential Mode inputs
Ramesh August 16, 2008

EC o4 405 Electronics circuit 2 rameshpkd@gmail.com

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MOS DIFFERENTIAL PAIR-1

Common Mode and differential Mode inputs
The fig shows the basic MOS differential pair configuration. Q1 and Q2, matched transistors, are biased by a constant current source. Assume the current source is ideal and that it has high input impedance. 1. Operation with a Common mode input voltage; Consider the circuit below, here the two gate terminals are joined together and connected to a voltage Vg1=Vg2=Vicm. Since Q1 and Q2 are matched (1) (2) (3) That is the differential pair does not respond to a common mode input signal.
I Vcm + I/2 Vdd +V

Rd

Rd

+
Vo

Vd1
Q1

iD1

iD2
Q2

Vd2

I/2

- Vss

2. Operation with a Differential input voltage. Here we are going to consider two cases , which means that there is a 1. Let the small difference between the two inputs. In this case 2. When
Vid + I 0 Vdd +V

Rd

Rd

+
Vo

MOS DIFFERENTIAL PAIR-1 | August 16, 2008

Vd1
Q1

iD1

iD2
Q2

Vd2

From the above it is clear that the differential pair responds to difference mode or differential i/p signal between the two drains. By adjusting the value of Vid, we can make any one of the transistor causes the entire ON (OFF) and the other OFF (ON). i.e. the bias current I to flow in one of the two transistors. the id s will be { That is when corresponding o/p will be , and

- Vss

and the (4)

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rameshpkd@gmail.com Or, This property is known as current steering. (6) To use the differential pair as a linear amplifier, we keep the differential input signal very small, so that and Thus, small .i.e. when (7) (8) is } (5)

Since

(9) (10)

Ref: Sedra/Smith: Micro electronic circuits: 5th edition

By Ramesh.K rameshpkd@gmail.com

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MOS DIFFERENTIAL PAIR-1 | August 16, 2008

S.R.K

MOS DIFFERENTIAL PAIR

LARGE SIGNAL ANALYSIS
Ramesh August 14, 2008

EC o4 405 Electronics circuit 2 rameshpkd@gmail.com

www.edutalks.org

MOS DIFFERENTIAL PAIR

LARGE SIGNAL ANALYSIS
The fig shows a MOS differential pair. Here Q1 and Q2 are two matched transistors, biased by a common current source I, with identical drain resistances Rd s. Vg1 and Vg2 are two input voltages applied at the gates G1 and G2. (1) (2) Let Vid be the differential i/p voltage, (3) The drain current of a MOSFET is given by the relation (4)
Where W=the width of the Channel, L= the length of the Channel, The threshold voltage, = the process trans-conductance parameter
- Vss
+ Vg1 Rd

+V Vdd

Rd

Vo

Q1

Q2 + Vg2

Hence the currents

and

can be written as follows (5)

(6)
MOS DIFFERENTIAL PAIR | August 14, 2008

Taking square root on both side we get,

(7)

(8) (7)-(8), gives (9)

(10)

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(11) (12) (13) (14) Using (13), Squaring both sides of (15) (15)

(16)

Or,

(17)

But we have

is positive, hence

> (18)

From (18) & (13)

(19)
MOS DIFFERENTIAL PAIR | August 14, 2008

At the bias(quiescent) point Correspondingly,

(20) (21) (22) (23) (25)

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Substituting (25) in (18) and (19), (26)

(27) Normalized plots for currents in MOS Differential Pair.

0.5

-1.4

1.4

and . , and Because of the square term in the above equations of the transfer characteristics are non-linear.
,

To get a linear relation ship (or amplification) from the DP, keep
MOS DIFFERENTIAL PAIR | August 14, 2008

Small signal approximation

(28) (29) From (29), When the differential current. When a small signal
,

(30)

(31)

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where

is the signal current. Comparing,(29)and(31)

(32) (33) (34)

We have the trans-conductance, From (33) and (32)

Here the

represents the trans-conductance of the differential pair (Q1 and Q2),

(35)

This is because

divides equally between the two devices.

Ref: Micro Electronic Circuits; Sedra/Smith. 5th Edition

By Ramesh.K rameshpkd@gmail.com

www.edutalks.org

MOS DIFFERENTIAL PAIR | August 14, 2008