Module code:

module sec2(in1,in2,O,F,clk,rst_n,button_A,button_B,button_add,button_and ); input clk,rst_n,button_A,button_B,button_add,button_and; input [3:0] in1,in2; output [3:0]O; output [2:0]F;

reg [4:0] out; reg [1:0] flag; assign O=out [3:0]; assign F[1]=out[4]; assign F[0]=flag[0]; assign F[2]=flag[1]; reg [3:0] A,B;

always@(posedge clk) begin if(rst_n==0) begin A=4'd0; B=4'd0; out=5'd0; flag=3'd0; end else begin if(button_A) A=in1; if(button_B) B=in2; if(B>A) flag[1]=1; if(button_add) begin out= A+B; if( out==0) flag[0]=1; end if(button_and) begin out=A&B;

if( out==0) flag[0]=1; end

end end endmodule

Testbench code:
module secc2_test; // Inputs reg [3:0] in1; reg [3:0] in2; reg clk; reg rst_n; reg button_A; reg button_B; reg button_add; reg button_and; // Outputs wire [3:0] O; wire [2:0] F; // Instantiate the Unit Under Test (UUT) sec2 uut ( .in1(in1), .in2(in2), .O(O), .F(F), .clk(clk), .rst_n(rst_n), .button_A(button_A), .button_B(button_B), .button_add(button_add), .button_and(button_and) ); initial begin // Initialize Inputs clk=1; rst_n = 0;

# 20; rst_n = 1; in1 = 8;

button_A = 1; in2=5; button_B = 1; button_add = 0; button_and = 1; #20;

in1= 8; button_A = 1; in2=8; button_B = 1;

button_and = 0; button_add = 1; #20; $stop; // Add stimulus here end always begin #10 clk=~clk; end// Add stimulus here

// Wait 100 ns for global reset to finish

endmodule

Snapshot for add operation:

Snapshot for and operation: