1.

Classify the instruction set of IAS computer. Data Transfer, unconditional branch, conditional branch, arithmetic , address modify

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2.

A program runs on computer A in 10 seconds. A has a 4 GHz clock rate. Design a computer B that runs the same program in 6 seconds. Constraint is that a faster design is possible but will require 1.2 times as many clock cycles as A. What is Bs clock rate?

3.

List the registers of the Von Neumann architecture and explain the expanded structure of IAS computer in detail with a diagram. Set of registers (storage in CPU)

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Memory Buffer Register (MBR) Memory Address Register (MAR) Instruction Register (IR) Instruction Buffer Register (IBR) Program Counter (PC) Accumulator (AC) Multiplier Quotient (MQ)

OR Perform the 5 bit addition and subtraction of two signed binary numbers (A= -1810, B= +1010). Explain the above mentioned concept with a suitable hardware. 5 bit adder with compliment xor gates Hard ware implementation and -18+10=-8 and -1810=-18

General h/w implementation

4.

A Compiler designer is trying to decide between two code sequences for a particular computer. The hardware designers have supplied the following facts:

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For a particular high level language statement the compiler writer is considering two code sequences that require the following instruction counts.

Which code sequence executes the most instructions? Which will be faster? What is the CPI for each sequence?

The above example shows the danger of using one factor to decide the performance. It is better to use all three parameters for a performance measure
5. Explain Booths Algorithm for Twos complement multiplication of multiplicand 7 and multiplier 3 with a flow chart. [10]

6.

Brief about the Floating point representation with examples.

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