Motes 1

Problem 1: 4kB memory system

x4 1kB chips 2n = 1024 n = 10 10 address bits (A9 - A0)
4kB / 1kB = 4 chips 2x4 decoder 2 chip select bits (A11, A10)
Remaining 4 bits (2 bits each) for chip decoder enables E1 and ~E2 (A15, A14, A13, A12)
A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0
Chip
1
2
3
4

Address range (hex)

$4000 - $43FF
$4400 - $47FF
$4800 - $4BFF
$4C00 - $4FFF

Instruction
ldaa $4B03
staa $4400
ldaa $5000

Chip
3
2
n/a

Address range (binary)

0100 0000 0000 0000 0100 0011 1111 1111
0100 0100 0000 0000 0100 0111 1111 1111
0100 1000 0000 0000 0100 1011 1111 1111
0100 1100 0000 0000 0100 1111 1111 1111

E1
1
1
1

E2
0
0
1

WE
0
1
0

RE
1
0
1

R/W
1
0
1

Chip select instruction

00
01
10
11

Motes 2
Problem 2: 12kB memory system
x3 4kB chips 2n = 4096 n = 12 12 address bits (A11 - A0)
12kB / 4kB = 3 chips 2x4 decoder 2 chip select bits (A13, A12)
Remaining 2 bits for chip decoder enables E1 and ~E2 (A15, A14)
A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0
Chip
n/a
1
2
3

Address range (hex)

$9000 - $9FFF
$A000 - $AFFF
$B000 - $BFFF

Instruction
ldaa $A001
staa $BF00

Chip
2
3

Address range (binary)

1001 0000 0000 0000 1001 1111 1111 1111
1010 1000 0000 0000 1010 1011 1111 1111
1011 1100 0000 0000 1011 1111 1111 1111

E1
1
1

E2
0
0

WE
0
1

RE
1
0

R/W
1
0

Chip select instruction

00
01
10
11