PHN MM THIT K QUARTUS II. 3.1 Gii thiu phn mm Quartus II.

Quartus II l cng c phn mm pht trin ca hng Altera, cung cp mi trng thit k ton din cho cc thit k SOPC (h thng trn 1 chip kh trnh - system on a programmable chip). y l phn mm ng gi tch hp y phc v cho thit k logic vi cc linh kin logic kh trnh PLD ca Altera, gm cc dng APEX, Cyclone, FLEX, MAX, Stratix... Quartus cung cp cc kh nng thit k logic sau: Mi trng thit k gm cc bn v, s khi, cng c son tho cc ngn ng: AHDL, VHDL, v Verilog HDL. Thit k LogicLock. L cng c mnh tng hp logic. Kh nng m phng chc nng v thi gian. Phn tch thi gian.
Phn tch logic nhng vi cng c phn tch SignalTap@ II.

Cho php xut, to v kt ni cc file ngun to ra cc file chng trnh. T ng nh v li. Kh nng lp trnh v nhn din linh kin. Phn mm Quartus II s dng b tch hp NativeLink @ vi cc cng c thit k cung cp vic truyn thng tin lin mch gia Quartus vi cc cng c thit k phn cng EDA khc. Quartus II cng c th c cc file mch (netlist) EDIF chun, VHDL v Verilog HDL cng nh to ra cc file netlist ny. Quartus II c mi trng thit k ha gip nh thit k d dng vit m, bin dch, sot li, m phng... Vi Quartus c th kt hp nhiu kiu file trong 1 d n thit k phn cp. C th dng b cng c to s khi (Quartus Block Editor) to ra s khi m t thit k mc cao, sau dng cc s khi khc, cc bn v nh: AHDL Text Design Files (.tdf), EDIF Input Files (.edf), VHDL Design Files (.vhd), and Verilog HDL Design Files (.v) to ra thnh phn thit k mc thp.

Quartus II cho php lm vic vi nhiu file cng thi im, son tho file thit k trong khi vn c th bin dch hay chy m phng cc d n khc. Cng c bin dch Quartus II nm trung tm h thng, cung cp quy trnh thit k mnh cho php ty bin t c thit k ti u trong d n. Cng c nh v li t ng v cc bn tin cnh bo khin vic pht hin v sa li tr nn n gin hn. Sau khi ci Quartus II, giao din nh hnh v:

Hnh v. Giao din Quartus II. 3.2 Thit k mch. Mnh in trong Quartus c th c thit k theo cc cch sau: 3.2.1/ S khi (Block Diagram). Trong cch m t ny, mch in to nn t cc cng logic ri rc, hay cc hm gm nhiu cng logic tch hp (megafunctions). v mch theo cch ny, nhn New, chn tab Device Design Files, chn Block Diagram/ Schematic File, hin:

Hnh v

Cc cng c v mch

Ca s v

Hnh v. Giao din Block Editor Nhn chn Symbol Tool hin cc cng logic hay cc hm Megafuntions

Cc cng logic hay hm

Vng hin th cng logic hay hm

Hnh v. Cc cng logic, cc hm. Khi chn xong cc cng logic hay hm th dng cc cng c ni dy v mch hon chnh. 3.2.2 Cc file thit k. Nhn New, chn tab Device Design Files, chn Verilog HDL (hay VHDL hay AHDL). Vi cch ny, mch in c m t bi cc on m th hin

cc u vo u ra ca cc khi mch cng nh cch x s ca chng. Trong lun n ny, ly v d v thit k mch m 4 bit dng Verilog HDL file. To file mi. T giao din ca Altera Quartus chn File/New Project Wizard. Hin:

Tn th mc s cha D n Tn D n Tn ca thit k trong D n

Hnh v. Giao din D n mi Nhn Next/Next hin ra bng Thit lp linh kin (Family & Device Settings), chn linh kin FPGA m ta dng, ri nhn Finish. Lc ny, ta s c c Project u tin.

Thm file Thit k vo Project Nhn File/New .

Hnh v Giao din file thit k mi. to ra file thit k cho D n, ta c th dng s khi (nhn Block Diagram/Schematic File) hay dng mt trong cc ngn ng m t phn cng nh: AHDL, Verilog HDL hay VHDL hoc c th dng kiu EDIF. y, chn dng ngn ng Verilog HDL. B m nh phn 4 bit. Mt b m nh phn 4 bt gm 2 u vo: u vo xung m (clock), u vo xa b m v 0 (clear) v 4 u ra nh phn Q0, Q1, Q2, Q3.

Hnh v. S mch b m nh phn 4bit.

on m dng Verilog m t b m trn nh sau:

//4-bit Binary counter module counter(Q , clock, clear); // I/O ports output [3:0] Q; input clock, clear; //output defined as register reg [3:0] Q; always @( posedge clear or negedge clock) begin if (clear) Q <= 4'd0; //Nonblocking assignments are recommended //for creating sequential logic such as flipflops else Q <= Q + 1;// Modulo 16 is not necessary because Q is a // 4-bit value and wraps around. end endmodule

Dng b son tho sn c ca Quartus a on m ny vo file Verilog va to ra, ri Save vi tn ph hp.

Hnh v. File thit k dem4bit.v th hin bng ngn ng Verilog.

Dng on m mu ca Verilog. Quartus to sn mt s on m Verilog mu h tr ngi thit k. Chn Edit/Insert Template/ Verilog HDL. C kh nhiu khi c m t sn bng Verilog nh: b m, ghi dch, b cng, cc khi nh RAM, ROM... y cng l cch ngi dng c th hc thm v ngn ng Verilog. Bin dch. bin dch File nhn Processing/Start Compilation. Quartus s bin dch file dem4bit.v. Sau khi hon thnh, hin thng bo. Full Compilation was successful (Bin dch thnh cng). Bin dch gm 4 qu trnh thnh phn: Phn tch v tng hp (Analysis & Synthesis) Qu trnh ny s xem xt thit k logic to ra c s d liu thit k, thc hin tng hp logic v ti u ha thit k. Fitter (cn i yu cu v ti nguyn) Qu trnh ny c xem nh l t v tr (cng logic) v nh tuyn (gia chng) - Place and Router. S dng c s d liu c to ra bi qu trnh phn tch v tng hp, cng c Fitter s cn i gia cc yu cu v thi gian, logic ca D n thit k vi cc ti nguyn kh dng ca linh kin. N s n nh mi hm logic n mt n v logic m ti u nht v thi gian truyn v nh tuyn cng nh la chn ng ni ph hp v gn chn linh kin. Assembler. (hp dch) Qu trnh hp dch da vo kt qu ca qu trnh Fitter s to ra hnh nh ca thit k, c th trong cc dng sau: Programmer Object Files (.pof), SRAM Object Files (.sof), Hexadecimal (Intel-Format) Output Files (.hexout), Tabular Text Files (.ttf), and Raw Binary Files (.rbf), Classic Timing Analyzer (Phn tch thi gian). Phn tch thi gian cho php xc nh xung nhp, cc yu cu v thi gian vo/ra (I/O) nhm tha mn mc ch nh thi. Qu trnh ny s xc nh tnh nng tc cho ton b D n, cho tng khi thit k v cho vic truyn, nhn ca cc nt v chn linh kin.

Hnh v. Giao din khi bin dch v thng bo Bin dch thnh cng 3.3 Cch thc m phng hot ng trong Quartus. Cng c Simulator tch hp sn trong Quartus II cho php m phng hot ng ca D n (Project). Trc khi m phng cn to ra danh sch ng kt ni (netlist) bi vic nhn Processing/Generate Functional Simulation Netlist. c th quan st c dng sng m phng, cn to ra file khc lu tr dng sng, bi vic chn File/New/Other Files/Vector Waveform File. thm cc tn hiu vo/ra cho Vector Waveform File, chn Edit/ Insert Node or Bus, nhn Node Finder.

Hnh v. Giao din Node Finder Trong danh sch trn, chn 2 u vo Clear, Clock v u ra Q, nhy p vo cc tn hiu . Cc tn hiu ny s hin ra trong danh sch Selected Nodes. Nhn OK. n nh dng sng cho 2 tn hiu vo l Clock v Clear, nh du chn vo dng sng, trn thanh WaveForm Editor chn Overwrite Clock, hin :

Hnh v Giao din Clock n nh dng sng.

Time Range chnh l khong thi gian mun quan st dng sng. Chu k ca tn hiu cho trong Period, rng xung trong Duty Cycle.

Overwrite Clock Hnh v. Giao din Waveform File. C 2 kiu m phng trong Quartus l Functional v Timing. Vi kiu Functional, ch kim tra hot ng thun ty logic, cn vi m phng Timing, kim tra hot ng logic c tnh n yu t thi gian, nh: tr, qu ... chy m phng, chn Processing/Start Simulation.

Hnh v. Dng sng sau khi m phng Functional.