Methode 1 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.

all; entity compteur_bcd is port(clk: in std_logic; q:out std_logic_vector(3 downto 0)); end compteur_bcd; architecture comp of compteur_bcd is signal N : std_logic_vector(3 downto 0):="0000"; begin process(clk) begin if clk' event and clk = '0' then if N= "1001" then N<="0000"; else N <= N+1; end if; end if; end process ; q<=N; end comp;