• High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 32K Bytes of In-System Self-programmable Flash program memory – 1024 Bytes EEPROM – 2K Byte Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC • 8 Single-ended Channels • 7 Differential Channels in TQFP Package Only • 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF Operating Voltages – 2.7 - 5.5V for ATmega32A Speed Grades – 0 - 16 MHz for ATmega32A Power Consumption at 1 MHz, 3V, 25°C for ATmega32A – Active: 0.6 mA – Idle Mode: 0.2 mA – Power-down Mode: < 1 µA
8-bit Microcontroller with 32K Bytes In-System Programmable Flash ATmega32A Summary
• • • •
1. Pin Configurations
PD3 PD4 PD5 PD6 PD7 VCC GND (SCL) PC0 (SDA) PC1 (TCK) PC2 (TMS) PC3
. Pinout ATmega32A
(XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) PC3 (TMS) PC2 (TCK) PC1 (SDA) PC0 (SCL) PD7 (OC2)
PB4 (SS) PB3 (AIN1/OC0) PB2 (AIN0/INT2) PB1 (T1) PB0 (XCK/T0) GND VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3)
(MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2
PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO)
(INT1) (OC1B) (OC1A) (ICP1) (OC2)
Note: Bottom pad should be soldered to ground.
By executing powerful instructions in a single clock cycle.1
Figure 2-1. & TIMING RESET
INTERNAL CALIBRATED OSCILLATOR
COMP. the ATmega32A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.PA7 PC0 .PB7
PORTA DIGITAL INTERFACE
PORTC DIGITAL INTERFACE
MUX & ADC
AREF PROGRAM COUNTER
INTERNAL OSCILLATOR XTAL1
GENERAL PURPOSE REGISTERS X
XTAL2 MCU CTRL.
The ATmega32A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. INTERFACE
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
if the A/D Converter is not used. the Asynchronous Timer continues to run. or by an On-chip Boot program running on the AVR core.3
Port A (PA7:PA0) Port A serves as the analog inputs to the A/D Converter. Port pins can provide internal pull-up resistors (selected for each bit). This allows very fast start-up combined with low-power consumption.2
2. The device is manufactured using Atmel’s high density nonvolatile memory technology. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC.
2. The boot program can use any interface to download the application program in the Application Flash memory. The Idle mode stops the CPU while allowing the USART. the Atmel ATmega32A is a powerful microcontroller that provides a highly-flexible and costeffective solution to many embedded control applications. allowing the user to maintain a timer base while the rest of the device is sleeping. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU). and six software selectable power saving modes.1
VCC Digital supply voltage.2. In Power-save mode. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Power-down mode saves the register contents but freezes the Oscillator. SPI port. an 8-channel. allowing two independent registers to be accessed in one single instruction executed in one clock cycle. SRAM. disabling all other chip functions until the next External Interrupt or Hardware Reset. macro assemblers. In Standby mode. 2K byte SRAM. In Extended Standby mode. Port A also serves as an 8-bit bi-directional I/O port. The ATmega32A AVR is supported with a full suite of program and system development tools including: C compilers. program debugger/simulators. 10-bit ADC with optional differential input stage with programmable gain (TQFP package only).2
GND Ground. a JTAG interface for Boundaryscan. Timer/Counters. and interrupt system to continue functioning. a programmable Watchdog Timer with Internal Oscillator. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface. a serial programmable USART. both the main Oscillator and the Asynchronous Timer continue to run. 1024 bytes EEPROM. Two-wire interface. The Port A output buffers have sym4
. the crystal/resonator Oscillator is running while the rest of the device is sleeping. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip. in-circuit emulators. three flexible Timer/Counters with compare modes. providing true Read-While-Write operation. an SPI serial port.2. by a conventional nonvolatile memory programmer.ATmega32A
The AVR core combines a rich instruction set with 32 general purpose working registers. A/D Converter.
2. 32 general purpose I/O lines. a byte oriented Two-wire Serial Interface. Software in the Boot Flash section will continue to run while the Application Flash section is updated. Internal and External Interrupts.
2. 32 general purpose working registers.2. The ATmega32A provides the following features: 32K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities. to minimize switching noise during ADC conversions. and evaluation kits. On-chip Debugging support and programming.
2. As inputs. 2.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). Port D also serves the functions of various special features of the ATmega32A as listed on page 64. 2.2. even if the clock is not running. The Port A pins are tri-stated when a reset condition becomes active. Port C pins that are externally pulled low will source current if the pull-up resistors are activated.
metrical drive characteristics with both high sink and source capability. If the JTAG interface is enabled. The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. even if the clock is not running. 2. Port B pins that are externally pulled low will source current if the pull-up resistors are activated.4 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). 2. As inputs.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. The TD0 pin is tri-stated unless TAP states that shift out data are entered.7 RESET Reset Input. Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port B also serves the functions of various special features of the ATmega32A as listed on page 59. the pull-up resistors on pins PC5(TDI). The Port C pins are tri-stated when a reset condition becomes active. they will source current if the internal pull-up resistors are activated.2. The Port D pins are tri-stated when a reset condition becomes active. even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.2. A low level on this pin for longer than the minimum pulse length will generate a reset. When pins PA0 to PA7 are used as inputs and are externally pulled low. Port C also serves the functions of the JTAG interface and other special features of the ATmega32A as listed on page 62.2.9 XTAL2 Output from the inverting Oscillator amplifier. PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. As inputs. 2. even if the clock is not running. even if the clock is not running. The minimum pulse length is given in Table 27-1 on page 299. The Port C output buffers have symmetrical drive characteristics with both high sink and source capability.8 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.2. The Port B pins are tri-stated when a reset condition becomes active.
A comprehensive set of development tools.10 AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. even if the ADC is not used.
Note: 1. 2.11 AREF AREF is the analog reference pin for the A/D Converter.com/avr.atmel.2. It should be externally connected to VCC. application notes and datasheets are available for download on http://www. it should be connected to VCC through a low-pass filter.2.
3. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. If the ADC is used.ATmega32A
226 112 114 116 116 116 116 116 116 116 116
Timer/Counter1 – Counter Register High Byte Timer/Counter1 – Counter Register Low Byte Timer/Counter1 – Output Compare Register A High Byte Timer/Counter1 – Output Compare Register A Low Byte Timer/Counter1 – Output Compare Register B High Byte Timer/Counter1 – Output Compare Register B Low Byte Timer/Counter1 – Input Capture Register High Byte Timer/Counter1 – Input Capture Register Low Byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register – – URSEL URSEL – – – – UMSEL – – – – UPM1 – – WDTOE – UPM0 – USBS – – AS2 WDE TCN2UB WDP2 UCSZ1 OCR2UB WDP1 UBRR[11:8] UCSZ0 EEAR9 UCPOL EEAR8 TCR2UB WDP0
132 135 135 135 43 171 170 20 20 21
EEPROM Address Register Low Byte EEPROM Data Register – PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPI Data Register SPIF SPIE RXC RXCIE ACD REFS1 ADEN WCOL SPE TXC TXCIE ACBG REFS0 ADSC – DORD UDRE UDRIE ACO ADLAR ADATE – MSTR FE RXEN ACI MUX4 ADIF – CPOL DOR TXEN ACIE MUX3 ADIE – CPHA PE UCSZ2 ACIC MUX2 ADPS2 – SPR1 U2X RXB8 ACIS1 MUX1 ADPS1 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0 – PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 – PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 – PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0
21 66 66 66 67 67 67 67 67 67 67 67 68 145 145 143 167 168 169 171 206 222 224 225 225 203
USART I/O Data Register
USART Baud Rate Register Low Byte
ADC Data Register High Byte ADC Data Register Low Byte Two-wire Serial Interface Data Register TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
. 117.137. 69 42. 136 264 202 36. 251 84 86 32 232
SP7 SP6 SP5 Timer/Counter0 Output Compare Register INT1 INTF1 OCIE2 OCF2 SPMIE TWINT SE JTD FOC0 INT0 INTF0 TOIE2 TOV2 RWWSB TWEA SM2 ISC2 WGM00 INT2 INTF2 TICIE1 ICF1 – TWSTA SM1 – COM01
Timer/Counter0 (8 Bits) Oscillator Calibration Register On-Chip Debug Register ADTS2 COM1A1 ICNC1 ADTS1 COM1A0 ICES1 ADTS0 COM1B1 – – COM1B0 WGM13 ACME FOC1A WGM12 PUD FOC1B CS12 PSR2 WGM11 CS11 PSR10 WGM10 CS10
66. 136 87.ATmega32A
5. 71 71 87. Register Summary
$3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31(1) ($51)(1) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20(2) ($40)(2) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22)
SREG SPH SPL OCR0 GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL OCDR SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR ADMUX ADCSRA ADCH ADCL TWDR TWAR
S – SP4 – – OCIE1A OCF1A RWWSRE TWSTO SM0 JTRF COM00
V SP11 SP3 – – OCIE1B OCF1B BLBSET TWWC ISC11 WDRF WGM01
N SP10 SP2 – – TOIE1 TOV1 PGWRT TWEN ISC10 BORF CS02
Z SP9 SP1 IVSEL – OCIE0 OCF0 PGERS – ISC01 EXTRF CS01
C SP8 SP0 IVCE – TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00
8 11 11 86 48.90. 117. 70.206.
For compatibility with future devices. Note that the CBI and SBI instructions will operate on all bits in the I/O Register. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. the OSCCAL Register is always accessed on this address. Reserved I/O memory addresses should never be written.ATmega32A
$01 ($21) $00 ($20)
Two-wire Serial Interface Bit Rate Register
1. 3. thus clearing the flag.
. When the OCDEN Fuse is unprogrammed. reserved bits should be written to zero if accessed. Some of the Status Flags are cleared by writing a logical one to them. writing a one back into any flag read as set. The CBI and SBI instructions work with registers $00 to $1F only. 4. Refer to the USART description for details on how to access UBRRH and UCSRC.
S Z.V Z.V.C Z. Instruction Set Summary
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS Rd.N.V None Z.N.C.C.V. K Rdl.V Z.V Z.C.N.K Rd.K Rd ← Rd .N.Rr Rd.H Z. b s.V Z.C. Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set
Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd .V.K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← $FF − Rd Rd ← $00 − Rd Rd ← Rd v K Rd ← Rd • ($FF .N.V Z.V.Rr Rd ← Rd .V.C.V Z.C Z. N.Rr .N.C.Rr Rd.V Z.K Rd Rd Rd Rd Rd Rd.N.C.V Z.C Z. Rr Rdl. Rr Rd Rd Rd.C.N.C.N.H Z.K Rd. Rr Rd.C Z.N.ATmega32A
6. b P. Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal. Rr Rd.V.V. Rr Rd. Rr Rd. k k k k k k k k k k k k k k k k k
Rd.N.V Z.H Z.C None None None None None None None I None Z. b Rr. Rr Rd.N.N. N.V.C.H Z.H None None None None None None None None None None None None None None None None None None None
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS
1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1
PC ← PC + k + 1 PC ← Z PC ← k PC ← PC + k + 1 PC ← Z PC ← k PC ← Stack PC ← Stack if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1
R1:R0 ← (Rd x Rr) <<
.K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← $FF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr
Z. Rr Rd.V.K Rd. K Rd.C.H Z.C Rd ← Rd . K Rd. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare. b P.N.N.V.Rr Rd.V Z. Rr Rd. K Rd.S Z. Rr Rd.V Z. k s.N.H Z.H Z. N.V.N.N. Signed Branch if Less Than Zero.H Z. Rr Rd.C Z.C.N.K Rr.V.C.K . Rr k
Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg.N.N. Rr Rd.H Z.C Rdh:Rdl ← Rdh:Rdl .
Y+q Rd.b Rd Rd Rd Rd Rd Rd s s Rr.ATmega32A
BRTC BRVS BRVC BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV Rd. Rr Rd.C←Rd(0) Rd(n) ← Rd(n+1). b Rd.C. Rd ← (X) Rd ← (Y) Rd ← (Y).Y Rd. . Rr
Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Store Indirect and Pre-Dec. Rr Y+q. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. X ← X + 1 X ← X . b Rd. Z ← Z+1 Z ← Z . Load Indirect and Pre-Dec. n=0:6 Rd(3:0)←Rd(7:4).N. (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr. Store Indirect Store Indirect and Post-Inc. X Rd. K Rd. Rr Z+q. Rd(0) ← 0 Rd(n) ← Rd(n+1). Z+
k k k k k Rd. Z ← Z+1 (Z) ← R1:R0 Rd ← P P ← Rr Stack ← Rr Rd ← Stack I/O(P. Load Indirect and Pre-Dec. Rr .N. Y+ Rd.Rr k.1.Rd(7:4)←Rd(3:0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z.Rd(n)← Rd(n+1). X+ Rd.N. Z Rd.b P.C←Rd(7) Rd(7)←C. k X.Rr Z.V None SREG(s) SREG(s) T None C C N N Z Z I I S S V
1/2 1/2 1/2 1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATA TRANSFER INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
Clear Twos Complement Overflow
.b) ← 0 Rd(n+1) ← Rd(n). Z ← Z + 1 Z ← Z . P P. Rr X+. Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z). Rr . Rd(7) ← 0 Rd(0)←C.
if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X).V Z.1. Load Indirect and Pre-Dec. Z Rd. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Rr -Z. Store Indirect and Pre-Dec. X ← X + 1 X ← X .X Rd.X. Load Indirect Load Indirect and Post-Inc.1. Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr. Rr Y+.Y.N.1. Y Rd. Rr Rd.V Z. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Rr Y. Rr Z+. Y ← Y + 1 Y ← Y . Z+q Rd.V Z.C. (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z).b) ← 1 I/O(P.C. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc.V Z. Z+ Rd.C.C.1.N.1.Rd(n+1)← Rd(n). (X) ← Rr (Y) ← Rr (Y) ← Rr. -Z Rd. . Rr Rr Rd P. Y ← Y + 1 Y ← Y .
Mnemonics Operands Description
Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset Break
T←1 T←0 H←1 H←0
T T H H None None None None
1 1 1 1 1 1 1 N/A
SET CLT SEH CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK
(see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-Chip Debug Only
This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Also Halide free and fully Green.ATmega32A
7. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). 7 x 7 x 1.0 mm.5V Ordering Code ATmega32A-AU ATmega32A-PU(2) ATmega32A-MU(2)
Package(1) 44A 40P6 44M1
Operational Range Industrial (-40oC to 85oC)
1.7 .600” Wide. 10 x 10 x 1. Plastic Dual Inline Package (PDIP) 44-pad.0 mm.5.
Package Type 44A 40P6 44M1 44-lead. Thin Profile Plastic Quad Flat Package (TQFP) 40-pin. 2. Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
. 0. Ordering Information
Speed (MHz) 16 Power Supply 2.
25 mm per side. This package conforms to JEDEC reference MS-026.00 – – – 0. Variation ACB.75 9.20 0. 10 x 10 mm Body Size.00 10.ATmega32A
8. Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO.05 0.09 0.15 1. 44A REV. 1. B
.30 0. Lead coplanarity is 0.05 12. CA 95131 TITLE 44A.95 11.20 0.1 44A
PIN 1 B
PIN 1 IDENTIFIER
D1 D C
0˚~7˚ A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN – 0.00 12.25 10. 2.10 12.00 10.45 0. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.10 mm maximum. 3.90 0.8 mm Lead Pitch.80 TYP MAX 1.90 11.00 12.0 mm Body Thickness.25 10. Allowable protrusion is 0. Dimensions D1 and E1 do not include mold protrusion.10 0.75 9.75 Note 2 Note 2 NOTE
1.45 NOM – – 1. 44-lead. 0.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose. Packaging Information
L B1 e E B
0º ~ 15º
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0. 40-lead (0.970 0. This package conforms to JEDEC reference MS-011.600"/15. 40P6 REV.ATmega32A
8.540 TYP MAX 4.826 – 52.
B1 L C eB e
09/28/01 2325 Orchard Parkway San Jose.578 15. Variation AC.462 0.875 13. Mold Flash or Protrusion shall not exceed 0.070 15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO.203 15.559 1. B
.356 1. 2.651 3.526 Note 2 Note 2 NOTE
1.381 17.048 0. CA 95131 TITLE 40P6.25 mm (0.240 13.556 0.010").381 52. Dimensions D and E1 do not include mold Flash or Protrusion.494 NOM – – – – – – – – – – 2.041 3.
90 5. Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) GPC ZWS DRAWING NO.3 44M1
Marked Pin# 1 ID
K L D2
Pin #1 Corner
1 2 3
Pin #1 Triangle
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.0 mm Body.41 0.00 5.20 7.20 REF 0.10 5.20 0. 44M1 REV.50 mm.69 0. 44-pad. H
.23 7.00 0.05 NOTE
Pin #1 Chamfer (C 0.com TITLE 44M1.90 0.00 6.90 5. 5.
9/26/08 Package Drawing Contact: email@example.com MAX 1. 7 x 7 x 1.50 BSC 0.64 0.59 0.00 5. Lead Pitch 0.30 7.80 – NOM 0.20 mm Exposed Pad.20 0.10 5.40 7.02 0.26 0. Fig. 1 (SAW Singulation) VKKD-3.18 6.30)
A A1 A3 b D
K b e
Pin #1 Notch (0.20 R)
D2 E E2 e L
Note: JEDEC Standard MO-220.ATmega32A
Problem Fix/Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx). Errata
9. – If the Device IDs of all devices in the boundary scan chain must be captured simultaneously. rev. 3. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. or asynchronous Output Compare Register (OCRx). G to rev. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR. 2. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC. – Select the Device ID Register of the ATmega32A by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. I
• • • •
First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Problem Fix / Workaround – If ATmega32A is the only device in the scan chain. Data to succeeding devices are replaced by all-ones during Update-DR.
. asynchronous Timer Counter Register (TCNTx). Problem Fix/Workaround When the device has been powered or reset. Issue the BYPASS instruction to the ATmega32A while reading the Device ID Registers of preceding devices of the boundary scan chain. the ATmega32A must be the fist device in the chain.1 ATmega32A.ATmega32A
9. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. the first Analog Comparator conversion will take longer than expected on some devices. 4.
1. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. disable then enable theAnalog Comparator before the first conversion. the problem is not visible. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly.
Test limits of Reset Pull-up Resistor (RRST) in “DC Characteristics” on page 296.
10. 8155A – 06/08
1. .New graphs in “Typical Characteristics” on page 306. .New “Ordering Information” on page 339. 2. .
Updated “Errata” on page 343. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document.Updated description in “Stack Pointer” on page 11. 8155B – 07/09
Rev. . Updated the last page with Atmel’s new addresses.
Initial revision (Based on the ATmega32/L datasheet 2503N-AVR-06/08) Changes done compared ATmega32/L datasheet 2503N-AVR-06/08: . . The referring revision in this section are referring to the document revision.All Electrical characteristics is moved to “Electrical Characteristics” on page 296.Register descriptions are moved to sub sections at the end of each chapter.ATmega32A
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