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MC LC
LI NI U............................................................................................................................3
Phn I: TNG QUAN V H VI IU KHIN 8051............................................................5
1. GII THIU CHUNG V H 8051............................................................................5
2. GII THIU CHUNG V AT89S52............................................................................7
2.2. S chn v chc nng cc chn ca h 8051................................................9
PHN II: NI DUNG THIT K.......................................................................................26
Chng I: GII THIU CC MODUL V CC LINH KIN DNG TRONG MCH.
...............................................................................................................................................26
2.1 Cng ni tip (COM)...........................................................................................27
2.2. IC MAX232..........................................................................................................28
4.2 LED MATRIX 8X8..............................................................................................33
Phn 2: NI DUNG THIT K..............................................................................................52
DANH MC K HIU, CH VIT TT.

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ROM: Read Only Memory.
RAM : Random Access Memory.
- SRAM: Static Random Access Memory.

-
EEPROM: Electrically Erasable Programmable Read-Only Memory.
CPU: Central Processing Unit.
- ALU : Arithmetic Logical Unit.

-
PSW: Program Status Worl.
UART: Universal Ansynchrous Receiver and Transmitter.
WDM: Watch Dog Timer .
RTC: Real Time Clock.
- ISP: In System Programmer.
DANH MC HNH V.
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Hnh 1.1.1: S khi ca h 8051...........................................................................................8

Hnh 1.1 .2: S chn ca h 8051.......................................................................................11
Hnh 1.1.3: Cu trc Port 0.......................................................................................................12
Hnh 1.1.4: Cu trc Port 1.......................................................................................................12
Hnh 1.1.5: Cu trc Port 2.......................................................................................................13
Hnh 1.1.6 : Cu trc Port 3......................................................................................................13
Hnh 1.1.7 Hot ng ca Timer0 v Timer1 ch 0.......................................................19
Hnh 1.1.10 Hot ng ca Timer0 ch 3........................................................................22
Hnh 1.2.1 : S d khi ngun..................................................................................................26
Hnh 1.2.2 S khi ghp ni vi my tnh qua cng ni tip.............................................27
Hnh 1.2.3 S chn ca cng COM......................................................................................28
Hnh 1.2. 4 S chn v hnh nh thc t ca MAX 232....................................................29
Hnh 1.2.5 S khi vi iu khin.........................................................................................30
Hnh 1.2.6: S mch to dao ng ca 8051......................................................................30
Hnh 1.2.7: S mch reset ca 8051....................................................................................31
Hnh 1.2.8 S khi qut led matrix....................................................................................32
Hnh 1.2.9: S chn v hnh nh thc t ca IC 74HC595.................................................33
Hinh 1.2.10: S chn v hnh nh thc t ca Led Matrix 8x8..........................................34
Hnh 1.2.11 S khi giao tip LCD.....................................................................................35
Hnh 1.2.12: Hnh nh LCD.....................................................................................................36
Hnh 1.2.13 S khi chuyn i A/D..................................................................................38
Hnh 1.2.14 S chn v hnh nh thc t ca IC ADC 0804..............................................39
Hnh 1.2.15 S khi hin th thi gian thc........................................................................42
Hnh 1.2.16: S chn v hnh nh thc t ca DS1307......................................................42
Hnh 1.2.17: S khi ngt hng ngoi................................................................................43
Hnh 1.2.18 S chn ca OPTO.........................................................................................44
Hnh 1.2.19: S chn v hnh nh thc t ca LM358.......................................................44
Hnh 1.2.20 S khi qut led 7 on...................................................................................47
Hnh 1.2.21. Hnh nh thc t ca led qut 4..........................................................................47
Hnh 1.2.22. S chn ca led quet 4....................................................................................48
Hnh 1.2.23 S khi qut led n........................................................................................49
Hnh 1.2.24. Khi ghp ni ma trn phm 4x4.........................................................................49
Hnh 1.2.25. S khi iu khin ng c mt chiu.........................................................50
Hnh 1.2.26: S mch cu H...............................................................................................51
Hnh 1.2.27. S khi np chng trnh theo chun ISP.....................................................51
Hnh 2.1.1 : S mch nguyn l..........................................................................................53
LI NI U.
Ngy nay k thut vi iu khin tr nn quen thuc trong cc ngnh
k thut v trong dn dng. T cc dy truyn sn xut ln n cc thit b
gia dng chng ta u thy s hin din ca vi iu khin ( VK ). Cc b
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VK c kh nng x l nhiu hot ng phc tp m ch cn mt chip vi

mch nh, n thay th cc t iu khin ln v phc tp bng nhng mch
in gn nh, d dng thao tc s dng. VK khng nhng gp phn vo k
thut iu khin m cn gp phn to ln vo pht trin thng tin. l s ra
i ca hng lot thit b vin thng v truyn hnh hin i, c bit s ra i
ca mng internet gp phn a con ngi ln nh cao ca nn vn minh
nhn loi.
Chnh v cc l do trn, vic tm hiu kho st VK l iu m cc sinh
vin ngnh in t chng em ht sc quan tm . Cc b iu khin s dng
VK tuy n gin nhng vn hnh v s dng c li l mt iu rt
phc tp. Phn cng vic s l chnh vn l con ngi chnh l chng
trnh hay phn mm. Tuy chng ta thy cc my tnh ngy nay cc k thng
minh, gii quyt cc bi ton phc tp trong vi phn triu giy nhng
cng u l da trn s hiu bit ca con ngi. Nu khng c s tham gia
ca con ngi th h thng VK cng ch l mt vt v tri. Do vy khi ni
n VK cng nh my tnh bao gm phn cng v phn mm.
Cc b VK theo thi gian cng pht trin rt nhanh cng vi cng
ngh bn dn, t cc b VK 4 bit n gin ti cc b VK 32 bit. B VK
8 bit l c s chng ta tm hiu v s dng cc b VK ti tn hn, y
chnh l bc u tin chng ta tm hiu su vo lnh vc ny.
tm hiu b VK mt cch khoa hc v mang li hiu qu cao lm
nn tng cho vic xm nhp cng ngh ti tn hn. Vic trang b nhng kin
thc v VK cho sinh vin l ht sc cn thit. Xut pht t thc t ny em
quyt nh thc hin ti Thit k b KIT thc hnh vi iu khin
8051.
ti ca em gm 3 phn:
Phn I: TNG QUAN V H VI IU KHIN.
Phn II: NI DUNG THIT K.
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Phn III: U NHC IM CA TI.

Trong qu trnh thc hin ti do lng kin thc cn hn ch nn em
khng trnh khi nhng thiu st. Em rt mong thy c ng gp kin
em c th ng dng ti vo thc t.
Em xin chn thnh cm n Thy C!
Sinh vin:
V TH BCH HNG.
Lp: T5 - K10 - HaUI.
H Ni, Thng 6 nm 2011.
Phn I: TNG QUAN V H VI IU KHIN

8051.
1. GII THIU CHUNG V H 8051.
Nm 1981 hng Atmel gii thiu b vi iu khin 8051. B vi iu
khin (VK) ny c 128 byte RAM, 4 byte ROM, hai b nh thi, mt cng
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ni tip v bn cng vo/ra song song ( rng 8 bit ) tt c u c t trn

1 chip. 8051 l b x l 8 bit ( c ngha l CPU ch c th lm vic vi 8 bit
d liu ti mt thi im). D liu ln hn 8 bit s c chia ra thnh cc d
liu 8 bit x l.
8051 tr nn ph bin khi Intel cho php cc nh sn xut khc sn
xut v bn cc dng bin th ca 8051. iu ny dn n s ra i nhiu
phin bn ca 8051 vi tc v dung lng ROM trn chip kh nhau, nhng
tt c cc lnh u phi tng thch vi 8051 ban u. Nh vy nu ta vit
chng trnh cho mt phin bn ca 8051 th cng chy c vi mi phin
bn khc khng ph thuc vo hng sn xut.
1.1. Cu trc bus.

Bus a ch ca h vi iu khin 8051 gm 16 ng tn hiu (thng
gi l bus a ch 16 bit) vi lng bit a ch nh vy, khng gian nh ca n
c th m rng ti a n 2^16=65536 a ch tng ng 64K.
Bus d liu ca h 8051 gm 8 ng tn hiu (thng gi l d liu
8 bit), l l do v sao ni 8051 l h vi iu khin 8 bit. Vi rng ca
bus d liu nh vy, cc chip h 8051 c th x l c cc ton hng 8 bit
trong 1 chu k lnh.
1.2. B nh chng trnh.

Vi iu khin h 8051 c khng gian nh l 64K a ch, cng l
b nh chng trnh ln nht m mi chip thuc h ny c c. B nh
chng trnh ca cc chip thuc h 8051 c th thuc loi ROM, EPROM,
Flash, hoc khng c b nh chng trnh bn trong chip, tn ca chip th
hin b nh chng trnh m n cha bn trong .
1.3. B nh d liu.
B nh SRAM c tch hp bn trong mi chip thuc h ny, c dung
lng khc nhau ty loi chip nhng thng th ch khong vi trm byte.
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y chnh l ni cha cc bin trung gian trong qu trnh hot ng ca chip.

Khi mt in do bn cht ca SRAM m cc gi tr ny cng mt theo. Bn
cnh b nh loi SRAM th mt s chip thuc h 8051 cn c thm b nh
EEPROM vi dung lng ti a vi Kbyte ty tng loi chip c th. V d
nh sau:
2. GII THIU CHUNG V AT89S52.

AT89S52 l mt thnh vin ca h 8051. N l mt b VK thng
dng, gi r, c kh nhiu chc nng hay, c bit l c tch hp sn b np
ISP trn chip gip ngi s dng c th d dng thc hin cc bi th nghim
vi chi ph rt thp.
AT89S52 c 8 kbyte Flash ROM trn chip, khi chn /EA ( chn s 31)
t mc logic cao (+5v) th VK s thc hin chng trnh b nh trong.
Khi /EA t mc logic thp (0v) th VK thc hin chng trnh b nh
ngoi, AT89S52 c 256 bytes RAM ni, 32 bytes thp ca b nh ni dng
cho cc thanh ghi, 128 bit c cha cc byte nh a ch theo bit t 20H n
2FH.
AT89S52 c cha 3 b m /nh thi (timer/counter) 16 bit c dng
cho vic nh thi hoc m s kin.
AT89S52 cha 1 port ni tip phc v cho vic trao i thng tin vi
cc thit b c kh nng giao tip ni tip nh my tnh( qua cng COM)
AT89S52 c cha 6 ngun ngt, 2 mc u tin,1 b giao ng trn chip,
n thng c ni vi b giao ng thch anh c tn s ln nht l 33MHz,
thng thng l 12 MHz.
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AT89S52 dng ngun 1 chiu c di in p t 4v -5,5v c cp qua

chn 40 v chn 20.
2.1. S khi v chc nng cc khi ca h 8051.
Hnh 1.1.1: S khi ca h 8051.
* B vi iu khin AT89S52 gm cc khi chc nng sau y:

+ CPU( Central Processing unit ) bao gm:
- Thanh ghi tch ly A.
- Thanh ghi tch ly ph B, dng cho php nhn v php chia.
- n v logic hc ALU( Arithmetic Logical Unit).
- Thanh ghi t trng thi chng trnh ( PSW: Program Sttatus Worl).
- Bn bng thanh ghi.
- Con tr ngn xp.
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+ B nh chng trnh( b nh ROM) gm 8 Kb Flash.

+ B nh d liu ( B nh RAM ) gm 256 Bytes.
B UART ( Universal Ansynchrous Receiver and Transmitter) c chc
nng truyn nhn ni tip, AT89S52 c th giao tip vi cng ni tip ca
my tnh thng qua b UART.
+ Ba b timer/count 16 bit: thc hin cc chc nng nh thi v m s
kin.
+ WDM ( Watch Dog Timer ) : c dng phc hi li hot ng ca
CPU khi n b treo bi mt nguyn nhn no .
+ Khi diu khin ngt : vi 2 ngun ngt ngoi v 4 ngun ngt trong.
+ B lp trnh ( ghi chng trnh ln flash ROM ): cho php ngi s
dng c th np chng trnh cho chip m khng cn b np chuyn dng.
+ B chia tn: vi h s chia l 12.
+ Bn cng xut nhp: vi 32 chn.
2.2. S chn v chc nng cc chn ca h 8051.
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Hnh 1.1 .2: S chn ca h 8051.
2.2.1. Port 0( P0.0-P0.7).
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Hnh 1.1.3: Cu trc Port 0.
Port 0 gm 8 chn , ngoi chc nng xut nhp Port 0 cn l bus a hp

d liu v a ch ( AD0- AD7), chc nng ny s c s dng khi 8051
giao tip vi thit b ngoi c kin trc Bus nh cc vi mch nh, mch
PIO
2.2.2. Port 1( P1.0-P1.7).
i vi 8051, chc nng duy nht ca Port 1 l chc nng xut nhp,
cng nh cc Port khc Port 1 c th xut nhp theo bit v theo byte.
Ring dng 89xx, ba chn P1.5,P1.6,P1.7 c dung np ROM theo
chun ISP; hai chn P1.0 v P1.1 c dng cho b timer.
2.2.3. Port 2( P2.0-P2.7).
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Port 2 ngoi chc nng l cng vo / ra nh Port 0 v Port 1 cn l byte

cao ca bus a ch khi s dng b nh ngoi.
2.2.4. Port 3( P3.0-P3.7).
Hnh 1.1.6 : Cu trc Port 3.
Mi chn trn Port 3 ngoi chc nng xut nhp cn c mt chc nng
ring c th nh sau:
Bng 1.1.1: Chc nng cc chn ca Port3.

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Bit
Tn
Chc nng
P3.0
RXD
D liu nhn cho Port ni tip.
P3.1
TXD
D liu truyn cho Port ni tip.
P3.2
INT0
Ngt bn ngoi 0.
P3.3
INT1
Ngt bn ngoi 1.
P3.4
T0
Ng vo ca Timer/count 0.
P3.5
T1
Ng vo ca Timer/count 1.
P3.6
/WR
Xung ghi b nh d liu ngoi.
P3.7
/RD
Xung c b nh d liu ngoi.
2.2.5. Chn /PSEN( Program Store Enable)

/PSEN l chn iu khin c chng trnh b nh ngoi, n c ni
vi chn /OE cho php c cc byte m lnh trn ROM ngoi. /PSEN s
mc thp trong thi gian c m lnh. M lnh c c t b nh ngoi qua
bus d liu (Port 0) thanh ghi lnh c gii m.
Khi thc hin chng trnh trong ROM ni thi /PSEN mc cao.
2.2.6. Chn ALE ( Address Latch Enable).
ALE l tn hiu iu khin cht a ch c tn s bng 1/6 tn s dao
ng ca vi iu khin. Tn hiu ALE c dng cho php vi mch cht
bn ngoi nh 74373, 74573 cht byte a ch thp ra khi bus a hp a
ch /d liu( Port0).
2.2.7. Chn /EA( External Access).
Tn hiu /AE cho php chn b nh chng trnh l b nh trong hay
ngoi vi iu khin. Nu /AE mc cao( ni vi Vcc) th vi iu khin thi
hnh trong ROM ni. Nu /AE mc thp( ni vi GND ) th vi iu khin
thc hin chng trnh t b nh ngoi.
2.2.8. RST( Reset).
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Ng vo RST trn chn 9 l ng reset ca 8051. Khi tn hiu ny c

a ln mc cao ( trong t nht 2 chu k my) , cc thanh ghi trong b vi diu
khin c ti nhng gi tr thch hp khi ng h thng.
2.2.9. XTAL1, XTAL2.
AT89S52 c mt b dao ng trn chip, n thng c ni vi b dao
ng thch anh c tn s ln nht l 33MHz, thng thng l 12MHz.
2.2.10. Vcc,GND.
AT89S52 dng ngun mt chiu c di in p t 4V n 5.5 V c cp
qua chn 40 v 20.
2.3. Hot ng nh thi.

2.3.1. Gii thiu.
Cc b nh thi(Timer) c s dng rt rng ri trong cc ng dng
o lng v iu khin.C th coi mt b nh thi n bit l b m n bit c
to ra bi n flip_flop mc ni tip vi nhau.u ca b nh thi chnh l u
vo ca flip_flop u tin...
AT89S52 c 3 b nh thi 16 bit trong hai b Timer 0,Timer 1 c 4
ch hot ng. Timer 2 c 3 ch hot ng. Cc b nh thi dng
nh khong thi gian(hn gi), m s kin xy ra bn ngoi b vi iu
khin hoc to tc baud cho cng ni tip.
Trong cc ng dng nh khong thi gian, Timer c lp trnh sao cho
s trn sau mt khong thi gian v thit lp c trn bng 1. C trn c s
dng bi chng trnh thc hin mt hnh ng tng ng nh kim tra
trng thi ca cc ng vo hoc gi cc s kin ra cc ng ra.
m s kin dng xc nh s ln xy ra ca mt s kin. Trong ng
dng ny ngi ta tm cch quy cc s kin thnh s chuyn mc t 1 xung
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0 trn cc chn T0 hoc T1 hoc T2 dng cc Timer tng ng m cc s

kin .
2.3.2. Cc thanh ghi ca b nh thi.
* Cc thanh ghi ca Timer0,Timer1.
- Thanh ghi ch nh thi(TMOD).
Thanh ghi TMOD cha hai nhm 4 bit dng t ch lm vic cho
Timer0 v Timer1.
7
GATE1
C/#T1
M1
M0
GATE0
C/#T0
M1
MO
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Bit
Tn
Timer
M t
GATE1
Bit m cng cho timer 1.
C/#T1
Bit chn ch Counter/Timer 1.

1=b m s kin.
0=b nh khong thi gian.
M1
Bit 1 chn ch ca Timer1.
M0

00: Ch 0- Timer 13bit.
01: Ch 1-Timer 16bit.
10: Ch 2- 8 bit t ng np li.
11: Ch 3-tch timer.
GATE0
Bit m cng timer 0,khi c t bng 1 th

Timer0 ch chy khi chn INT0 mc cao.
C/#T0
Bit chn ch counter/timer ca Timer0.
M1
M0
TMOD khng c bit nh v, n thng load mt ln bi phn mm

u chng trnh khi ng mode Timer. Sau s nh gi c th dng
li, c khi ng li nh th bi truy xut ca cc thanh ghi chc nng c
bit ca Timer khc.
-Thanh ghi iu khin Timer(TCON).
Thanh ghi TCON cha cc bit trng thi v cc bit iu khin Timer0 v
Timer1.
Bn bit cao trong TCON (TCON.4-TCON.7) c dng iu khin
cc b nh thi hot ng hoc ngng(TR0,TR1) hoc bo cc b nh
thi trn(TF0,TF1).
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Bn bit thp ca TCON(TCON.0-TCON.3) khng dng iu khin

cc b nh thi, chng c dng pht hin v khi ng cc ngt ngoi.
- Cc thanh ghi cha gi tr ca cc b nh thi.
Cc Timer0 v Timer1 u l cc Timer 16bit, mi Timer c thanh ghi
8bit dng cha gi tr khi to hoc gi tr hin thi ca cc Timer.
2.3.3 Cc ch ca b nh thi.
* Cc ch ca Timer0 v Timer1.
- Ch 0.
Ch 0 l ch nh thi 13bit, ch ny tng thch vi cc b vi
iu khin trc , trong cc ng dng hin nay ch ny khng cn thch
hp.
Hnh 1.1.7 Hot ng ca Timer0 v Timer1 ch 0.
- Ch 1.
Trong ch 1,b Timer dng c hai thanh ghi TH v TL cha gi tr
m, v vy ch ny cn c gi l ch nh thi 16bit. Bit MSB s l
bit D7 ca TH cn bit LSB l D0 ca TL.
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Hnh 1.1.8 m t hot ng ca cc Timer ch 1: Ngun xung clock

c a ti Timer t mt trong cch ph thuc vo bit C/#T trong thanh ghi
TMOD.
+ Nu C/#T=1, xung clock s
c ly t bn ngoi qua chn
Tx(T0,T1,T2).
+ Nu C/#T=0, xung clock s c ly t b chia tn trong chip,tn s
ca xung y l 1/12 tn s ca dao ng thch anh.
Ngun xung clock trn s c iu khin a ti cc Timer bng
cc bit: TR,GATE v mc logic trn cc chn INTx.
+ Nu TRx=0, cc Timer s b cm m khng cn quan tm ti GATE
v mc logic trn cc chn INTx ( th hin bng cng AND).
+ Nu TRx=1, cc Timer s hot ng khi hoc l bit GATE=0 hoc l
bit GATE=1 v trn chn /INTx c mc logic 1.
Vi ch 1, gi tr ln nht m cc Timer cha c l 65535, khi m
qu gi tr ny s xy ra trn, khi c trn TF s c t =1. Sau khi xy ra
trn, nu mun Timer tip tc m, chng trnh phi c cu lnh np li gi
tr khi to sau khi dng Timer bng cch xa bit TR.
- Ch 2
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Trong ch 2, b Timer dng TL cha gi tr m v TH cha

gi tr np li v vy ch ny c gi l ch t np li 8 bit. Sau khi
m qu 255 s xy ra trn,khi TF c t bng 1 ng thi gi tr ca
Timer t ng c np li bng ni dung ca TH.
Vi ngun xung clock,cch iu khin Timer ch 2 hon ton ging
ch 1.
- Ch 3.
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Hnh 1.1.10 Hot ng ca Timer0 ch 3.
Trong ch 3, Timer0 c tch thnh hai b Timer hot ng c lp,

ch ny s cung cp cho b vi iu khin thm b Timer na.
B Timer th nht vi ngun xung clock c ly t b chia tn trn
chip hoc t b to xung bn ngoi qua chn T0 ty thuc vo gi tr ca bit
C-/T0. Vic iu khin hot ng ca b th nht do bit GATE, bit TR0 v
mc logic trn chn INT0 ( ging ch 0,1,2 ).
Gi tr m ca Timer c cha trong TL0, khi xy ra trn, c TF0=1
v gy ra ngt do Timer0 (nu c t).
B Timer th hai vi ngun xung clock c ly t b chia tn trn
chip. Vic iu khin hot ng ca b th hai ch l vic t gi tr ca bit
TR0. Gi tr m ca Timer c cha trong TH0, khi xy ra trn, c TF1=1
v gy ra ngt do Timer1(nu c t).
Khi Timer0 c tch thnh hai Timer 8 bit th Timer1 vn c th hot
ng bnh thng cc ch 0,1,2, tuy nhin khi xy ra trn c TF1 khng
c thit lp bng 1. Nh vy trong trng hp ny Timer1 ch c th s
dng cho cc ng dng khng cn n ngt(TF1=1), chng hn nh to tc
baud cho port ni tip.
2.4. Ngt v x l ngt.

2.4.1. Gii thiu.
Interrupt l mt s c c iu kin m n gy ra s ngng li tm thi
ca chng trnh phc v mt chng trnh khc. Cc Interrupt vn hnh
mt Relay rt quan trng trong thit b v s cung cp y cc ng dng vi
iu khin. Chng cho php mt h thng p ng ng b n s kin quan
trng v gi quyt s kin trong khi chng trnh khc ang thc thi. Mt
h thng c li bi Interrupt cho mt k xo lm nhiu cng vic cng mt
lc. Tt nhin CPU khng th thc thi nhiu lnh ti mt thi im, nhng n
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c th tm thi treo cng vic thc thi ca chng trnh chnh thc thi
chng trnh khc v sau quay li chng trnh chnh.
Khi chng trnh chnh ang thc thi m c mt s ngt xy n th
chng trnh chnh ngng thc thi v r nhnh n th tc phc v ngt
ISR.ISR thc thi thc hin hot ng v kt thc vi lnh tr li t s
ngt .Chng trnh tip tc ni m n dng li.
2.4.2 T chc ngt.
AT89S52 c 6 ngun ngt:
- Ngt ngoi n t chn #INT0.
- Ngt ngoi n t chn #INT1.
- Ngt do b Timer0.
- Ngt do b Timer1.
- Ngt do b Timer2.
- Ngt do Port ni tip.
6 ngun ngt ny c xa khi reset v c t ring bng phn mm
bi cc bit trong thanh ghi cho php ngt(IE) ,thanh ghi u tin ngt(IP).
* Thanh ghi cho php ngt IE(Interrupt Enable):
EA
ET2
ES
ET1
EX1
ET0
EX0
Bit
K hiu
a ch bit
IE.7
EA
AFH
Cho php hoc cm ton b.
IE.6
AEH
Khng c nh nga.
IE.5
ET5
ADH
Cho php ngt t timer 2.
IE.4
ES
ACH
Cho php ngt Port ni tip.
IE.3
ET1
ABH
Cho php ngt t timer1.
IE.2
EX1
AAH
Cho php ngt ngoi 1.
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IE.1
ET0
A9H
Cho php ngt t timer 0.
IE.0
EX0
A8H
Cho php ngt ngoi 0.
* Thanh ghi u tin ngt IP:

Mi ngun ngt c lp trnh ring t vo mt trong hai mc u
tin qua thanh ghi chc nng c bit c a ch bit IP a ch B8H.
PT2
PS
PT1
a ch bit
PX1
PT0
PX0
Bit
K hiu
M t(1: cho php, 0: cm)
IP.7
Khng c nh nghia.
IP.6
Khng c nh ngha.
IP.5
PT2
BDH
u tin cho ngt t timer2.
IP.4
PS
2.4.3 X l ngt.
IP.3
PT1
BCH
BBH
u tin cho ngt t port ni

tip.
IP.2
PX1
BAH
IP.1
PT0
B9H
u tin cho ngt ngoi 1.
IP.0
PX0
B8H

u tin cho ngt ngoi 0.
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- Khi c mt ngt xut hin v c CPU chp nhn c cc thao tc

sau:
+ Hon tt lnh thc thi hin hnh.
+ PC c ct vo Stack.
+ Trng thi ca ngt hin hnh c lu gi li.
+ Cc ngt c chn li mc ngt.
+ PC np a ch vector ngt ca ISR.
+Thc thi ISR.
- Cc ngt do Port ni tip.
+ Cc ngt ny xut hin khi c ngt pht TI hoc c ngt thu RI c
set bng 1.
+ C gy ra ngt port ni tip khng c xa bi phn cng khi CPU
tr ti ISR.
- Cc ngt ngoi.
+ Xy ra khi c mc thp hoc c cnh m trn chn /INT0 v /INT1.
+ Cc c gy ra ngt ny l cc bit IE0,IE1 ca TCON.
+ Vic chn cc ngt loi tc ng mc hay cnh c lp trnh thng
qua cc bit IT0 v IT1 ca TCON.
+ Cc c gy ngt IE0,IE1 t ng c xa khi CPU tr ti ISR tng
ng.
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PHN II: NI DUNG THIT K.

Chng I: GII THIU CC MODUL V CC LINH
KIN DNG TRONG MCH.
1. KHI NGUN.
Hnh 1.2.1 : S d khi ngun.
Cung cp ngun nui 5V cho ton mch.
2. KHI GHP NI VI MY TNH QUA CNG COM.
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Hnh 1.2.2 S khi ghp ni vi my tnh qua cng ni tip.
2.1 Cng ni tip (COM).

Cng ni tip l mt giao din rt ph bin trn my tnh, cng ny c
tn gi khc l cng COM. N c s dng kh rng ri v thun tin cho
vic ghp ni my tnh vi thit b ngoi. Khong cch truyn ca cng ni
tip c ci thin hn so vi cng song song do mc chnh lch in p l
kh ln.
Vic truyn d liu qua cng COM c tin hnh theo cch ni tip.
Ngha l cc bit d liu c truyn i ni tip nhau trn mt ng dn. Loi
truyn ny c kh nng dng cho nhng ng dng c yu cu truyn khong
cch ln hn, bi v cc kh nng gy nhiu l nh ng k hn khi dng mt
cng song song (cng my in).
Cng COM khng phi l mt h thng bus n cho php d dng to ra
lin kt di hnh thc im vi im gia hai my cn trao i thng tin vi
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nhau, mt thnh vin th ba khng th tham gia vo cuc trao i thng tin
ny.
* S chn cng COM.
Hnh 1.2.3 S chn ca cng COM.
* ngha cc chn tn hiu:

- Chn 1 (DCD) : Tn hiu pht hin mang d liu.
- Chn 2 (RxD) : Nhn d liu.
- Chn 3 (TxD) : Truyn d liu.
- Chn 4 ( DTR) : D liu cui sn sang.
- Chn 5 ( GND) : Ni t.
- Chn 6 (DSR) : D liu sn sng c gi.
- Chn 7 ( RTS) : Tn hiu yu cu gi.
- Chn 8 ( CTS) : Tn hiu yn cu xa gi tip.
- Chn 9 ( RI) : Ring Indicator.
2.2. IC MAX232.
B vi iu khin AT89S52 c kh nng giao tip vi th gii bn ngoi
thng qua cng ni tip. Vn tr ngi duy nht khi giao tip vi my tnh
l mc logic b vi iu khin v cng COM ca my tnh khc nhau, c
th nh sau:
Bng 1.2.1: So snh in p ca cc mc logic gia RS232 v TTL.
i tng
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Cng COM
-12V n -3V
(RS232)
+3V n +12V
Vi iu khin
+5V
(Mc TTL)
0V
Khc phc vn ny, ngi ta s dng vi mch MAX232 chuyn

i mc in p gia hai chun. Vi mch ny c cha hai b chuyn i mc
logic t TTL sang RS232 v ngc li.
Hnh 1.2. 4 S chn v hnh nh thc t ca MAX 232.
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3. KHI VI IU KHIN.
Hnh 1.2.5 S khi vi iu khin.
3.1 Mch to dao ng.
Hnh 1.2.6: S mch to dao ng ca 8051.
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AT89S52 c mt b chia tn bn trong chip, b ny s cp xung clock

cho cc khi trn chip t ngun dao ng bn ngoi qua 2 chn XTAL1 v
XTAL2 .
B chia tn c th hot ng hai ch :
- Ch X1: ( ch mc nh): ch ny tn s thch anh c
chia 12 ln, ngha l mt lnh c thc hin trong mt chu k my v tn s
thch anh l 12 MHz th thi gian thc hin lnh s l 12 (us).
- Ch X2: ch ny tn s thch anh c chia 6 ln , ch nay
c dt bng cch t cc bit thanh ghi CLKCON0 v thanh ghi
CLKCON1.
3.2 Mch reset.
Hnh 1.2.7: S mch reset ca 8051.
C 4 cch reset AT89S52 ln lt l: reset khi cp ngun, reset bi

WDT, reset bng phn mm, reset bng mch ngoi qua chn RST.
Trong mt h thng gm nhiu vi mch kh trnh th mt mch reset tch
hp c 2 cch reset khi bt ngun v reset bi mch ngoi thng c s
dng.
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4. KHI QUT LED MA TRN 8x8.
Hnh 1.2.8 S khi qut led matrix.
4.1. IC 74HC595.
74HC595 l IC ghi dch 8bit kt hp cht d liu. u vo ni tip, u
ra song song.
Chc nng: Thng dung trong cc mch qut led 7 on, led matrix
tit kim s chn VK ti a. C th m rng s chn vi iu khin bao
nhiu ty thch m khng IC no c th lm c bng vic mc ni tip u
vo d liu cc IC vi nhau.
* S chn IC 74HC595.
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Hnh 1.2.9: S chn v hnh nh thc t ca IC 74HC595.
* Gii thch ngha hot ng ca mt s chn quan trng:

- Chn 14: u vo d liu ni tip. Ti mt thi im xung clock ch
a vo c 1 bit.
- QA=>QH: Trn cc chn (15,1,2,3,4,5,6,7): Xut d liu khi chn 13
tch cc mc thp v c mt xung tch cc sn m ti chn cht 12.
- Chn 13: Chn cho php tch cc mc thp (0). Khi mc cao tt c
cc u ra ca 74HC595 tr v trng thi cao tr, khng c u ra no c
cho php.
- Chn 9: Chn d liu ni tip. Nu dng nhiu 74HC595 mc ni tip
nhau th chn ny a vo u vo con tip theo khi dch 8bit.
- Chn 11: Chn vo xung clock. Khi c 1 xung clock tch cc sn
dng th mt bit c dch vo IC.
- Chn 12: Xung clock cht d liu. Khi c 1 xung clock tch cc sn
dng th cho php xut d liu trn cc chn output.
- Chn 10: Khi chn ny mc thp (0) th d liu s b xa trn chip.
4.2 LED MATRIX 8X8.
4.2.1 S nguyn l ca ma trn led 8x8.
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Hinh 1.2.10: S chn v hnh nh thc t ca Led Matrix 8x8.
Cc led trn cng mt hng c ni chn dng vi nhau.

Cc led trn cng mt ct c ni chn m vi nhau.
Trng thi ca mi led c quyt nh bi tn hiu in p 5v a vo ng
thi c 2 chn.
VD : led sng th in p 5v phi a vo chn dng cn chn m ni
mass. Led tt th khng c in p ni vo chn dng.
4.2.2 Cch qut LED ma trn 8x8.
Ti mt thi im th ch c trng thi ca mt im nh c xc nh.
xc nh cc trng thi v a ch im nh tip theo th cc im nh cn li
s chuyn v trng thi tt( led ang sng s chuyn v trng thi tt dn ). V
th hin th c ton b hnh nh ca ma trn led ta c th qut ma trn led
nhiu ln vi tc qut rt ln( ln hn nhiu ln thi gian kp tt ca n).
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Mt ngi ch nhn bit c ti a 24 hnh/s. Do nu tc qut rt ln

th s khng nhn ra c s thay i ca n m s thy c ton b hnh
nh cn hin th.
5. KHI GIAO TIP LCD.
Hnh 1.2.11 S khi giao tip LCD.
LCD c s dng trong ti l loi hin th k t ( character LCD)

kch c 16x2. Mi k t c to bi mt ma trn cc im sang kch thc
5x7 hoc 5x10.
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Hnh 1.2.12: Hnh nh LCD
5.1. ngha cc chn ca LCD hin th k t.

Hu ht cc module LCD hin th k t c thit k da trn b iu
khin HD 44780 ca Hitachi nn chng c tp lnh v chn tng thch nhau.
Bng 1.2.2 Bng chc nng cc chn ca module LCD c ti a 80 k t.
Chn s
K Hiu
Mc Logic
I/O
Chc nng
Vss
Ngun cung cp (GND)
Vcc
Ngun cung cp (+5V)
Vee
RS
0/1
in p vo iu chnh
tng phn
La chn thanh ghi
0= Thanh ghi lnh
1= Thanh ghi d liu
R/W
0/1
0= Ghi vo LCD module

1= c t LCD module
1.1 0
Tn hiu cho php
DB0
0/1
I/O
Data bus line 0 (LSB)
DB1
0/1
I/O
Data bus line 1
DB2
0/1
I/O
Data bus line 2
10
DB3
0/1
I/O
Data bus line 3
11
DB4
0/1
I/O
Data bus line 4
12
DB5
0/1
I/O
Data bus line 5
13
DB6
0/1
I/O
Data bus line 6
14
DB7
0/1
I/O
Data bus line 7 (MSB)
5.2 Nguyn tc hin th k t trn LCD.

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Mt chng trnh hin th k t trn LCD s i qua 4 bc sau:

1. Xa ton b mn hnh.
2. t ch hin th.
3. t v tr con tr ( Ni bt u ca k t hin th).
4. Hin th k t.
Cc bc 3 v 4 c th c lp i lp li nhiu ln nu cn hin th
nhiu k t .
Mi khi thc hin ghi lnh hoc ghi d liu hin th ln LCD u phi
kim tra c bn. Tuy nhin c mt s loi LCD khng cho php kim tra c
bn v vy b VK cn phi ch ng phn phi thi gian khi ra lnh cho
LCD.
Ch hin th mc nh s l hin th dch, v tr con tr mc nh s l
u dng th nht.
iu khin hot ng ca LCD nn s dng Port 2 hoc Port 1 cho
vic xut nhp d liu. Cc chn to tn hiu iu khin RS, RW, EN_LCD c
th chn ty trong cc chn ca Port cn li.
6. KHI
ADC0804
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Hnh 1.2.13 S khi chuyn i A/D.
Thc hin chuyn i tn hiu tng t thnh tn hiu s.

* ADC0804
Chp ADC 0804 l b chuyn i tng t sang s thuc h ADC 0800 t
hng National Semiconductor. N cng c nhiu hng khc sn xut, lm
vic vi +5V v c phn gii l 8 bt. Ngoi phn gii th thi gian
chuyn i cng l mt yu t quan trng khc khi nh gi mt b ADC.
Thi gian chuyn i c nh ngha nh l thi gian m b ADC cn
chuyn mt u vo tng t thnh mt s nh phn. Trong ADC 0804 thi
gian chuyn i thay i ph thuc vo tn s ng h c cp ti chn
CLK v CLK IN nhng khng th nhanh hn 110s.
* S chn v chc nng cc chn ca IC ADC0804.
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Hnh 1.2.14 S chn v hnh nh thc t ca IC ADC 0804.
- Chn
- chn chp: L mt u vo tch cc mc thp c s dng
kch hot chp ADC 804. truy cp ADC 804 th chn ny phi mc thp.
- Chn
(c): y l mt tn hiu u vo c tch cc mc thp. Cc
b ADC chuyn i u vo tng t thnh s nh phn tng ng vi n

v gi n trong mt thanh ghi trong.
c s dng nhn d liu c
chuyn i u ra ca ADC 804. Khi CS = 0 nu mt xung cao xung thp

c a n chn
D0 - D7. Chn
- Chn ghi
th u ra s 8 bt c hin din cc chn d liu

cng c coi nh cho php u ra.
(thc ra tn chnh xc l Bt u chuyn i). y l
chn u vo tch cc mc thp c dng bo cho ADC 804 bt u qu

trnh chuyn i. Nu CS = 0 khi
to ra xung cao xung thp th b ADC
804 bt u chuyn i gi tr u vo tng t V in v s nh phn 8 bt.

Lng thi gian cn thit chuyn i thay i ph thuc vo tn s a
n chn CLK IN v CLK R. Khi vic chuyn i d liu c hon tt th
chn INTR c p xung thp bi ADC 804.
- Chn CLK IN v CLK R: Chn CLK IN l mt chn u vo c ni
ti mt ngun ng h ngoi khi ng h ngoi c s dng to ra thi
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gian. Tuy nhin 804 cng c mt b to xung ng h. s dng b to

xung ng h trong (cng cn c gi l b to ng h ring) ca 804 th
cc chn CLK IN v CLK R c ni ti mt t in v mt in tr nh ch
ra trn hnh 3.6.1. Trong trng hp ny tn s ng h c xc nh bng
biu thc:
Gi tr tiu biu ca cc i lng trn l R = 10k v C= 150pF v tn s

nhn c l f = 606kHz v thi gian chuyn i s mt l 110s.
- Chn ngt
(ngt hay gi chnh xc hn l kt thc chuyn i).
y l chn u ra tch cc mc thp. Bnh thng n trng thi cao v

khi vic chuyn i hon tt th n xung thp bo cho CPU bit l d liu
c chuyn i sn sng ly i. Sau khi
v gi mt xung cao 0 xung thp ti chn
xung thp, ta t CS = 0
ly d liu ra ca 804.
- Chn Vin (+) v Vin (-): y l cc u vo tng t vi sai m Vin = Vin

(+) - Vin (-). Thng thng Vin (-) c ni xung t v Vin (+) c dng
nh u vo tng t c chuyn i v dng s.
- Chn VCC. y l chn ngun nui +5v, n cng c dng nh in p
tham chiu khi u vo Vref/2 (chn 9) h.
- Chn Vref/2. Chn 9 l mt in p u vo c dng cho in p tham
chiu. Nu chn ny h (khng c ni) th in p u vo tng t cho
ADC 804 nm trong di 0 n +5v (ging nh chn VCC). Tuy nhin, c nhiu
ng dng m u vo tng t p n Vin cn phi khc ngoi di 0 n 5v.
Chn Vref/2 cdng thc thi cc in p u vo khc ngoi di 0 - 5v. V
d, nu di u vo tng t cn phi l 0 n 4v th Vref/2 c ni vi +2v.
Ghi ch: - VCC = 5V.
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Khi Vref/2 h th o c khong 2,5V. Kch thc bc ( phn di)

l s thay i nh nht m ADC c th phn bit c.
- Cc chn d liu D0 - D7. (D7 l bt cao nht MSB v D0 l bt thp
nht LSB) l cc chn u ra d liu s. y l nhng chn c m ba
trng thi v d liu c chuyn i ch c truy cp khi chn CS = 0 v
chn
b a xung thp. tnh in p u ra ta c th s dng cng
thc sau:
Vi Dout l u ra d liu s (dng thp phn). V in l in p u vo

tng t v phn di l s thay i nh nht c tnh nh l (2 V ref/2)
chia cho 256 i vi ADC 8 bt.
- Chn t tng t v chn t s: y l nhng chn u vo cp
t chung cho c tn hiu s v tng t. t tng t c ni ti t ca
chn Vin tng t, cn t s c ni ti t ca chn V cc. L do m ta phi
c hai t l cch ly tn hiu tng t Vin t cc in p k sinh to ra vic
chuyn mch s c chnh xc. Trong phn trnh by ca chng ta th cc
chn ny c ni chung vi mt t. Tuy nhin, trong thc t thu o d liu
cc chn t ny c ni tch bit.
7. KHI HIN TH THI GIAN THC.

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Hnh 1.2.15 S khi hin th thi gian thc.
* DS 1307
DS 1307 l chip ng h thi gian thc ( RTC: Real-time clock ). Chip
ny c 7 thanh ghi, 8 bit cha thi gian l: giy, pht, gi, th, ngy, thng,
nm. Ngoi ra DS 1307 cn c mt thanh ghi iu khin ng ra ph v 56
thanh ghi trng c th dng nh RAM. DS1307 c c v ghi thng qua
giao din ni tip I2C nn cu to bn ngoi rt n gin.
Hnh 1.2.16: S chn v hnh nh thc t ca DS1307.
* Cc chn ca DS 1307 c m t nh sau:

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- X1 v X2 : l 2 ng kt ni vi thch anh 32.768 KHz lm ngun to

dao ng cho chip.
- VBAT : cc dng ca 1 ngun pin 3V nui chip.
- GND: chn mass chung cho c pin 3V v Vcc.
- Vcc ngun cho giao din I2C thng l 5V v dung chung vi VK.
- SQW/OUT: mt ng ph to xung vung, tn s ca xung c to c
th c lp trnh . Khi ni mch chn ny thng b trng.
- SCL v SDA l 2 ng giao xung nhip v d liu ca giao din I2C.
*Ch :Nu Vcc khng c cp ngun nhng Vbat c cp th
DS1307 vn hot ng(nhng khng ghi v c c)
8. KHI NGT HNG NGOI.
Hnh 1.2.17: S khi ngt hng ngoi.
8.1 OPTO
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Hnh 1.2.18 S chn ca OPTO.
Opto hay cn gi l cch ly quang l linh kin tch hp c cu to gm 1

led v 1 photo diot hay mt photo transito. c s dng cch ly gia cc
khi chnh lch nhau v in hay cng sut nh khi c cng sut nh vi
khi c in p ln.
* Nguyn l hot ng:
Khi c dng nh i qua hai u ca led c trong opto lm cho led pht
sang. Khi led pht sng lm thng hai cc ca photo diot m cho dng in
chy qua.
8.2. LM358.
Hnh 1.2.19: S chn v hnh nh thc t ca LM358.
- LM 358 l mt b khuch i thut ton kp ( gm 2 con opamp bn

trong) c 2 chn u vo o, hai chn u vo khng o v hai chn u ra.
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- S dng ngun n t 3V-32V hoc ngun i xng t +/- 1,5V n

+/- 16V.
- Hot ng nhit t 0 - 70 .
9. KHI QUT LED 7 ON.
Hnh 1.2.20 S khi qut led 7 on.
* Led qut 4.
Hnh 1.2.21. Hnh nh thc t ca led qut 4.
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LED qut 4 c 12 chn 4 chn cp ngun cho 4 LED v 8 chn iu

khin cc thanh hin th v du chm, c dng trong cc mch m sn
phm, ng h.
Hnh 1.2.22. S chn ca led quet 4.
hin th trn led 7 on th cn 8 ng iu khin ( 7 ng cho 7

on v 1 ng cho du chm) khi iu khin trc tip hoc cn 4 ng
dy iu khin khi dng vi mch gii m BCD-7 on 7447. Vi c hai cch
trn nu cn iu kin mt lng ln cc ng iu khin trong khi s lng
cc ng iu khin trn b vi iu khin l c hn. gim thiu s ng
dy iu khin ngi ta dng phng php qut.
* Nguyn l hin th qut: iu khin cho n led 7 on ta s dng n
ng dy iu khin cp ngun cho cc led v 8 ng dy s liu chung
cho tt c cc led. Vic hin th c thc hin bng cch ln lt cp ngun
cho cc led v a s liu tng ng ca led ra 8 ng dy s liu. Nh
vy thc cht ti mt thi im ch c 1 led hot ng cn li cc led khc
khng hot ng v khng c cp ngun. Tuy nhin do c tnh lu nh ca
mt m ta thy tt c cc led u hot ng.
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10. KHI QUT LED N.
Hnh 1.2.23 S khi qut led n.
Khi qut led n c chc nng kim tra kh nng xut nhp ca cc
Port. Tt c cc Port0, Port1, Port2, Port3 ca vi iu khin u c kh nng
xut nhp theo tng bit v tng byte.
11. KHI GHP NI MA TRN PHM 4x4.
Hnh 1.2.24. Khi ghp ni ma trn phm 4x4.

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Ma trn phm 4x4 gm 16 phm. Khi ta thc hin nhn mt phm bt k

th s hiu ca phm s c hin th trn thit b giao tip.
Phm bm c ni thnh ma trn 4 hng x 4ct, cc hng v ct c
ni vi cc chn cng vo ra ca vi iu khin. Khi mt phm c bm, n
s ni mt hng v mt ct tng ng. Nh vy ta s c 16 nt nhn m ch
mt c 8 chn vi iu khin. Khi nt 1 c nhn th n ni gia ct 1 hng 1.
Cn nt 2 c nhn th ct 2 v hng 1 c ni, nt 3 c nhn th ni
gia ct 3 v hng 1... c nh vy n nt th 16.
12. KHI IU KHIN NG C 1 CHIU.
Hnh 1.2.25. S khi iu khin ng c mt chiu.
ng c bc l mt c cu chp hnh rt thng dng trong cc ng

dng iu khin v tr chnh xc. ng c bc thng dch chuyn u t
ca a mm, dch chuyn giy trong my in, dch chuyn mi khoan trong
my khoan l mch in...
* Mch cu H
Mch cu H c cu to bi 4 transitor hay l Fet. i khi mch cu H
cng c cu to bi 2 transitor hay Fet. Tc dng ca transitor v Fet l cc
van ng m dn dng in t ngun xung ti vi cng sut ln. Tn hiu
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iu khin cc van l tn hiu nh (in p hay dng in) v cho dn dng v

in p ln cung cp cho ti.
Hiu nh th ny tn hiu iu khin ca mnh l nh thng l tn hiu
u ra ca vi iu khin l nh hn 5V (do cc iu ch PWM) m iu khin
ng c cn dng in v in p ln. Cc van iu khin hay cc chn iu
khin ch cn tn hiu nh (in p hay dng in) l m kha (Transitor) dn
dng cho ti.
Mch cu H c th o chiu dng in qua ti nn th n hay c
dng trong cc mch iu khin ng c DC . Ch cn m kha cc van ng
chiu m mnh mun.
Hnh 1.2.26: S mch cu H.
13. KHI NP CHNG TRNH THEO CHUN ISP.

Hnh 1.2.27. S khi np chng trnh theo chun ISP.
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Thc hin np chng trnh cho vi iu khin thng qua chun ISP.
Dng vi iu khin 89Sxx c 3 chn P1.5, P1.6, P1.7 c dng np
ROM theo chun ISP.
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49
Phn 2: NI DUNG THIT K.

Chng I. THIT K M HNH B KIT THC
HNH VK.
1. YU CU:
- Mch in t c thit k trn my tnh bng phn mm chuyn dng.
- Mch c th kim tra khai thc c cc ti nguyn ca VK AT89S52.
2. S NGUYN L.
Hnh 2.1.1 : S mch nguyn l.
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Chng II: CC V D MINH HA CHO CC

MODUL.
1. LP TRNH GHP NI MODUL LED 7 ON V B M
HNG NGOI.
- Mc ch: m sn phm hin th trn Led 7 on.
- Chng trnh iu khin AT89S52.
#include<regx52.h>
sbit DK1=P3^4;
sbit DK2=P3^5;
sbit DK3=P3^6;
sbit DK4=P3^7;
unsigned int dem;
unsigned int
M[10]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};
void delay(unsigned int x)//tao ham tre(delay)
{
unsigned int i;
for(i=0;i<=x;i++);
}
void hien_thi()//ham quet led 7 thanh
{
int i,nghin,tram,chuc,don_vi;
nghin=dem/1000;
tram=dem%1000/100;
chuc=dem%1000%100/10;
don_vi=dem%1000%100%10;
for(i=0;i<=10;i++)
{
DK1=0;
P0=M[don_vi];
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delay(100);
DK1=1;
P0=0xff;
DK2=0;
P0=M[chuc];
delay(100);
DK2=1;
P0=0xff;
DK3=0;
P0=M[tram];
delay(100);
DK3=1;
P0=0xff;
DK4=0;
P0=M[nghin];
delay(100);
DK4=1;
P0=0xff;
}
}
void main()
{
IE=0x85;
IT1=IT0=1;
while(1)
{
hien_thi();
}
}
void ngat0(void) interrupt 0
{
dem--;
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}
void ngat1(void) interrupt 2
{
dem++;
}
2. LP TRNH GHP NI LCD V ADC 0804.

- Mc ch: Thit k voltmet ( c gi tr in p trn bin tr, hin th
trn mn hnh LCD).
.- Chng trnh iu khin AT89S52.
#include<regx52.h>
sbit RS=P3^7;
sbit RW=P3^6;
sbit EN=P3^5;
sbit RD_ADC=P1^2;
sbit INTR_ADC=P1^0;
sbit WR_ADC=P1^1;
char x;
unsigned int y,n,dien_ap_thuc;
float dien_ap;
void delay(unsigned int x)//tao ham tre(delay)
{
unsigned int i;
for(i=0;i<=x;i++);
}
void BF()//kiem tra co ban BF
{
P0=0xff;
RS=0;
RW=1;
while(x==0x80)
{
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EN=1;
delay(10);
EN=0;
x=P0;
x=x&0x80;
}
}
void ghi_lenh(unsigned char x)//ghi lenh ra LCD
{
BF();
P0=x;
RS=0;
RW=0;
EN=1;
delay(50);
EN=0;
delay(50);
}
void ghi_du_lieu(unsigned char x)//ghi du lieu can hien thi
{
BF();
P0=x;
RS=1;
RW=0;
EN=1;
delay(35);
EN=0;
delay(35);
}
void ghi_du_lieu_cham(unsigned char x)//ghi du lieu can hien thi
{
BF();
P0=x;
RS=1;
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RW=0;
EN=1;
delay(5000);
EN=0;
delay(5000);
}
void chuoi_cham(char *s)
{
while(*s)
{
ghi_du_lieu_cham(*s);//ghi mot chuoi ki tu ra LCD
s++;
}
}
void chuoi(char *s)
{
while(*s)
{
ghi_du_lieu(*s);//ghi mot chuoi ki tu ra LCD
s++;
}
}
void thong_so()//cai dat thong so ban dau cho LCD
{
ghi_lenh(0x38);
ghi_lenh(0x0e);
ghi_lenh(0x06);
ghi_lenh(0x03);
ghi_lenh(0x01);
}
void hien_thi()
{
int i,M[2];
unsigned int chuc,don_vi,thap_phan;
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thap_phan=(dien_ap-dien_ap_thuc)*10;
M[0]=dien_ap_thuc%10;
M[1]=dien_ap_thuc/10;
chuc=thap_phan%10;
don_vi=thap_phan/10;
chuoi("
");
for(i=1;i>=0;--i)
ghi_du_lieu(0x30+M[i]);
chuoi(".");
ghi_du_lieu(0x30+chuc);
ghi_du_lieu(0x30+don_vi);
chuoi(" Vol");
}
void do_dien_ap()//ham chuyen doi tu ADC-->VDK
{
RD_ADC=0;
WR_ADC=0;
delay(3);
WR_ADC=1;
y=P2;
dien_ap=(float)(y*5)/255;
dien_ap_thuc=(int)(dien_ap);
}
void main()
{
thong_so();
ghi_lenh(0x80);
chuoi_cham("DO DIEN AP 5V");
ghi_lenh(0xc0);
chuoi_cham("DIEN TU 05-K10");
while(1)
{
do_dien_ap();
ghi_lenh(0x80);
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chuoi("DIEN AP DO DC");
ghi_lenh(0xc0);
hien_thi();
}
}
3. LP TRNH GHP NI LED MA TRN.

- Mc ch: iu khin Led matrix sng ch A.
#include<regx52.h>
sbit datah=P0^3;
sbit clkh=P0^4;
sbit strh=P0^5;
sbit datac=P0^0;
sbit clkc=P0^1;
sbit strc=P0^2;
unsigned int H[8]={0,0x3f,0x7f,0x88,0x88,0x7f,0x3f,0};
unsigned int C[8]={0xfe,0xfd,0xfb,0xf7,0xef,0xdf,0xbf,0x7f};
void delay(unsigned int x)
{
unsigned int i;
for(i=0;i<=x;i++);
}
void hien_thi1(unsigned int x)
{
int j,y;
for(j=0;j<=7;j++)
{
y=x;
y=y&0x80;
if(y==0x80)
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datah=1;
else
datah=0;
clkh=0;
delay(1);
clkh=1;
x=x*2;
}
strh=0;
delay(1);
strh=1;
}
void hien_thi2(unsigned int x)
{
int j,y;
for(j=0;j<=7;j++)
{
y=x;
y=y&0x80;
if(y==0x80)
datac=1;
else
datac=0;
clkc=0;
delay(1);
clkc=1;
x=x*2;
}
strc=0;
delay(1);
strc=1;
}
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void main()
{
int i;
while(1)
{
for(i=0;i<=7;i++)
{
hien_thi1(H[i]);
hien_thi2(C[i]);
}
}
}
4. LP TRNH GHP NI MA TRN PHM .
- Mc ch:Khi ngi dng nhn nt th hin th s ln led 7 on.
5. LP TRNH GHP NI KHI QUT LED N.
- Mc ch: Qut led sng tun t.
#include<regx52.h>
unsigned int M[8]={0xfe,0xfc,0xf8,0xf0,0xe0,0xc0,0x80,0x00};
void delay(unsigned int x)
{
unsigned int i;
for(i=0;i<=x;i++);
}
void main()
{
int i;
P2=0xff;
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while(1)
{
for(i=0;i<=7;i++)
{
P2=M[i];
delay(30000);
}
for(i=0;i<=5;i++)
{
P2=0xff;
delay(33000);
P2=0x00;
delay(33000);
}
}
}
GVHD: DNG TH HNG.
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Phn 3. KT LUN.
3.1. U IM CA MCH.
- Mch c thit k k khoa hc, cc khi c phn chia r rng d
quan st, p mt.
- C nhiu modul thng dng c kh nng khai thc ht ti nguyn ca
vi iu khin AT89S52.
- Thun tin cho sinh vin khi mi hc lp trnh cho vi iu khin thc
hnh hay m phng mt cch nhanh chng thun tin.
- Tch hp mch np qua chun ISP thun tin cho vic np chng
trnh cho AT89S52.
3.2. NHC IM.

- Kch thc ca mch cn kh ln v khi thit k tch bit cc modul
d dng nghin cu th nghim.
- Mch np theo chun ISP nn ch c th s dng c chp 89Sxx.
3.3. HNG CI THIN.

- Mch c th pht trin thm nhiu modul hn na c th ghp ni
v tn vi thit b ngoi.
- C th thit k SOCKET 40 chn c th np chip nhiu ch v
s dng c nhiu loi chip khac nhau.
GVHD: DNG TH HNG.
BO CO N TT NGHIP.
KHOA IN T.
61
TI LIU THAM KHO.
GVHD: DNG TH HNG.

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BO CO N TT NGHIP.

DANH MC K HIU, CH VIT TT.

SVTH: V TH BCH HNG _T5K10.

ROM: Read Only Memory.

RAM : Random Access Memory.

- SRAM: Static Random Access Memory.

EEPROM: Electrically Erasable Programmable Read-Only Memory.

CPU: Central Processing Unit.

- ALU : Arithmetic Logical Unit.

PSW: Program Status Worl.

UART: Universal Ansynchrous Receiver and Transmitter.

WDM: Watch Dog Timer .

RTC: Real Time Clock.

- ISP: In System Programmer.

SVTH: V TH BCH HNG _T5K10.

Hnh 1.1.1: S khi ca h 8051...........................................................................................8

SVTH: V TH BCH HNG _T5K10.

VK c kh nng x l nhiu hot ng phc tp m ch cn mt chip vi

SVTH: V TH BCH HNG _T5K10.

Phn III: U NHC IM CA TI.

H Ni, Thng 6 nm 2011.

Phn I: TNG QUAN V H VI IU KHIN

SVTH: V TH BCH HNG _T5K10.

ni tip v bn cng vo/ra song song ( rng 8 bit ) tt c u c t trn

1.1. Cu trc bus.

1.2. B nh chng trnh.

SVTH: V TH BCH HNG _T5K10.

y chnh l ni cha cc bin trung gian trong qu trnh hot ng ca chip.

2. GII THIU CHUNG V AT89S52.

GVHD: DNG TH HNG.

SVTH: V TH BCH HNG _T5K10.

AT89S52 dng ngun 1 chiu c di in p t 4v -5,5v c cp qua

2.1. S khi v chc nng cc khi ca h 8051.

Hnh 1.1.1: S khi ca h 8051.

* B vi iu khin AT89S52 gm cc khi chc nng sau y:

SVTH: V TH BCH HNG _T5K10.

+ B nh chng trnh( b nh ROM) gm 8 Kb Flash.

2.2. S chn v chc nng cc chn ca h 8051.

GVHD: DNG TH HNG.

SVTH: V TH BCH HNG _T5K10.

Hnh 1.1 .2: S chn ca h 8051.

2.2.1. Port 0( P0.0-P0.7).

GVHD: DNG TH HNG.

SVTH: V TH BCH HNG _T5K10.

Hnh 1.1.3: Cu trc Port 0.

Port 0 gm 8 chn , ngoi chc nng xut nhp Port 0 cn l bus a hp

Hnh 1.1.4: Cu trc Port 1.

SVTH: V TH BCH HNG _T5K10.

Hnh 1.1.5: Cu trc Port 2.

Port 2 ngoi chc nng l cng vo / ra nh Port 0 v Port 1 cn l byte

Hnh 1.1.6 : Cu trc Port 3.

Bng 1.1.1: Chc nng cc chn ca Port3.

SVTH: V TH BCH HNG _T5K10.

D liu nhn cho Port ni tip.

D liu truyn cho Port ni tip.

Xung ghi b nh d liu ngoi.

Xung c b nh d liu ngoi.

2.2.5. Chn /PSEN( Program Store Enable)

SVTH: V TH BCH HNG _T5K10.

Ng vo RST trn chn 9 l ng reset ca 8051. Khi tn hiu ny c

2.3. Hot ng nh thi.

GVHD: DNG TH HNG.

SVTH: V TH BCH HNG _T5K10.

0 trn cc chn T0 hoc T1 hoc T2 dng cc Timer tng ng m cc s