5

REVISIONS REV DESCRIPTION DATE APPROVED

PROTOTYPES

04-April-2002

B
D

PRODUCTION RELEASE UPDATE PER SPRS174G

07-June-2002 20-Jan-2003
D

The TM S320F2812 EzDSP design is based on preliminary information(SPRS174G) for the TM S320F2812 device. This schematic is subject to change without notification. Spectrum Digital Inc. assumes no liability for applications assistance, customer product design or infringement of patents described herein.
B B

DWN REVISION STATUS OF SHEETS CHK

A

DATE DATE
A

REV ENGR SH ENGR-MGR REV QA SH MFG REV SH C 1 C 2 B 3 C 4

5

DATE DATE DATE DATE DATE

SPECTRUM DIGITAL
Title TMS320F2812 EzDSP Size B Date:
3 2

C 5

C 6

NEXT ASSY APPLICATION

USED ON RLSE

Document Number 506262 Thursday, February 13, 2003 Sheet

1

Rev C 1 of 6

3.3V GND VDD3VFL

1.8V XA[0..18] XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XA16 XA17 XA18 XD[0..15]

31 64 81 114 145

23 37 56 75 100 112 128 143 154

69

U8

VDD3VFL

TAIYO YUDEN EMK325F106ZH-T

ADCREFM ADCREFP 10UF CERAMIC LOW ESR C35 10UF CERAMIC LOW ESR C36 R26 24.9K TP3

ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7

174 173 172 171 170 169 168 167 2 3 4 5 6 7 8 9 11 10 16 12 13 175 164

ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFP ADCREFM ADCRESEXT AVSSREFBG AVDDREFBG ADCLO ADCBGREFIN

VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5

VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10

XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XA16 XA17 XA18

18 43 80 85 103 108 111 118 121 125 130 132 138 141 144 148 152 156 158

AGND

XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15 XZCS0AND1n XZCS2n XZCS6AND7n XWEn XRDn XRnW XREADY XMP/MCn XHOLDn XHOLDAn XRSn X1/XCLKIN X2 XCLKOUT TESTSEL TEST1 TEST2 TRSTn TCK TMS TDI TDO EMU0 EMU1 GPIOF0-SPISIMOA GPIOF1-SPISOMIA GPIOF2-SPICLKA GPIOF3-SPISTEA GPIOF8-MCLKXA GPIOF9-MCLKRA GPIOF10-MFSXA GPIOF11-MFSRA GPIOF12-MDXA GPIOF13-MDRA

21 24 27 30 33 36 39 54 65 68 73 74 96 97 139 147 44 88 133 84 42 51 161 17 159 82 160 77 76 119 134 67 66 135 136 126 131 127 137 146 40 41 34 35 28 25 26 29 22 20 155 157 90 91 87 89 140

XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15 RN2A RN2B RN2C RN2D RN2E RN2F

VDD CORE - 1.8V

FLASH - 3.3V

VDD I/0 -3.3V

VDDA1 ADCBGREFIN

1 2 3 4 5 6

TP

A A A A A A

16 B 33 15 B 33 14 B 33 13 B 33 12 B 33 11 B 33

VREFLO

PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 T1PWM_T1CMP T2PWM_T2CMP CAP1_QEP1 CAP2_QEP2 CAP3_QEPI1 TDIRA TCLKINA C1TRIPn C2TRIPn C3TRIPn PWM7 PWM8 PWM9 PWM10 PWM11 PWM12 T3PWM_T3CMP T4PWM_T4CMP CAP4_QEP3 CAP5_QEP4 CAP6_QEPI2 TDIRB TCLKINB C4TRIPn C5TRIPn C6TRIPn T1CTRIP_PDPINTAn T2CTRIPn_EVASOCn T3CTRIP_PDPINTBn T4TRIPn_EVBSOCn XINT1n_XBIOn XINT2n_ADCSOC XNMIn_XINT3

92 93 94 95 98 101 102 104 106 107 109 116 117 122 123 124 45 46 47 48 49 50 53 55 57 59 60 71 72 61 62 63 110 115 79 83 149 151 150

GPIOA0-PWM1 GPIOA1-PWM2 GPIOA2-PWM3 GPIOA3-PWM4 GPIOA4-PWM5 GPIOA5-PWM6 GPIOA6-T1PWM_T1CMP GPIOA7-T2PWM_T2CMP GPIOA8-CAP1_QEP1 GPIOA9-CAP2_QEP2 GPIOA10-CAP3_QEPI1 GPIOA11-TDIRA GPIOA12-TCLKINA GPIOA13-C1TRIPn GPIOA14-C2TRIPn GPIOA15-C3TRIPn GPIOB0-PWM7 GPIOB1-PWM8 GPIOB2-PWM9 GPIOB3-PWM10 GPIOB4-PWM11 GPIOB5-PWM12 GPIOB6-T3PWM_T3CMP GPIOB7-T4PWM_T4CMP GPIOB8-CAP4_QEP3 GPIOB9-CAP5_QEP4 GPIOB10-CAP6_QEPI2 GPIOB11-TDIRB GPIOB12-TCLKINB GPIOB13-C4TRIPn GPIOB14-C5TRIPn GPIOB15-C6TRIPn GPIOD0-T1CTRIP_PDPINTAn GPIOD1-T2CTRIPn_EVASOCn GPIOD5-T3CTRIP_PDPINTBn GPIOD6-T4CTRIPn_EVBSOCn 14 VDDA1 166 VDDA2 15 VSSA1 165 VSSA2 GPIOE0-XINT1_XBIOn GPIOE1-XINT2_ADCSOC GPIOE2-XNMI_XINT13

XZCS0AND1n XZCS2n XZCS6AND7n XWEn XRDn XRnW XREADY XMP_MCn XHOLDn XHOLDAn XRSn X1_CLKIN XCLKOUT XTESTSEL

C28_TRSTn C28_TCK C28_TMS C28_TDI C28_TDO C28_EMU0 C28_EMU1 SPISIMOA SPISOMIA SPICLKA SPISTEA MCLKXA MCLKRA MFSXA MFSRA MDXA MDRA SCITXDA SCIRXDA SCITXDB SCIRXDB CANTXA CANRXA XF_XPLLDISn

SINGLE POINT CONNECTION

TP2 AGND

L4 1.8V BLM21P221SN C2 1uF C58 .1uF C56 .001uF

ADC

GPIOF4-SCITXDA GPIOF5-SCIRXDA GPIOG4-SCITXDB GPIOG5-SCIRXDB

( 1.8V )

VDD1

1.8V

1 VDDAIO 176 VSSAIO

GPIOF6-CANTXA GPIOF7-CANRXA VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 GPIOF14-XF-XPLLDISn

19 32 38 52 58 70 78 86 99 105 113 120 129 142 153

3.3V

L3

162 VDD1 163 VSS1

( 3.3V )
BLM21P221SN C3 1uF C57 .1uF C38 .1uF

VDDA1 C37 .001uF

TMS320F2812PGF

DSP
Title TMS320F2812 EzDSP Size B Date: Document Number 506262 Thursday, February 13, 2003 Sheet
1

LOCATE NEAR DSP

Rev C 2 of 6

XA[0..18]
C

XD[0..15]

3.3V

ASRAM
11 33 U4 XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15 VDD1 VDD2

3.3V C22 0.1uF 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 C10 0.1uF

XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XA16 XA17 XZCS6AND7n XWEn XRDn

1 2 3 4 5 18 19 20 21 24 25 26 27 42 43 44 22 23 6 17 41 40 39

A0 A1 A2 A3 A4 A5 A6 A7 A8 A11 A12 A13 A14 A15 A16 A17 A9 A10 CS WE OE

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

NC

28

64Kx16 and 256Kx16 Compatible

12 34

IS61LV6416-12T

VSS1 VSS2

BHE BLE

Title TMS320F2812 EzDSP GND Size B Date:

5 4 3 2

Document Number 506262 Thursday, February 13, 2003 Sheet

1

Rev B 3 of 6

JP5 3.3V B 3 C A 1 JUMPER3_SMT 2 +5V

Make a solder connection on JP4 and/or JP5 to the appropriate power supply.

3.3V 3

JP4 +5V C A 1 JUMPER3_SMT 2

P2 XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 XA0 XA2 XA4 XA6 XA8 XA10 XA12 XA14 XZCS0AND1n XREADY XRnW XWEn 3.3V DSP_RSn DSP_RSn
C

XA16 XA18 XHOLDAn

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

P8 XD1 XD3 XD5 XD7 XD9 XD11 XD13 XD15 XA1 XA3 XA5 XA7 XA9 XA11 XA13 XA15 ISn STRBn XZCS2n XRDn XNMIn_XINT3 SCITXDA XINT1n_XBIOn CAP2_QEP2 PWM1 PWM3 PWM5 T1PWM_T1CMP TDIRA 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SCIRXDA CAP1_QEP1 CAP3_QEPI1 PWM2 PWM4 PWM6 T2PWM_T2CMP TCLKINA

SPISIMOA SPICLKA CANTXA XCLKOUT PWM8 PWM10 PWM12 T1CTRIP_PDPINTAn

XINT1n_XBIOn SPISOMIA SPISTEA CANRXA PWM7 PWM9 PWM11 CAP4_QEP3 T3CTRIP_PDPINTBn

TMS320F2812 supports 3.3V input/output levels which are NOT 5V tolerant. Connecting the eZdsp to a system with 5V input/output levels will damage the TMS320F2812. If the eZdsp is connected to another target then the eZdsp must be powered up first and powered down last to prevent latchup conditions.

XF_XPLLDISn
PLLDISn

3.3V

R42 R41

10K 2.2K

1 3

JP9 2

3.3V DS2 LTST-C150GKT GREEN C62 .1uF 5

JUMPER3B 3.3V U12

R43 SN74AHC1G14 4 220 XF

2
XF

3.3V
XTESTSEL

XTESTSEL XA17 XHOLDn XINT2n_ADCSOC MCLKXA MCLKRA MFSXA MFSRA MDXA MDRA ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 VREFLO CAP5_QEP4 CAP6_QEPI2 T3PWM_T3CMP T4PWM_T4CMP TDIRB TCLKINB XF_XPLLDISn SCITXDB SCIRXDB P4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P7 1 2 3 4 5 6 7 8 9 10 C1TRIPn C2TRIPn C3TRIPn T2CTRIPn_EVASOCn C4TRIPn C5TRIPn C6TRIPn T4TRIPn_EVBSOCn 1 3 JUMPER3B R39 R36 10K 2.2K 1 3 JUMPER3B
BOOT MODE
C

JP1 XMPNMC 2

XMP_MCn

HEADER 30X2

JP12 2

BOOT-0

SPICLKA

P9 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20

R38 R35

10K 2.2K

1 3

JP11 2

BOOT-1

SPISTEA

JUMPER3B R40 R37 10K 2.2K 1 3 JUMPER3B JP8 2

BOOT-2

MDXA

P5 1 2 3 4 5 6 7 8 9 10 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFM ADCREFP

Connect VREFLO to AGND or to VREFLO of target system for proper ADC operation.

R31 R30 L1 3.3V

10K 2.2K

1 3

JP7 2

BOOT-3

SCITXDA

JUMPER3B

1.8V BLM21P221SN C43 U14 5 0.1uF U11 8 2 JP3 C 3 100 C42 33 pF

SMT/4PIN DIP

BOOT-3 SCITXDA

BOOT-2 MDXA

BOOT-1 SPISTEA

BOOT-0 SPICLKA

MODE

1 0

X 1 0 0 0 0

X X 1 1 0 0

X X 1 0 1 0

FLASH SPI SCI H0 OTP PARALLEL

A

Tie off unused F24xx compatible signals.

R6 ISn 10K
A

R1 X1_CLKIN 4 100

SN74LVC1G14 2 R29 5 1

VCC CLK

OFFn GND

1 4

0 0 0 0

3.3V R5

JUMPER3_SMT

NO-POP

STRBn 10K GND GND

Schematic change from version A/B to C. F2812 clkin is 1.8V input.

MCLK AGND

OPTIONAL
Title TMS320F2812 EzDSP Size B Document Number 506262
2 Thursday,

Rev C Sheet 4
1

Date:

February 13, 2003

of

R16 U5 XPPD7 XPPD6 XPPD5 XPPD4 XPPD3 XPPD2 XPPD1 XPPD0 RN4A RN4B RN4C RN4D RN4E RN4F RN4G RN4H 1 2 3 4 5 6 7 8 A A A A A A A A B B B B B B B B 16 15 14 13 12 11 10 9 33 33 33 33 33 33 33 33 PPBUSENn PPBUSDIR 2 3 4 5 6 7 8 9 19 1 A1 A2 A3 A4 A5 A6 A7 A8 G DIR B1 B2 B3 B4 B5 B6 B7 B8 VCC GND
D

18 17 16 15 14 13 12 11 20 10

RN3A RN3B RN3C RN3D RN3E RN3F RN3G RN3H 5V C50

1 2 3 4 5 6 7 8

A A A A A A A A

B B B B B B B B

16 15 14 13 12 11 10 9

33 33 33 33 33 33 33 33

C52 33pf C54 33pf C33 C53 33pf

R14 R13

10K 10K 10K

C55 33pf C32 33pf C29 33pf P3 DB25_SHIELD PPSLCT PPPE PPBSY PPACKn PPD7 PPD6 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 A PPTRSTn P1 PPTMS PPTDI 5V PPTDO PPTCK PPEMU0 1 3 5 7 9 11 13 2 4 6 8 10 12 14 3.3V R17 10K EMUOFF
D

C51 .001uF

33pf C31 33pf

.1uF 74ABT245PW U2 XPPS4 XPPS5 XPPS7n XPPS3 2 3 4 5 6 7 8 9 5V 19 1 A1 A2 A3 A4 A5 A6 A7 A8 G DIR B1 B2 B3 B4 B5 B6 B7 B8 VCC GND 74ABT245PW 18 17 16 15 14 13 12 11 20 10

RN1A RN1B RN1C RN1D RN1E RN1F RN1G RN1H 5V C27

1 2 3 4 5 6 7 8

A A A A A A A A

B B B B B B B B

16 33 15 33 14 33 13 33 12 33 11 33 10 33 9 33

HEADER 7X2 PPEMU1 XDS510PP EMULATION HEADER

C28 PPD5 .001uF PPD4 PPD3 PPSELn PPD2 PPINITn PPD1 PPERRn PPD0 PPALEn PPSTRBn

.1uF

PPEMU0/1 CONNECT DIRECTLY TO F2812 FOR EMULATOR WAIT-IN-RESE T SUPPORT

XPPC3n XPPC2 XPPC1n XPPC0n

PONRSnIN B XTRSTn PLACE NEAR EACH MOUNTING HOLE 3.3V XTDO R19 R47 C16 1M .001uF 1M C67 .001uF R11 R12 10K 10K R22 10K TPOWLOSSn XTCK XEVNT0 XEVNT1 XTMS XTDI

PONRSnIN C28_TRSTn C28_TMS C28_TDO C28_TDI C28_TCK

C

CROSS COUPLE IN T O OUT

C28_EMU0 C28_EMU1

R20 100 R25 100 R24 100 R15 R8 R10 R9 33 33 33 XTCK PPTCK PPTDO R18 100 100 C34 33pf C30 33pf C15 33pf C17 33pf 3.3V

100 XEVNT0 99 98 XTRSTn 97 PPTRSTn 96 IPPTCK 95 XTDI 94 93 IPPTDO 92 GND 91 FPGA_VCCA 90 VCCR 89 XTCKI 88 GND 87 JCLK 86 XTMS 85 PPTMS 84 XTDO 83 3.3V 82 PPTDI 81 80 79 78 77 EMUOFF 76

C14 0.1uF

C25 0.1uF

C26 0.1uF

C49 0.1uF

Locate R7,R54, C70 at the DSP XRSn pin for best EMI/ESD noise immunity. 3.3V 3.3V U6 XRSn is logical AND of PONRSnIN and emulator controlled reset. Power on default is PONRnIN controls XRSn. R54 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DSP_RSn GND GND 3.3V GND GND FPGA_VCCA C70 22nF
OPEN-DRAIN

R49 0 U13 1 2 IN GND EN NC/FB 4 41.2K 1% OUT 5 FPGA_VCCA R50 C45 0.1uF C23 0.1uF C24 0.1uF C11 0.1uF C68 1uF

RSV13_TCK_IO XEVNT0 PPEMU0 XTRSTn PPTRSTn PPTCK XTDI PPTDO RSV11_PRA_IO GND VCCA VCCR_NC XTCKI RSV10 JCLK XTMS PPTMS XTDO VCCI PPTDI ODEMU0n ODEMU1n ODEMU0_SRC ODEMU1_SRC EMUOFF_1

R7 1.5K 100

GND 3.3V R23 10K 3.3V GND XPPD0 XPPD1 XPPD2 XPPD3 XPPD4 XPPD5 XPPD6 XPPD7 3.3V XPPS3 XPPS4 XPPS5 XPPS7n 3.3V XEVNT1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

PPBUSENn RSV6 PPBUSDIR RSV7 XPPC3n XPPC2 XPPC1n XPPC0n RSV8_PRB_IO VCCA GND VCCR_NC ALT_MCLK HCLK RSV9 PONRSn TPOWLOSSn VFUNC_EN VCCI EXT_VER7 EXT_VER6 EXT_VER5 EXT_VER4 EXT_VER3 EXT_VER2

GND RSV1_TDI_IO EMUOFF XEVNT1 PPEMU1 RSV2 RSV3_TMS_IO VCCI GND XPPD0 XPPD1 XPPD2 XPPD3 XPPD4 XPPD5 XPPD6 XPPD7 RSV4 RSV5 VCCI XPPS3 XPPS4 XPPS5 XPPS6 XPPS7n

SPECTRUM DIGITAL INC. EMBEDDED PP JTAG CONTROLLER 506053-0001B

EXT_VER 0011 0-001

DSP_RSn MCLKOUT MCLKOUTEN MCLKOUT2 MCLKOUT2EN EXTERN_RSTn GND GND VCCA XBITOUT0 XBITOUT1 XBITOUT2 XBITOUT3 XBITIN0 XBITIN1 XBITIN2 XBITIN3 VCCI VCCA VBUS_ENn VPOWER_BLEED VPOWER_ONn EXT_VER0 EXT_VER1 GND

XRSn IF U13 IS INSTAL LED THEN REMOVE R49 AN D R48.

TPS72201

R51 DSP_RSn To/from expansio n header +5V 40.2K 1%

GND GND GND GND 3.3V FPGA_VCCA

R48 VCCR 0 C47 0.1uF C13 0.1uF

3.3V GND GND

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

L2 506053-0001B

3.3V

FPGA_VCCA GND VCCR ALT_MCLK MCLK

PPBUSENn

PONRSnIN TPOWLOSSn GND 3.3V GND GND 3.3V 3.3V GND GND

PPBUSDIR

XPPC3n XPPC2 XPPC1n XPPC0n

BLM21P221SN C48 0.1uF 5V 3.3V GND 1 4 Title TMS320F2812 EzDSP C46 30 MHz Size C Date:
3 2

+5V 3.3V

U10 8 R32 MCLK 5 33 CLK GND VCC OFFn

GND

NO-POP CBLV-3C-30 .000

5 4

Document Number 506262 Thursday, February 13, 2003

1

Rev C Sheet 5 of 6

+5V P6 5 6 C66 +5V Max R44 220 + CT2 47uF 1.8VONn 0.1uF 3
D

U9 1IN 1IN 1EN 1GND 22 1RESET 1OUT 1OUT 1FB/SENSE 28 23 24 25

18.2K 1.899V 16.9K 1.848V 15.0K 1.773V 13.7K 1.722V

1.8V R33 16.9K, 1% R45 30.1K, 1% 3.3V C64 + CT3 22uF 0.1uF
D

DS1 LTST-C150GKT GREEN

11 12 C65 10 0.1uF R46 10K 3.3V 9 1 2 7 8 13 14 D Q3 BSS138

2IN 2IN 2EN 2GND THERMAL_PAD NC NC NC NC NC NC TPS767D301

2RESET 2OUT 2OUT 2SENSE

17 18 19 C63 + CT4 22uF 0.1uF R52 0 3.3V C1 1uF C7 .1uF VDD3VFL

U16 1 2 CT VDD GND RESETn 3

C

R53 5 1.5K 1% 4 R34 2.0K 1% G S

NC NC NC NC NC NC

15 16 20 21 26 27

R2 10K TIE TPS767D301 POWER PAD TO GND PLANE (TI-SLMA002) PONRSnIN

C

MRn TPS3838K33DBV

RESETn of TPS3838 is open-drain. U16 was added for testing but not populated on production boards.

1.8V + +

CT6 22uF

CT5 22uF

C19 0.1uF

C18 0.1uF

C5 0.1uF

C8 0.1uF

C21 0.1uF

C41 0.1uF

C40 0.1uF

C61 0.1uF

C59 0.1uF

3.3V
B B

CT1 22uF

C20 0.1uF

C6 0.1uF

C9 0.1uF

C39 0.1uF

C60 0.1uF 1 TP1 GND GND

POWER ON SEQUENCE NOTES 3.3V THEN 1.8V PONRSnIN, GOES HIGH > 200ms AFTER ALL POWER IS STABLE. SET Q3 TO TURN ON WHEN 3.3V SUPPLY IS GREATER THEN 2.2 VOLTS. REGULATOR TURN ON DELAY AND RAMP RATE WILL ENSURE THAT 3.3V SUPPLY IS AT 2.5 VOLTS OR HIGHER BEFORE THE 1.8V SUPPLY REACHES 0.3 VOLTS. U16 WILL TURN OFF THE 1.8V SUPPLY WHEN INPUT POWER FALLS BELOW 2.94V. THIS SPEEDS UP THE 1.8V SUPPLY TURN OFF. PONRSnIN 3.3V SUPPLY, VDDIO VDD3VFL, VDDA1,VDDA2 2.2V Q3

TPS767D301 RATINGS MAX Iout PER CHANNEL IS 1A TPS767D301 PD = (Vin-Vout)*Iout VOLTAGE SUPPLY 1.8V SUPPLY 1.8V 3.3V 140ms-280ms PD(max) = (Tj(max) - Ta)/Rja Title = (125 - 35)/27.9 = 3255mW Size B Date:
2

MAX CURRENT 333mA 307mA

TPS767D301 PD 1065mW 521mW 1586mW Total

A

TMS320F2812 EzDSP Document Number 506262 Thursday, February 13, 2003 Sheet
1

Rev C 6 of 6