Bn trong kin trc Pentium M.

Trong hng dn ny, chng ti s gii thiu n cc bn cch CPU Pentium M lm vic nh th no di cch d hiu nht. T khi tt c cc CPU mi ca Intel s dng kin trc Pentium M, vic nghin cu kin trc ny l mt vic quan trng t bn c th hiu su c kin trc ca cc CPU Core Solo hay Core Duo (Yonah) v cng hiu c lp nn tng cho vic tin ti kin trc li siu nh (Core microarchitecture), c s dng bi cc CPU Merom, Conroe v Woodcrest. Trong hng dn ny, bn s bit c kin trc ca n lm vic th no t c th so snh c vi cc b vi x l khc n t Intel cng nh t cc i th cnh tranh khc nh AMD. Pentium M c xy dng da trn kin trc th h th 6 ca Intel, cng c s dng trong cc CPU Pentium Pro, Pentium II v Pentium III, tuy nhin li khng trn Pentium 4 nh nhiu bn ngh, mc ch ca n nhm vo cc my tnh di ng. Bn c th ngh Pentium M nh mt Pentium III c nng cao. Nhng cn ch khng nhm ln Pentium M vi Pentium III. Trong mt bi khc chng ti s gii thiu cho cc bn v tt c cc Model ca Pentium M c pht hnh cho n thi im hin nay. i khi Pentium M cn c gi l Centrino. Qu thc n c th c gi nh vy khi bn c mt laptop CPU Pentium M, chipset Intel 855 hay 915 v Intel/PRO wireless LAN. Chnh v vy nu bn c mt laptop c xy dng trn Pentium M m khng c nhng iu kin b sung nh trn th khng th c coi l Centrino. Trong hng dn ny chng ti s gii thiu c bn cho cc bn v cch kin trc P6 lm vic nh th no v nhng im g mi khi so snh Pentium M vi Pentium III. Cng v vy m trong hng dn ny bn s bit thm c v cch lm vic ca cc CPU Pentium Pro, Pentium II, Pentium III v Celeron (chng cng chnh l cc m hnh da trn P6, ngha l slot 1 v socket 370). Trong bi ny, chng ti s khng gii thiu mt cch c bn v cch lm vic ca cc CPU, tm hiu thm bn c th c bi ny. Trong hng dn ny, chng ti tha nhn rng bn c mt cht kin thc v cch lm vic ca cc CPU.

Trc khi tip tc, chng ta hy xem xt n s khc nhau gia cc CPU Pentium M v Pentium III: Nhn bn ngoi, Pentium M lm vic ging nh Pentium 4, truyn ti 4 d liu trn mt chu k clock. K thut ny c gi l QDR (Quad Data Rate Gp bn ln tc d liu) v lm cho bus ni b c hiu sut tng gp 4 ln vi tc clock thc ca n, bn c th xem bng di y. Clock thc 100 MHz 133 MHz

Hiu sut 400 MHz 533 MHz

Tc truyn 3.2 GB/s 4.2 GB/s

L1 memory cache: Hai L1 memory cache 32 KB, mt cho d liu v mt cho ch lnh (Pentium III c hai L1 memory cache16 KB). L2 memory cache: 1 MB trn cc m hnh 130 nm (li Banias) hay 2 MB trn cc m hnh 90 nm (li Dothan). Pentium II ch c n 512 KB. Celeron M, phin bn r tin nht ca Pentium M cng c 512 KB L2 memory cache. H tr cho cc ch lnh SSE2. D bo nhnh cao cp: D bo nhnh c thit k li (v c da trn mch ca Pentium 4) ci thin hiu sut. S hp nht nhiu hot ng nh: B gii m ch lnh hp nht c hai hnh ng nh thnh mt c th tit kim c nng lng v ci thin hiu sut. Chng ta s ni k hn v vn ny phn di. Cng ngh SpeedStep nng cao, y l cng ngh cho php cc CPU c th gim c clock trong ch nhn ri tit kim thi gian sng ca pin. Mt s tnh nng nhm tit kim cho pin cng c b sung vo kin trc siu nh ca Pentium M, v mc ch ca cc CPU ny ban u c thit k cho my tnh di ng.

By gi chng ta hy i xem xt su hn v kin trc ca Pentium M. Nguyn l ca Pentium M Nguyn l l mt danh sch tt c cc tng m ch lnh cho phi c thc thi theo ng thut ton. Intel khng tit l cc nguyn l ca

Pentium M, chnh v vy chng ti s ni v nguyn l ca Pentium III. Nguyn l ca Pentium M c th s c nhiu tng hn so vi Pentium III nhng vic phn tch n s cho chng ta c c tng v kin trc ca Pentium M lm vic nh th no. Hy nh rng, nguyn l lm vic ca Pentium 4 c n 20 tng v nguyn l lm vic ca cc CPU Pentium 4 mi hn c da trn li Prescott c n 31 tng. Trn hnh 1 bn c th thy c nguyn l 11 tng ca Pentium III

Hnh 1: Nguyn l ca Pentium III Di y chng ti s gii thch mt cch c bn v mi tng, gii thch s lm sng t cch mi ch lnh c gn c thc hin nh th no bi cc b vi x l lp P6. iu ny s khng qu phc tp nh bn ngh. y ch l tm tt v nhng gii thch c th d hiu s c chng ti a ra bn di.

IFU1: Np mt dng (32 byte tng ng vi 256 bit) t ch lnh L1 cache v lu n vo trong b m lung ch lnh (Instruction Streaming Buffer).

IFU2: Nhn dng cc ch lnh ng bin (16byte tng ng vi 128bit). V cc ch lnh x86 khng c mt chiu di c nh nn tng ny nh du v tr m mi ch lnh bt u v kt thc bn trong 16byte c np. Nu c bt k nhnh no bn trong 16byte th a ch c n s c lu ti Branch Target Buffer (BTB), chnh v vy CPU c th s dng nhng thng tin ny sau trn mnh tin on nhnh ca n. IFU3: nh du n v gii m ch lnh ca mi ch lnh phi c gi. C ba khi gii m ch lnh khc nhau m chng ta s cp n chng trong phn di. DEC1: Gii m ch lnh x86 thnh nhng ch lnh nh RISC (cc hot ng nh). V CPU c n 3 b gii m ch lnh nn n c th gii m c n 3 ch lnh cng lc. DEC2: Gi cc ch lnh nh va c gii m vo hng i ch lnh gii m (Decoded Instruction Queue), hng i ny c kh nng lu tr c n 6 ch lnh nh. Nu ch lnh c chuyn i nhiu hn 6 ch lnh nh th tng ny cn phi c lp li khng b st chng. RAT: V kin trc P6 thc hin vic thi hnh out-of-order (khng tun theo th t, vit tt l OOO), nn gi tr ca thanh ghi cho c th c thay i bi mt ch lnh c thc thi trc v tr chng trnh din ra, sa d liu cn thit cho ch lnh khc. Chnh v vy gii quyt c kiu xung t ny, ti tng ny, thanh ghi gc c s dng bi ch lnh s c thay i thnh 40 thanh ghi bn trong m kin trc siu nh m P6 c. ROB: Ti tng ny, ba ch lnh nh c gii m s np vo Reorder Buffer (ROB). Nu tt c d liu u cn thit cho vic thc thi ca mt ch lnh nh c cung cp v nu c mt khe m ti hng i ch lnh gii m Reservation Station th ch lnh ny s c chuyn vo hng i ny. DIS: Nu ch lnh gii m ny li khng c gi n hng i trn th n c th c thc hin ti tng ny. Ch lnh gii m s c gi n khi thc thi thch hp. EX: Ch lnh c gii m s c thc thi ti khi thc thi ny. Mi mt ch lnh gii m ny ch cn mt chu k xung nhp c thc thi. RET1: Kim tra ti b m Reorder Buffer xem c bt k ch lnh gii m no c nh du nh thc thi khng. RET2: Khi tt c cc ch lnh gii m c lin quan n ch lnh x86 thc s c xa ht khi b m Reorder Buffer v tt c cc ch

lnh nh ( c gii m) c lin quan vi ch lnh x86 hin hnh c thc thi, th cc ch lnh ny s c xa khi b m Reorder Buffer v cc thanh ghi x86 s c nng cp (tin trnh c quay tr v tng RAT). Tin trnh tr li lm vic phi c thc hin theo th t. Ba ch lnh gii m c th c xa khi b m Reorder Buffer trong mi mt chu k clock. Di y chng ti s gii thu cc thng tin chi tit hn cc bn d hiu c hot ng ca n. Memory Cache v Khi tm np Nhng chng ti cp t trc, L2 memory cache ca Pentium M c th l 1 MB trn cc m hnh 130 nm (li Banias) hay 2 MB trn cc m hnh 90 nm (li Dothan). Trong khi n c hai memory cache L1, mt ci l 32KB cho ch lnh v ci kia l 32KB cho d liu. Nh gii thch phn trc, khi tm np c chia thnh 3 tng. Trong hnh 2, bn c th xem c cch khi tm np lm vic nh th no.

Hnh 2: Khi tm np Khi tm np np dng th nht (32 bytes = 256 bits) vo b m lung ch lnh ca n (Instruction Streaming Buffer). Sau b gii m chiu di ch lnh s nhn ra cc ranh gii ch lnh bn trong mi 16byte. V ch lnh x86 khng c chiu di c nh nn tng ny s nh du v tr mi ch lnh bt u v kt thc bn trong 128bit c np. Nu c mt ch lnh nhnh no bn trong 128 bit th a ch s c lu vo Branch Target Buffer (BTB), chnh v vy CPU ca bn c th s dng cc thng tin ny sau trn mnh d bo nhnh ca n. BTB c 512 u vo. Sau khi tng Decoder Alignment Stage nh du khi gii m ch lnh no th mi ch lnh s c gi i. C 3 khi gii m ch lnh khc nhau m chng ti s gii thiu phn di y. Gii m ch lnh v thay i tn cho thanh ghi

V kin trc P6 s dng cho cc b vi x l Pentium Pro kin trc CISC/RISC lai nn b vi x l phi chp nhn cc ch lnh CISC v cng c bit n vi t cch l cc ch lnh x86, iu ny l do tt c cc phn mm cung cp ngy nay u c vit bng kiu ch lnh ny. CPU ch s dng RISC khng phi l to ra cho my tnh, v n khng chy phn mm hin nay nh Windows v Office. V vy, gii php c s dng bi tt c cc b vi x l hin ang cung cp trn th trng ngay nay t c Intel v AMD l u s dng gii m CISC/RISC. Bn trong, CPU x l cc ch lnh RISC nhng front-end ca n li ch chp nhn cc ch lnh CISC x86. Cc ch lnh CISC x86 c cp n nh ch lnh thng thng cn cc ch lnh RISC bn trong c cp n nh cc ch lnh c gii m. Mc d vy, cc ch lnh c gii m RISC khng th c truy cp mt cch trc tip, do chng ta khng th to phn mm da trn cc ch lnh ny vng trnh qua b gii m. Cng vy, mi CPU s dng cc ch lnh RISC ca ring n, cc ch lnh ny khng c cng b v khng tng thch vi ch lnh gii m t cc CPU khc. iu c ngha l cc ch lnh gii m ca Pentium M khc hon ton vi ch lnh gii m ca Pentium 4, s khc bit ny chnh l t cc ch lnh gii m Athlon 64. Ph thuc vo phc tp ca ch lnh x86 m n phi c chuyn thnh cc ch lnh gii m RISC. B gii m ch lnh Pentium M lm vic ging nh trn hnh 3. Nh nhng g bn c th quan st thy, c ba b gii m v mt b xp dy ch lnh gii m (MIS). Hai b gii m c ti u ha cho cc ch lnh n gin, trong cc ch lnh n gin l ch lnh thng ch l mt ch lnh gii m. Kiu ch lnh ny c chuyn i nh mt ch lnh gii m. Mt b gii m c ti u ha cho cc ch lnh x86 phc tp, ch lnh ny c th c chuyn i thnh 4 ch lnh gii m. Nu ch lnh x86 qu phc tp, c ngha l n chuyn i ti hn bn ch lnh gii m th n s c gi n MIS l b nh ROM, gm c mt danh sch cc ch lnh c th c dng thay th cho x86 trn.

Hnh 3: B gii m v i tn thanh ghi B gii m ch lnh c th chuyn i ln n 3 ch lnh x86 trn mi mt chu k clock, mt b gii m phc tp Decoder 0 v hai b gii m n gin 1 v 2, iu ny lm cho chng ta c cm gic hng i ch lnh c gii m (Decoded Instruction Queue) c th ln n 6 ch lnh gii m trn mi chu k clock, kch bn c th khi Decoder 0 gi 4 ch lnh gii m v hai b gii m kia gi mi b mt ch lnh c gii m hoc khi MIS c s dng. Cc ch lnh x86 phc tp s dng (MIS) Micro Instruction Sequencer c th d chm mt s chu k clock khi gii m, iu ph thuc vo s lng ch lnh c gii m s to ra t s chuyn i. Bn cn nn lu rng Decoded Instruction Queue ch c th gi c n 6 ch lnh gii m, chnh v vy nu c hn 6 ch lnh gii m c sinh ra bi b gii m cng vi MIS th mt chu k khc s c s dng gi cc ch lnh hin hnh trong hng i ti Register Allocation Table (RAT), lm trng hng i v chp nhn cc ch lnh gii m m khng ph hp vi n trc . Pentium M s dng mt khi nim mi i vi kin trc P6, khi nim ny c gi l hp nht ch lnh gii m. Trn Pentium M, mi mt b gii m ni hai ch lnh gii m thnh mt. Chng s ch c tch ra khi c thc thi, ti tng thc thi. Trn kin trc P6, mi ch lnh c chiu di 118 bit. Pentium M thay v lm vic vi cc ch lnh 118bit, n lm vic vi cc ch lnh c chiu di 236bit m chnh l kch thc ni ca hai ch lnh 118bit.

Bn cn phi lu rng cc ch lnh gii m lin tc c chiu di l 118bit, cn nhng g c thay i l chng c truyn ti thnh mt nhm gm hai ch lnh c bn ny. tng ng sau phng php ny l tit kim nng lng v tng hiu sut. Vic gi mt ch lnh c kch thc 236bit di s nhanh hn vic gi hai ch lnh 118bit. Thm vo , CPU s tiu tn t ngun in hn v s c t ch lnh gii m lu thng bn trong n. Cc ch lnh c gn sau s gi n bng Register Allocation Table (RAT). Kin trc CISC x86 ch c 8 thanh ghi 32bit l EAX, EBX, ECX, EDX, EBP, ESI, EDI v ESP. S lng ny l qu thp v cc CPU hin i c th thc thi m out-of-order, v n s ph hng ni dung bn trong thanh ghi c, t gy ra hng cc chng trnh. Chnh v vy, ti tng ny, b vi x l thay i tn v ni dung ca cc thanh ghi c s dng bi chng trnh thnh mt trong 40 thanh ghi bn trong c (mi mt thanh ghi ny c 80 bit rng, nh vy vic chp nhn c d liu nguyn v d liu thay i), cho php ch lnh c th chy ti cng mt thi im vi ch lnh khc m s dng cng cng mt thanh ghi chun, hoc thm ch out-of-order, c ngha l cho php ch lnh th hai c th chy trc ch lnh th nht d l chng cng chung trn mt thanh ghi. B m Reorder Buffer Khi cc ch lnh x86 v ch lnh c gii m c kt qu truyn ti gi cc tng CPU theo cng mt th t th chng s xut hin trn chng trnh ang chy. Khi vo ROB, cc ch lnh gii m c th c np v thc thi out-oforder bi cc khi thc thi. Sau khi thc thi, cc ch lnh c gi tr li v Reorder Buffer. Sau ti tng cui cng (Retirement), cc ch lnh thc thi c xut ra khi b m Reorder Buffer vi cng th t m chng np vo, c ngha l chng c chuyn theo th t. Trn hnh 4, bn c th c c tng v cch chng lm vic nh th no.

Hnh 4: Cch lm vic ca b m Reorder Trn hnh 4, chng ta n gin ha trm dnh ring (Reservation Station) v cc khi thc thi c th to s d hiu cho b m ny. Chng ta s ni v hai tng ny su hn na phn di. Reservation Station v cc khi thc thi Nh chng ta cp t trc, Pentium M s dng cc ch lnh c ni (thng l hai ch lnh c ni vi nhau) t khi gii m n v tr cc cng gi i c t trn Reservation Station. Reservation Station gi i cc ch lnh gii m mt cch ring bit ( tch ghp i). Pentium M c 5 cng nh vy, cc cng ny c nh s t 0 n 4 trn Reservation Station. Mi cng c kt ni n mt hoc nhiu khi thc thi, cc bn c th xem trn hnh 5.

Hnh 5: Reservation Station v cc khi thc thi Di y l gii thch vn tt v mi khi thc thi c trn CPU ny:

IEU: Instruction Execution Unit Khi thc thi ch lnh l ni cc ch lnh thng c thc thi. Cng c bit n trong cc sch gii thiu v cu trc my tnh vi tn ALU (Khi logic s hc Arithmetic and Logic Unit). Cc ch lnh thng thng ny cng c hiu l cc ch lnh integer. FPU: Floating Point Unit l ni cc ch lnh ton hc phc tp c thc thi. Trc kia, khi ny cng c tn gi l math co-processor khi ng x l ton hc. SIMD: l ni cc ch lnh SIMD c thc thi, ngha l MMX, SSE v SSE2. WIRE: Cc hm phc tp JEU: Jump Execution Unit x l cc nhnh v cng c bit n l Branch Unit. Shuffle: Khi ny thc thi mt loi ch lnh ca SSE c tn gi l shuffle.

PFADD: Thc thi mt ch lnh SSE c tn gi PFADD (Packed FP Add) v c cc ch lnh COMPARE, SUBTRACT, MIN/MAX v CONVERT. Khi ny c cung cp ring, chnh v vy n c th bt u vic thc thi mt ch lnh gii m mi mi chu k clock d l n khng hon tt c s thc thi ca ch lnh gii m trc. Khi ny c mt tr ba chu k clock, ngha l n s gi chm 3 chu k clock i vi mi ch lnh c x l. Reciprocal Estimates: Thc thi hai ch lnh SSE, mt c gi l RCP (Reciprocal.Estimate) v mt gi l RSQRT (Reciprocal Square Root Estimate). Load: Khi ny dng x l cc lnh hi d liu c c t b nh RAM. Store Address: Khi x l cc ch lnh hi d liu c ghi ti b nh RAM. Khi ny cng c tn gi l AGU, Address Generator Unit. Kiu ch lnh ny s dng c hai khi Store Address v Store Data ti cng mt thi im. Store Data: X l cc ch lnh hi d liu ghi vo b nh RAM. Loi ch lnh ny s dng c hai khi Store Address v Store Data ti cng mt thi im.

Bn cn phi nh rng cc ch lnh phc tp c th mt n vo chu k clock c x l. Chng ta hy ly mt v d ca cng 0, ni m khi floating point unit (FPU) c mt . Trong khi khi ny ang x l mt ch lnh rt phc tp, mt n vi clock thc thi th cng 0 s khng ngng hot ng: n lun lun gi cc ch lnh n gin n IEU mc d khi FPU li ang rt bn. Chnh v vy, mc d tc gi i ln nht l 5 ch lnh gii m trn mi mt chu k clock, nhng thc t CPU c th tng ln n 12 ch lnh gii m ti cng mt thi im. Nh chng ti cp t trc, cc ch lnh yu cu CPU c th c d liu c lu tr ti a ch RAM cho, Khi lu tr a ch (Store Address Unit) v lu tr d liu (Store Data Unit) c s dng ti cng mt thi im, mt dng cho nh a ch v mt dng cho c d liu. y l l do ti sao cng 0 v cng 1 c nhiu khi thc thi. Nu ch mt cht th bn s thy c Intel t trn cng mt cng c khi nhanh v t nht cng vi mt khi chm (phc tp). Chnh v vy, trong khi khi

phc tp ang bn x l d liu th cc khi khc c th vn nhn cc ch lnh gii m t cng gi i tng ng ca n. Nh chng ti cp trc, tng ny l gi tt c cc khi thc thi lun lm vic. Nh gii thch, sau mi mt ch lnh gii m c thc thi, n li tr v b m Reorder Buffer, y chnh l ni c ca n c thit lp ch thc thi. Sau ti tng cui (Retirement Stage), cc ch lnh gii m c c thc thi ca chng s c xa khi b m Reorder Buffer theo th t ban u ca n (ngha l theo th t m chng c gii m) v sau cc thanh ghi x86 c cp nht (ngc li bc ca tng t li tn ca thanh ghi). C th c n 3 ch lnh gii m c xa b t b m Reorder Buffer trn mi mt chu k clock. Sau , mi ch lnh ny c thc thi hon ton. Cng ngh SpeedStep nng cao Cng ngh SpeedStep c to ra tng thi gian sng ca pin v n c gii thiu u tin trong cc b vi x l ca Pentium III M. Phin bn u tin ca cng ngh ny cho php cc CPU c th chuyn gia hai tn s clock mt cch ng. Ch tn s thp (LFM), ch cho php thi lng sng ca pin ln nht, v ch tn s cao (HFM), ch cho php chy CPU ti tc ln nht. CPU c hai t l nhn clock. T lnh LFM l t lnh factory-lock v bn khng th thay i c t l ny. Pentium M gii thiu cng ngh SpeedStep nng cao (Enhanced SpeedStep Technology), cng ngh ny l cng ngh c mt vi cu hnh clock v in p khc gia LFM (c nh l 600 MHz) v HFM. Mt v d cc bn c th d hiu hn trong trng hp ny, bng cu hnh clock v in p cho 1.6 GHz Pentium M da trn cng ngh 130nm: in p 1.484 V 1.42 V 1.276 V 1.164 V 1.036 V Clock 1.6 GHz 1.4 GHz 1.2 GHz 1 GHz 800 MHz

0.956 V

600 MHz

Mi mt m hnh ca Pentium M li c mt bng in p/clock ca ring n. Bn cn phi ch mt iu rng khi khng cn tn nhiu nng lng i vi laptop th khng nhng ch gim tc clock m cn gim c in p, vic gim in p s gip gim tiu tn rt nhiu pin my. Cng ngh Enhanced SpeedStep lm vic bng cch kim tra cc thanh ghi model c th MSR (Model Specific Registers) ca CPU, thnh phn ny c gi l Performance Counter. Vi thng tin thu nhn t b phn ny, CPU c th gim hoc tng clock/in p ca n ph thuc vo kh nng s dng ca CPU. n gin nu bn tng yu cu s dng CPU th n s tng clock/in p cn nu bn gim hiu sut s dng CPU th n s gim clock/in p. Enhanced SpeedStep ch l mt trong nhng nng cao c thc hin vi kin trc siu nh Pentium M nhm mc ch tng thi lng s dng ca pin. Memory Cache v Khi tm np (Fetch Unit) Nhng chng ti cp t trc, L2 memory cache ca Pentium M c th l 1 MB trn cc m hnh 130 nm (li Banias) hay 2 MB trn cc m hnh 90 nm (li Dothan). Trong khi n c hai memory cache L1, mt ci l 32KB cho ch lnh v ci kia l 32KB cho d liu. Nh gii thch phn trc, khi tm np c chia thnh 3 tng. Trong hnh 2, bn c th xem c cch khi tm np lm vic nh th no.

Hnh 2: Khi tm np Khi tm np np dng th nht (32 bytes = 256 bits) vo b m lung ch lnh ca n (Instruction Streaming Buffer). Sau b gii m chiu di ch lnh s nhn ra cc ranh gii ch lnh bn trong mi 16byte. V ch lnh x86 khng c chiu di c nh nn tng ny s nh du v tr mi ch lnh bt u v kt thc bn trong 128bit c np. Nu c mt ch lnh nhnh no bn trong 128 bit th a ch s c lu vo Branch Target Buffer (BTB), chnh v vy CPU ca bn c th s dng cc thng tin ny sau trn mnh d bo nhnh ca n. BTB c 512 u vo.

Sau khi tng Decoder Alignment Stage nh du khi gii m ch lnh no th mi ch lnh s c gi i. C 3 khi gii m ch lnh (Instruction Decoder) khc nhau c gii thiu phn di y.

Gii m ch lnh v thay i tn cho thanh ghi (Instruction Decoder and Register Renaming) V kin trc P6 s dng cho cc b vi x l Pentium Pro kin trc CISC/RISC lai nn b vi x l phi chp nhn cc ch lnh CISC v cng c bit n vi t cch l cc ch lnh x86, iu ny l do tt c cc phn mm cung cp ngy nay u c vit bng kiu ch lnh ny. CPU ch s dng RISC khng dnh cho h PC, v n s khng chy c phn mm ph bin hin nay nh Windows v Office.

V vy, gii php c s dng bi tt c cc b vi x l hin ang cung cp trn th trng ngy nay t c Intel v AMD l s dng gii m ng thi CISC/RISC. Bn trong, CPU x l cc ch lnh RISC nhng front-end ca n li ch chp nhn cc ch lnh CISC x86.

Cc ch lnh CISC x86 c cp n nh ch lnh thng thng cn cc ch lnh RISC bn trong c cp n nh cc ch lnh c gii m. Mc d vy, cc ch lnh c gii m RISC khng th c truy cp mt cch trc tip, do chng ta khng th to phn mm da trn cc ch lnh ny vng trnh qua b gii m. Cng vy, mi CPU s dng cc ch lnh RISC ca ring n, cc ch lnh ny khng c cng b v khng tng thch vi ch lnh gii m t cc CPU khc. iu c ngha l cc ch lnh gii m ca Pentium M khc hon ton vi ch lnh gii m ca Pentium 4, s khc bit ny chnh l t cc ch lnh gii m Athlon 64. Ph thuc vo phc tp ca ch lnh x86 m n phi c chuyn thnh cc ch lnh gii m RISC. B gii m ch lnh Pentium M lm vic ging nh trn hnh 3. Nh nhng g bn c th quan st thy, c ba b gii m v mt b xp dy ch lnh gii m (MIS). Hai b gii m c ti u ha cho cc ch lnh n gin, trong cc ch lnh n gin l ch lnh thng ch l mt ch lnh gii m. Kiu ch lnh ny c chuyn i nh mt ch lnh gii m. Mt b gii m c ti u ha cho cc ch lnh x86 phc tp, ch lnh ny c th c chuyn i thnh 4 ch lnh gii m. Nu ch lnh x86 qu phc tp, c

ngha l n chuyn i ti hn bn ch lnh gii m th n s c gi n MIS l b nh ROM, gm c mt danh sch cc ch lnh c th c dng thay th cho x86 trn.

Hnh 3: B gii m v i tn thanh ghi

B gii m ch lnh c th chuyn i ln n 3 ch lnh x86 trn mi mt chu k clock, mt b gii m phc tp Decoder 0 v hai b gii m n gin 1 v 2, iu ny lm cho chng ta c cm gic hng i ch lnh c gii m (Decoded Instruction Queue) c th ln n 6 ch lnh gii m trn mi chu k clock, kch bn c th khi Decoder 0 gi 4 ch lnh gii m v hai b gii m kia gi mi b mt ch lnh c gii m hoc khi MIS c s dng. Cc ch lnh x86 phc tp s dng (MIS) Micro Instruction Sequencer c th d chm mt s chu k clock khi gii m, iu ph thuc vo s lng ch lnh c gii m s to ra t s chuyn i. Bn cn nn lu rng Decoded Instruction Queue ch c th gi c n 6 ch lnh gii m, chnh v vy nu c hn 6 ch lnh gii m c sinh ra bi b gii m cng vi MIS th mt chu k khc s c s dng gi cc ch lnh hin hnh trong hng i ti Register Allocation Table (RAT), lm trng hng i v chp nhn cc ch lnh gii m m khng ph hp vi n trc .

Pentium M s dng mt khi nim mi i vi kin trc P6, khi nim ny c gi l hp nht ch lnh gii m. Trn Pentium M, mi mt b gii m ni hai ch lnh gii m thnh mt. Chng s ch c tch ra khi c thc thi, ti tng thc thi.

Trn kin trc P6, mi ch lnh c chiu di 118 bit. Pentium M thay v lm vic vi cc ch lnh 118bit, n lm vic vi cc ch lnh c chiu di 236bit m chnh l kch thc ni ca hai ch lnh 118bit. Bn cn phi lu rng cc ch lnh gii m lin tc c chiu di l 118bit, cn nhng g c thay i l chng c truyn ti thnh mt nhm gm hai ch lnh c bn ny.

tng ng sau phng php ny l tit kim nng lng v tng hiu sut. Vic gi mt ch lnh c kch thc 236bit di s nhanh hn vic gi hai ch lnh 118bit. Thm vo , CPU s tiu tn t ngun in hn v s c t ch lnh gii m lu thng bn trong n.

Cc ch lnh c gn sau s gi n bng Register Allocation Table (RAT). Kin trc CISC x86 ch c 8 thanh ghi 32bit l EAX, EBX, ECX, EDX, EBP, ESI, EDI v ESP. S lng ny l qu thp v cc CPU hin i c th thc thi m out-of-order, v n s ph hng ni dung bn trong thanh ghi c, t gy ra hng cc chng trnh.

Chnh v vy, ti tng ny, b vi x l thay i tn v ni dung ca cc thanh ghi c s dng bi chng trnh thnh mt trong 40 thanh ghi bn trong c (mi mt thanh ghi ny c 80 bit rng, nh vy vic chp nhn c d liu nguyn v d liu thay i), cho php ch lnh c th chy ti cng mt thi im vi ch lnh khc m s dng cng cng mt thanh ghi chun, hoc thm ch out-of-order, c ngha l cho php ch lnh th hai c th chy trc ch lnh th nht d l chng cng chung trn mt thanh ghi.