FPGA Design Flow

Verilog RTL Coding Verilog model Functional/Gate simulation & Verification Verilog Netlist sdc Verilog test bench

Design Stage Tools

Verilog Design Verification Synthesis Text Editor Emacs, Nedit, Vi Modelsim SE Leda Xilinx ISE - XST Synplify Pro Xilinx ISE Xilinx Impact

Logic Synthesis

ucf

ngc

Pyhsical Design & Implementation

Physical Layout

par

Device Configuration

bit

Digital Design Flow

Verilog test bench Verilog Coding Verilog RTL

Design Stage Tools

Verilog Design Text Editor Emacs, Nedit, Vi Mentor - Modelsim SE Synopsys - Leda Synposys - Design Compiler Synopsys - TetraMax Mentor - Fastscan Synopsys - Primetime Cadence - Sensemble/ SOC Encounter Synopsys - Apolllo Cadence - CTgen Synopsys - StarRXT Cadence - Pearl Cadence - Assura, Dracula Mentor Callibre Cadence - Assura, Dracula Mentor Callibre

Functional/Gate Simulation/Verification

Verification Synthesis Test Insertion

Logic Synthesis Verilog Netlist Test-Insertion

scr

test.scr

Static Timing Anal. Place & Route

_pre.sdf

Static Timing Analysis Floorplanning/ Place & Route Clock Tree Insertion Final Layout
techfile.lef techfile.gcf *.lef *.tlf *.def

Clock Tree Insertion Timing Extraction DRC/ANT Checking LVS

ctgen.con

_post.sdf

Timing Extraction

Final Design Check DRC/LVS

gds2

Analogue Design Flow

Schematic Entry

Design Stage
Schematic Entry

Tools
Composer Spectre Virtuosso Assura Calibre Spectre

Simulation

Simulation Layout
techfile.lef techfile.gcf *.lef *.tlf *.def

Layout

Pyhsical Verification/ Extraction Post-Layout Simulation

Physical Verification / Extraction

Post-Layout Simulation

gds2

Mixed Signal Design Flow

Digital Flow
Cadence - SpectreVerilog Cadence -UltraSim Co-simulation Environement

Analog Flow

Verilog test bench

Verilog Coding

Verilog RTL

Schematic Entry

Behavioural Modelling

Functional/Gate Simulation/Verification Simulation

Logic Synthesis Verilog Netlist Test-Insertion _pre.sdf Static Timing Analysis Floorplanning/ Place & Route ctgen.con _pst.sdf Clock Tree Insertion Final Layout Timing Extraction Final Design Check DRC/LVS

scr test.scr

Layout

techfile.lef techfile.gcf *.lef *.tlf *.def

techfile.lef techfile.gcf *.lef *.tlf *.def

Physical Verification / Extraction

Post-Layout Simulation gds2

gds2