http://www.electronics-tutorials.ws/diode/diode_6.html http://www.scribd.com/doc/80680684/Full-Wave-Bridge-Rectifier#outer_page_18 http://www.bristolwatch.com/ele/basic_ac_rectification.htm http://dei.vlab.co.in/?

sub=22&brch=60&sim=1113&cnt=2150 19931103

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity project is port ( A0: in std_logic_vector(7 downto 0) := "00110011"; A1: in std_logic_vector(7 downto 0) := "00111100"; A2: in std_logic_vector(7 downto 0) := "11000011"; A3: in std_logic_vector(7 downto 0) := "00111011"; B0: in std_logic_vector(7 downto 0) := "10111011"; B1: in std_logic_vector(7 downto 0) := "01110011"; B2: in std_logic_vector(7 downto 0) := "01111111"; B3: in std_logic_vector(7 downto 0):="01011001"; clk: in std_logic; en: in std_logic; F: out std_logic_vector(7 downto 0) ); end entity; architecture project_a of project is signal T: std_logic_vector(3 downto 0); signal S: std_logic_vector(3 downto 0); signal M: std_logic_vector(1 downto 0); signal controller: std_logic_vector(5 downto 0); signal X,y: std_logic_vector(7 downto 0); signal counter: std_logic_vector(1 downto 0):="00"; signal en_counter:std_logic_vector(2 downto 0); begin process (clk, en, counter, T, A0,A1,A2,A3,B0,B1,B2,B3,S,M,X,y,en_counter,control ler) --codes for the counter ,decorder and controller -- modify the process terms** begin if (clk = '1') then counter <= counter+1; else counter <= counter; end if; en_counter <= en&counter; -- where to put???** if en_counter= "100" then T<="1000"; elsif en_counter= "101" then T<="0100"; elsif en_counter= "110" then T<="0010"; elsif en_counter= "111" then T<="0001"; else T<="0000"; end if;

if T = "0001" then controller<= "000000"; --controller output elsif T = "0010" then controller <= "101010"; elsif T = "0100" then controller <= "010101"; elsif T = "1000" then controller <= "111111"; end if; if controller(3 downto 2) = "00" then X <= A0; -- we have to fix the input elsif controller(3 downto 2) = "01" then X <= A1; -- controller for s0 and s1 elsif controller(3 downto 2) = "10" then X <= A2; elsif controller(3 downto 2) = "11" then X <= A3; end if; if controller(5 downto 4) = "00" then X <= B0; -- we have to fix the input elsif controller(5 downto 4) = "01" then X <= B1; -- controller for s2 and 23 elsif controller(5 downto 4) = "10" then X <= B2; elsif controller(5 downto 4) = "11" then X <= B3; end if; if controller(1 downto 0) elsif controller(1 downto 1 elsif controller(1 downto elsif controller(1 downto end if; -- show outp** end process; end architecture; = "00" then F <= A0 + B0; -- we have to fix the input 0) = "01" then F <= A1- B1; -- controller for m0 and m 0) = "10" then F<= A2 AND B2; 0) = "11" then F <= A3 OR B3;