Efficient HVDC Converter Model for Real Time Transients Simulation

S. Acevedo, Member, IEEE

University of British Columbia Vancouver, BC, V6T 1Z4 Canada

L. R. Linares
University of British Columbia Vancouver, BC, V6T 1Z4 Canada

J. R. Mart, Member, IEEE

University of British Columbia Vancouver, BC, V6T 1Z4 Canada

Y Fujimoto
Mitsubishi Electric Corporation Amagasaki, Hyogo 661 Japan
smoothing reactor DC system

Abstract: An efficient model has been developed to simulate High Voltage Direct Current (HVDC) Converters in real-time transient simulators. Real time performance of 45 s per solution step has been achieved for a 12-pulse monopolar converter and 81 s for the bipolar converter using a single processor Pentium Pro 200 MHz desktop computer. The HVDC converter model is solved simultaneously with the power network. Simultaneous solution makes the model capable of sustained long-time simulation for real time testing of system performance and control functions. Keywords: Real-time power system simulators, HVDC converters, high-voltage, direct current, EMTP solution techniques, power electronics device modelling.

AC system

Y-Y transformer SVC AC filters

6-valve bridge

DC filters

Y- transformer

6-valve bridge

Fig. 1. HVDC Converter Substation.

I. INTRODUCTION The power systems research group at the University of British Columbia (UBC), MicroTran Power system Analysis Corporation, and Mitsubishi Electric Corporation have been actively involved in the development of fast and accurate algorithmic solutions for real-time transients simulation [1][5]. This paper describes cooperative work in developing a high-performance model for 12- and 24-valve HVDC converters suitable for real-time power system simulators. The test model presented here includes a simplified AC source network representation, converter transformers, converter bridges, and smoothing reactors. Fig. 1 shows a typical converter substation. The task of developing an efficient 12-pulse converter substation model that can perform under the constraints of real time (e.g., around 50 s per solution step) and that can be solved simultaneously with the power network is a particularly challenging one. Traditional EMTP modelling techniques are not sufficient in this case. The EMTP models diode-type elements, such as, diodes, thyristors, GTOs, etc. as switches that ideally conduct or block depending on the polarization signals. This approach ignores the internal details at the device level, but it is widely accepted as sufficient for power electronic devices at the circuit level [6].

The traditional EMTP technique of collapsing or creating nodes as the device conducts or blocks involves retriangularizing the systems [G] matrix whenever there is a change in the conducting state of one of the valves [7]. In a 12- or 24- valve converter, however, this process is simply too slow for real time performance. Another major difficulty in modelling diode-type devices in transient simulations is the numerical oscillations of the trapezoidal rule of integration whenever current is interrupted in an inductive circuit. The use of the Critical Damping Adjustment (CDA) technique solves this problem [8]. The HVDC converter model developed in this project overcomes the above-mentioned problems in traditional EMTP solutions and provides fast and accurate solutions suitable for real time simulation. The algorithm is written in portable C++ code using object-oriented programming techniques. On a first stage, the model has been tested using a desktop Pentium Pro 200 MHz computer. The objectoriented structure of the code, however, permits its easy porting to parallel-computer architectures. Work is currently in progress to implement the algorithm in high-performance parallel-processing machines. The approach developed uses the principle of subdividing an electrical circuit containing a 6n-valve converter into at least n subsystems. For each 6-valve subsystem, the matrices corresponding to all possible 64 combinations of valve on or off states are precalculated and prestored in computer memory. With this subdivision approach, the number of precalculated combinations for a 24-valve HVDC substation is reduced from more than 16 million to only 256.

II. HVDC OBJECT MODEL The first step in developing the proposed general-purpose converter model is to define a subcircuit with elements that are common to typical HVDC substations. This subcircuit is named the HVDC Object. Different Object definitions are feasible and the one presented here is only one particular case. Consider an HVDC Object containing the elements indicated in Fig. 2. The Objects core is the 6-pulse bridge; the converter transformer can be connected in Y-Y or Y-, and the smoothing reactor is optional. The discrete-time equivalent for the HVDC Object has a conductance matrix (with 64 possibilities) and a history source vector. Associated with the HVDC Object there are 64 states resulting from all possible valve combinations. At each time-step, the state of the HVDC Object is determined from the systems terminal voltages. This Object is then combined with the external network for the simultaneous solution of system and object at the subsequent time step of the simulation. A more efficient algorithmic coding and solution speed can be achieved if the dimension of the system matrices is maintained constant. To avoid nodes collapsing when the valves conduct (as in the EMTP), the thyristors are modeled as varying resistors. A very low resistance is used for the conducting state and a very high resistance for the blocking state. The thyristors holding current Ih and minimum turn on voltage Von are user defined. An important feature of the model is its ability to simulate internal converter faults, such as commutation failures. A thyristor requires a period of time tq to recombine the internal charges before operating in the blocking state. If the device voltage becomes positive before the internal charges have recombined totally, the thyristor will conduct again with or without the presence of a firing signal. This event, which may lead to undesired reclosure of a thyristor, is known as commutation failure. The transformer model consists of three single-phase units, each one modeled as an ideal transformer in series with its short circuit impedance [7]. In the discrete time domain it is possible to write the transformer admittance matrix directly from the nominal data. The three-phase bank is formed combining three units and specifying the transformer connection (e.g., Y-Y or Y-).

The smoothing reactor commonly used in HVDC systems to filter the harmonic content in the dc line current is modeled as an inductor and its equivalent circuit is added to the converter substation matrix together with the corresponding valve and transformer conductances. Harmonic filters can be easily added externally using simplified discrete-time equivalents. III. SOLUTION ALGORITHM Experience in developing UBCs real-time simulator [1] suggested that precalculation and prestorage of the inverse -1 conductance matrix [G] for all possible conducting states of the switches can result in very efficient execution speeds. In the present problem, however, for 24 valves there are 224 = 16,772,216 possible conductance matrices. Considering both rectifier and inverter, the number of pre-stored matrices would be in the order of 33 million. This number was considered excessive for a general converter model solution. To overcome the problem of modelling all valves as a single matrix, with the excessive number of possible combinations indicated above, it was decided to follow an object-oriented approach and reduce the problem to more manageable units. Philosophically, this approach is consistent with the general power system real-time simulator project presented in [4]. In the object oriented approach, all possible states of the HVDC Object are precalculated. Although the actual number of physically possible states of a 6-pulse bridge is 49, it is algorithmically simpler and faster to precalculate all 64 combinations without a dramatic increase in the required storage requirements. This gives a total of 256 possible states for the 4 bridges of a 12-pulse bipolar converter. This small number is in strong contrast with the 16.8 million combinations required for a precalculation of all four groups together. As indicated, at each time step of the transient solution, and based on the results of the previous solution step and the firing signals, the matrix for the correct converter status is picked-up for each HVDC Object (see Fig. 3). All the Objects are then combined with the external power network for a simultaneous solution of the complete system using the algorithm shown in Fig. 4.

1 2 3

a b c Y Y or Y

6-valve bridge

4
smmothing reactor (optional)

Fig. 2. The HVDC Object.

For each HVDC Object, precalculate and prestore its 2x matrices (where x represents the number of valves). Assume an initial state for each Object

Build the system's conductance matrix G-system with all the elements in the system except for the HVDC Objects

Start transient analysis t=0

Update the system's matrix G-system by including the active G-matrix of each HVDC Object

during current interruptions. These oscillations occur regardless of whether interruption takes place at an exact zero crossing of the current (thyristors) or during current chopping (GTOs). The numerical oscillations problems can be totally eliminated using the Critical Damping Adjustment (CDA) technique of [8], implemented in the MicroTran and DCG/EPRI versions of the EMTP. Other numerical issues in power electronics modelling that were not considered here include the calculation of the exact instant at which a valve is closed or opened and the ability to model forced commutated converters. These topics are currently under investigation. Object-Oriented Program Design Considerations For the test results shown in the next section, the new HVDC model was driven by a subset of OVNI, the RealTime Power System Simulator Program currently under development at UBC [4]. The driver subset of OVNI considers the HVDC model as an object representation of a finite state machine (FSM). That is, the model can only be in one of a finite number of states and its trajectory to that particular state depends on the previous state history of the model. Encapsulation allows the HVDC model-object to shield its state, and to communicate to the driver only those pieces of information needed to determine the Objects change of state. OVNI, as well as its predecessor, RTNS [1], uses topological segmentation (Fig. 5) to take advantage of the network's matrix sparcity, and to allow for a convenient and efficient implementation of coarse grain parallelization. The HVDC Object model is incorporated into one of the topological blocks of Fig. 5 (as explained in Fig. 3). This scheme reduces the computational impact of state transitions of the model on the solution process for the rest of the network.

Using nodal analysis, solve the network at time t

For each HVDC Object, determine the valves' positions and the new HVDC Object status (use the known voltages, obtain currents and check controller firing signals)

Evaluate histories for all the elements in the system

Increment time-step

No

end of simulation time?

Yes

end

Fig. 4. Generalized algorithm to solve a network containing n HVDC Objects.

The simultaneous solution of the full system (including the HVDC converter) prevents the accumulated phase-shift errors that occur in real-time simulator solutions that use a t time delay to connect the separate solutions of the power network and the converter. This t delay technique, which is also often used to interface controllers (e.g., TACS in the EMTP) and synchronous machines to the network, can lead to instability and run-off of the solution for long-term simulations. Another critical issue in the modelling of power electronic devices is the idealization of the current interruption process. As indicated, the converter valves are modeled as ideal conduct/block devices, which creates sustained numerical oscillations of the trapezoidal rule of integration

G64

[Ga]
Gi G3 G2 G1

SYSTEM G-matrix

[ [Gb]

HVDC Object at corresponding nodes

G-matrix for active status

HVDC OBJECT MATRICES G1: matrix for status 1 G2: matrix for status 2 G3: matrix for status 3 : G63: matrix for status 63 G64: matrix for status 64

[G] matrices corresponding to three different topological blocks in the network

[Gc]

Fig. 5. Conductance [G] matrix for a network with topological segmentation. Fig. 3. One of the 64 Object matrices inserted into the network matrix.

IV. SIMULATION RESULTS

6 2
Y-D

The HVDC model performance is presented in this section. The ability to simulate the behaviour of the converter valves in detail is demonstrated by staging ac and dc faults. The real time capability of the proposed algorithm is then illustrated. The simulation results were obtained using a singleprocessor 200 MHz Pentium Pro desktop computer. The test program is object-oriented and was coded with the C++ programming language using the public domain gcc compiler of the Free Software Foundation. A. 12-PULSE TEST SYSTEM. The 12-pulse system of Fig. 6 was simulated to verify the response of the HVDC converter and its controller to different fault conditions and to show the capability of the proposed model to simulate the behaviour of the converter valves during abnormalities. The controller is a proportional integral controller with an equidistant pulse control scheme. Switches S1 and S2 were closed to simulate dc and ac faults, respectively. The dc source connected in series with the load resistance was set to zero for rectifier operation and to a negative value for inverter operation. Two simulated cases are presented next. Case 1. DC fault. The HVDC converter was operated as a rectifier in current control mode. A dc fault was then introduced from t=0.2 to t=0.3 seconds. The rectified current, firing angle, and rectified voltage are shown in Fig. 7.
current (A)
10000 5000 0 0 0.1 0.2 0.3

7 8

3 4 5
Y-Y

S1

dc fault

S2

ac line-to-ground fault

Idc CONTROL

Fig. 6. A 12-pulse test system.

Case 2. AC fault - commutation failure. An AC fault was applied to phase a during inverter operation. This resulted in the reduction of the available extinction angle until a commutation failure occured in valve 1, as illustrated in Fig. 8. B. SIMULATION TIMES. To verify the speed performance of the proposed algorithm, the C++ code was interfaced with a subset of to the OVNI simulator [4]. The following results correspond to the OVNI driver using the backward Euler integration rule. The results of these simulations illustrate the real-time performance of OVNI when simulating circuits containing HVDC converters.

DC

0.4

0.5

0.6

time (s) angle () firing

100 0

0.1

0.2

0.3

0.4

0.5

0.6

voltage (kV)

time (s)
500 0 -500 0 0.1 0.2 0.3 0.4 0.5 0.6

DC

time (s)

Fig. 7. DC fault.

current (A)

DC

5000

0.05

0.1

0.15

0.2

0.25

0.3

time (s) angle () firing

150

100

0.05

0.1

0.15

0.2

0.25

0.3

voltage (kV)

time (s)
500 0 -500 0 0.05 0.1 0.15 0.2 0.25 0.3

DC

time (s)

voltage (kV)

500

Valve 1

-500

1
0.22 0.24

2<1

2
0.26 0.28 0.3

time (s) currents (A)

4000 3000 2000 1000 0 0.22 0.24 0.26 0.28 0.3

Valve

ivalve1

ivalve3

time (s)

commutation failure
Fig. 8. AC fault.

Table I. Simulation times in microseconds per time step on a Pentium Pro 200 MHz workstation.

CPU time per time step (microseconds)

Real time performance is restricted by the solution time required by the time step that takes the longest. These longest solution times for a 6-valve, a 12-valve, and a 24valve HVDC converter are presented in Table I and Fig. 9. These timings were obtained on a Pentium Pro 200 MHz workstation.

HVDC Object in OVNI

MicroTran (v2.06) 3120

983 459 26 6-valve 45 12-valve 81 24-valve

MicroTran (v2.06) HVDC Object in OVNI Ratio:

6-valve 459 26 17.7

12-valve 983 45 21.8

24-valve 3120 81 38.5

number of valves in converter

Fig. 9. Simulation times on a Pentium Pro 200 MHz workstation.

Even though not yet tested, the timings in Table I and Fig. 9 will probably fall to about 2/3 of the shown values with the new Pentium II-300 MHz machines. This should bring the timings for the 24-valve case down to the 50 s real-time performance benchmark. V. CONCLUSIONS This paper has presented results of a common effort involving The University of British Columbia, MicroTran Power System Analysis Corporation, and Mitsubishi Electric Corporation to develop an efficient and accurate algorithm to represent HVDC converter stations in real-time transient simulators. The developed algorithm has minimum prestorage requirements: only 256 matrices are needed for a 24valve station, and yet, it is capable of achieving real time performance: 81 s/step for a bipolar 12-pulse converter (24 valves), and 45 s/step for a monopolar 12-pulse converter (12 valves) on an off-the-shelf Pentium Pro 200 MHz desktop computer. The developed real time algorithm gives numerically clean and absolutely stable results. Numerical oscillations at current interruptions are suppressed using the CDA (critical damping adjustment) concept of MicroTran and DCG/EPRIs EMTP. In the developed solution, the converter station model is solved simultaneously with the power system network, thus avoiding long-term instability due to growing phase error in t-delayed solution schemes. The absolute numerical stability of the algorithm makes it suitable for continuousduty (always on) general-purpose power system simulators. The algorithm is written in portable C++ code using object-oriented program design techniques. The algorithm makes maximum use of object decoupling techniques developed in connection with the RTNS and OVNI real-time simulators which account for its storage efficiency and high execution performance. This approach also allows for the easy porting of the model to higher-performance parallel processing machines. Testing of the algorithm in highperformance parallel-processing machines is currently in progress. It is expected that the timings reported in this paper will be improved by a factor of three or more in these machines. VI. REFERENCES [1] J. R. Mart and L. R. Linares, Real-time EMTP-Based Transients Simulation, IEEE Transactions on Power Systems, vol. 9, vo. 3, August 1994, pp. 1304-1317. [2] L. R. Linares and J. R. Mart, Sub-area latency in a real-time power network simulator, Proceeding IPST95, International Conference on Power System Transients, Lisboa, September 1995, pp. 541-545.

[3] J. R. Mart, S. Acevedo, L. R. Linares, H. W. Dommel, and Y. Fujimoto, Accurate Solution of HVDC Converters in Real Time Transients Simulation, Proceedings of the 1997 International Conference on Power System Transients IPST97, pp. 455-459. [4] J. R. Mart, L. R. Linares, R. Rosales, and H. W. Dommel, OVNI: A Full-Size Real-Time Power System Simulator. Transactions of the Second International Conference on Digital Power System Simulators, ICDS'97, May 1997, pp. 37-42.. [5] Y. Kowada, I. Iyoda, N. Sato, and A. Yamazaki, A study on parallel processing of electromagnetic transient simulation, IEEE Transactions on Power Systems, vol. 10, no. 3, August 1995. [6] S. Sudha, A. Chandrasekaran, and V. Rajagopalan, New approach to switch modelling in the analysis of power electronic systems, IEE Proceedings-B, vol. 140, no. 2, March 1993, pp. 115-123. [7] H. W. Dommel, EMTP Theory Book, Second Edition, Microtran Power System Analysis Corporation, Vancouver, BC, Canada, 1992. [8] J. R. Mart, and J. Lin, Suppression of numerical oscillation in the EMTP, IEEE Transactions on Power Systems, vol. 4, no. 2, May 1989, pp. 739-747.

VII. BIOGRAPHIES
Salvador Acevedo (M93) was born in Oaxaca, Mxico, in 1962. He obtained the degrees of Electrical Engineer (1985), M. Eng. (1987), and M. A. Sc (1993) from Instituto Tecnolgico y de Estudios Superiores de Monterrey (ITESM) in Monterrey, Mxico. Since 1987, he has worked for ITESM as an instructor and as Head of the Electrical Eng. Department. Currently, on a leave of absence he is finishing a Ph. D. at the University of British Columbia. Luis R. Linares was born in Valera, Venezuela in 1951. He graduated from Central University of Venezuela as an Electrical Engineer in 1981. He worked on software design and consulting and as an instructor for Central University of Venezuela. He obtained a M. A. Sc. degree from the University of British Columbia in Vancouver, Canada, in 1992, and is currently working towards a Ph. D. degree in the same University. Jos R. Mart (M71) was born in Lrida, Spain in 1948. He received the degree of Electrical Engineering from Central University of Venezuela in 1971, the degreee of M. E. E. P. E. from Rensselear Polytechnic Institute in 1974 and the Ph. D. degree from the University of British Columbia in 1981. He was with Central University of Venezuela in 1974-77 and 1981-84. Since 1988 he has been with the University of British Columbia in Vancouver, Canada. Yasushi Fujimoto was born in Wakayama, Japan in 1968. He graduated from Electrical Engineering of Kyoto University in 1992. Since 1992, he is working for Mitsubishi Electric Corporation in Amagasaki, Japan. He was working as a visiting scalar at the University of British Columbia in Vancouver, Canada from December, 1995 to July, 1996.