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RF Technology rfinfo@rftechnology.com.au August, 2003 Revision 2

T50 Tr ansmitter
Operation and Maintenance Manual

This manual is produced by RF Technology Pty Ltd 10/8 Leighton Place, Hornsby NSW 2077 Australia Copyright 2001 RF Technology 1

Contents
1 Operating Instructions 1.1 Front Panel Controls and Indicators 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.11 2.9 3 3.1 3.2 4 5 PTT Line POWER LED TX LED ALARM LED 5 5 5 5 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 8 8 8 8 9 9 10 10 10 13 14 15 16 18 20 20 21 21 21 22 22 24 25 25 26 28 2

Transmitter Internal J umper Options Serial I/O Parameters Line Terminations Exciter Low Battery Level External PA Parameters Generate Loop External Tone Input External Tone, High Pass Filter Bypass Transmit Time Channel Select Override CWID Start Delay CWID Period CWID Message Channel Selectable Parameters 25 Pin Connector 9 Pin Front Panel Connector

Transmitter I/O Connections

Channel and Tone Frequency Programming Circuit Description 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 T50 Master Schematic (Sheet 1) Microprocessor (Sheet 2) Audio Processing Section (Sheet 3) Line Input Processing Section (Sheet 4) Tone Generation Section (Sheet 5) Frequency Synthesiser (Sheet 6) Voltage Controlled Oscillators (Sheet 7) 1W Broadband HF Power Amplifier (Sheet 8) Power Generation Section (Sheet 9) Standard Test Equipment Invoking the Calibration Procedure Manually 6.2.1 The Miscellaneous Calibration Procedure 6.2.2 The Reference Calibration Procedure 6.2.3 The Deviation Calibration Procedure 6.2.4 The Tone Deviation Calibration Procedure 6.2.5 The Line Calibration Procedure 6.2.6 The Power Calibration Procedure

Field Alignment Procedure 6.1 6.2

Specifications

7.1

Overall Descr iption 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 Channel Capacity CTCSS Channel Programming Channel Selection Microprocessor

28 28 28 28 29 29 29 29 29 29 29 29 29 29 30 30 30 30 30 30 30 30 30 30 30 30 30 31 31 31 31 31 31 32 32 32 32 32 32 32 33 33 33 33 34 46 48 3

7.2 7.3

Physical Configuration Front Panel Controls, Indicators and Test Points 7.3.1 7.3.2 7.3.3 Controls Indicators Test Points Power Requirements Frequency Range and Channel Spacing Frequency Synthesizer Step Size Frequency Stability Number of Channels Output Power Transmit Duty Cycle Spurious and Harmonics Carrier and Modulation Attack Time Modulation Distortion Residual Modulation and Noise 600 Line Input Sensitivity Test Microphone Input External Tone Input T/R Relay Driver Channel Select Input / Output DC Remote Keying PTT in Programmable No-Tone Period Firmware Timers CTCSS DCS Codes CWID RF Output Connector Power and I/O Connector External Reference Connector (optional)

7.4

Electrical Specifications 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 7.4.12 7.4.13 7.4.14 7.4.15 7.4.16 7.4.17 7.4.18 7.4.19 7.4.20 7.4.21 7.4.22 7.4.23 7.4.24

7.5

Connectors 7.5.1 7.5.2 7.5.3

A A.1 A.2 A.3 B C D

Engineering Diagrams Block Diagram Circuit Diagrams Component Overlay Diagrams

T50 Parts List (Rev. 4) T50 Parts List (Rev. 3) EIA CTCSS Tones

WARNING
Changes or modifications not expressly approved by RF Technology could void your authority to operate this equipment. Specifications may vary from those given in this document in accordance with requirements of local authorities. RF Technology equipment is subject to continual improvement and RF Technology reserves the right to change performance and specification without further notice.

1 Oper ating Instr uctions

1.1 Fr ont Panel Contr ols and Indicator s
1.1.1 PTT
A front-panel push-to-talk (PTT) button is provided to facilitate bench and field tests and adjustments. The button is a momentary action type. When keyed, audio from the line input is disabled so that a carrier with subtone is transmitted. The front-panel microphone input is not enabled in this mode, but it is enabled when the PTT line on that socket is pulled to ground. The PTT button has another function when transmission is keyed up, and the TX LED light is showing. If there is a forward power low alarm (the ALARM LED flashes three times, then pauses), pressing this will cause the ALARM LED to flash 6, 7, 8, or 9 times before the pause (see Table 2). This will indicate what has caused the low power alarm.

1.1.2

Line

The LINE trimpot is accessible by means of a small screwdriver from the front panel of the module. It is used to set the correct sensitivity of either line input or the direct audio input. It is factory preset to give 60% of rated deviation with an input of 0dBm (1mW on 600, equivalent to 775mV RMS or about 2.2V peak-to-peak) at 1kHz. By this means an input sensitivity from approximately -12dBm to +12dBm may be established. An internal, software selectable, option, provides an extra gain step of 20dB. This, effectively changes the input sensitivity to 32 to 8dBm. LED Flash Cadence 9 flashes, pause 8 flashes, pause 7 flashes, pause 6 flashes, pause 5 flashes, pause Fault Condition External PA failure reason unknown Low dc supply on External PA External PA Over Current Condition External PA Over Temperature One or both synthesizers could not lock. 4

4 flashes, pause 3 flashes, pause 2 flashes, pause 1 flash, pause LED ON continuously LED Flash Cadence 9 flashes, pause 8 flashes, pause 7 flashes, pause 6 flashes, pause 3 flashes, pause 2 flashes, pause 1 flash, pause LED ON continuously

Either PLL is near its operational limit Unable to communicate with the External PA. The current channel is not programmed or the channel frequency is out of range. Low dc supply voltage Transmitter timed out Fault Condition External PA failure (if PTT is pressed) Low dc supply on External PA (if PTT is pressed) External PA Over Current Condition(if PTT is pressed) External PA Over Temperature(if PTT is pressed) Forward Power Out of Range(if PTT is not pressed) Reverse Power ratio exceeded. Low dc supply voltage Transmitter timed out

Table 1: Interpretations of LED flash cadence (TX LED Off)

Table 2: Interpretations of LED flash cadence (TX LED On)

1.1.3

POWER LED

The PWR LED shows that the dc supply is connected to the receiver and that the microprocessor is not being held in a RESET state.

1.1.4

TX LED

The TX LED illuminates when the transmitter is keyed. It will not illuminate (and an ALARM cadence will be shown) if the synthesizer becomes unlocked, or the output amplifier supply is interrupted by the microprocessor.

1.1.5

ALARM LED

The Alarm LED can indicate several fault conditions if they are detected by the self test program. The alarm indicator shows the highest priority fault present. See Tables 1 and 2.

2 Tr ansmitter Options
There are NO internal jumpers in the T50. There are many software selectable options. Some options are selected on a per channel basis, and some are defined globally (i.e. the parameter is fixed irrespective of which channel is selected). Below is a description of these global parameters

2.1 Ser ial I/O Par ameter s

There are two serial ports. There is the main serial port which is brought out to the front panel connector. This is referred to as PORT0. There is another serial port which is for factory use only. It is referred to as PORT1. The baud rate, can be defined for PORT0. PORT0 is set by default to 57.6Kbps, with No parity. 5

2.2 LINE Ter minations

There are two main audio inputs, plus a direct audio (TONE) input. The direct audio input is a High Impedance Balanced DC input, but the two audio inputs are AC coupled (> 10Hz) inputs which can be High Impedance(HiZ), or 600 ohm inputs. Each input can be software selected to be HiZ, or 600 ohms.

2.3 Exciter Low Batter y Level

This is factory set to 24.0V, and defines the level of the DC supply that will cause an Exciter dc supply low alarm.

2.4 Exter nal PA Par ameter s

There are several user definable parameters associated with the external PA provided with each exciter. These are the PA low battery alarm level (default is 26V), the PA Set Forward Power Level (defaults to 100W), the Forward Power Low Alarm Level (defaults to 90%), and the Reverse Power Alarm Level (defaults to 25% - corresponding to a VSWR of 3:1).

2.5 Gener ate LOOP

Normally the transmitter will key up if dc current is sensed flowing in either direction between Line1+ and Line1- (>=1mA). If the LOOP_VOLTS option is set to its nondefault setting, then a 12Vdc supply is applied to the pair through 660 ohms of source impedance. (It would be expected, normally, that if this option is selected, then the option to remove the 600 terminator from Line1, would also be selected). If dc current flows from having applied this potential, then the transmitter will key up.

2.6 Exter nal TONE Input

Normally any signal applied to the TONE+/TONE- pair is ignored. If this option is selected, then a Direct Audio input will be mixed with any audio received on either of the other two lines, and with any CTCSS tones, or DCS codes being generated.

2.7 Exter nal Tone High Pass Filter Bypass

Normally the Direct Audio, and the CTCSS/DCS outputs are passed through a 250Hz, low pass filter. This filter can be bypassed by selecting this option.

2.8 Tr ansmit Time

This parameter defines a maximum time limit for continuous transmission. It is expressed in seconds and can be arbitrarily large (months in fact). If it is set to zero seconds, then the transmitter can stay keyed up permanently.

2.9 Channel Select Over r ide

This parameter allows the user to override the channel number that is read in via connector P3. Normally it is InActive, but if it is set to a value from 0 to 255, then the exciter will behave as though that channel was hard-wired at the rear.

2.10 CWID Star t Delay

If CWID (Continuous Wave Identification) is enabled, then this value indicates the time in tenths of a second, from keying up an exciter to when the first station identication 6

message is sent. If this timer value is negative, then CWID transmission is disabled. This feature is only available on models from Rev. 4.

2.11 CWID Per iod

If CWID (Continuous Wave Identification) is enabled, then this value indicates the time in tenths of a second from one transmission to the next. If the value is zero, then the CWID message is transmitted only once. This feature is only available on models from Rev. 4.

2.12 CWID Message

This parameter allows the user to specify the message string to be transmitted as the station ID. This feature is only available on models from Rev. 4.

2.13 Channel Selectable Par ameter s

Each channel defines two complete set of parameters. One set of parameters is used when a transmitter keys up from the PTT-in input, and the other set is used when the transmitter keys up from the LOOP-in, the PTT switch, or the microphone PTT input. Each set defines what frequency to use, what CTCSS sub-tone (if any) to use, what maximum line deviation to use, what tone deviation to use, what transmit delay (a delay applied from PTT-in or LOOP-in to transmission), what transmit tail (delay from PTTin, or LOOP-in, to transmission being stopped, and No-TONE period (a period of extra transmission in which No Tone is applied after PTT-in or LOOP-in has been released. As well as these parameters, which Line (or Lines) can be selected, and whether the lines should have flat frequency response or have pre-emphasis applied. Also, it can enable or disable, the extra 20dB gain pad. Note that both Line1 and Line 2 can be selected (each with or without pre-emphasis), and if so, then the two signals will be mixed, and the Line potentiometer will adjust the level of them both.

3 Tr ansmitter I/O Connections

3.1 25 Pin Connector
The female D-shell, 25 pin, connector is the main interface to the transmitter. The pin connections are described in table 3. Function dc power Signal +28Vdc(in) 0 Vdc +5Vdc(out) +12Vdc(out) Vref Serial Communications SCLK MOSI CH_EN PA_CS Pins 13, 25 1, 14 17 15 4 12 6 18 24 7 Specification +24 to 32 Vdc Common Voltage Output for external Logic(100mA) Output for an external relay(120mA) Reference voltage for Tests Serial Clock Bi-directional Data Pin Enables Channel Select Shift Register Enables PA A/D chip

SPARE_SEL 5 600/HiZ Line 600/HiZ Line Direct PTT input T/R Relay output driver Tone+ ToneLine1+ Line1Line2+ Line28 19 10 22 11 23 9 21

Spare Select (for future use) Transformer Isolated Balanced 0dBm Input Transformer Isolated Balanced 0dBm Input Ground to key PTT Open collector, 250mA /12V >10k, dc coupled

Sub-Audible Tone Input

Table 3: Pin connections and explanations for the main 25-pin, D connector.

3.2 9 Pin Fr ont Panel Connector

The female D-shell, 9 pin, front panel connector is an RS232 interface for serial communications to a terminal, a terminal emulator, or to a computer. The pin connections are described in table 4. Function TXD RXD RTS CTS DTR DSR GND Pins 2 3 8 7 6 1 5 Specification Transmit Data (Output) Receive Data (Input) Request To Send (Output) Clear To Send (Input) Data Terminal Ready(Output) Data Set Ready (Input) GND Pin name on IBM PC RxD TxD CTS RTS DSR DCD GND

Table 4: Pin connections for the front panel 9 pin D connector. The pinout for the connector has been chosen so that a straight-through BD9 male to DB9 female cable can connect the transmitter to any male DB9 serial port on an IBM PC compatible computer. Note that for connection to a modem, a cross-over cable will be required.

4 Channel Pr ogr amming and Option Selection

Channel and tone frequency programming is most easily accomplished with RF Technology WinTekHelp software. This software can be run on an IBM compatible PC and can be used to calibrate a T50, R50, and PA50 as well as program channel information. See the WinTekHelp manual for further information.

5 Cir cuit Descr iption

The following descriptions should be read as an aid to understanding the block and schematic diagrams given in the appendix of this manual. There are 9 sheets in the schematic in all.

5.1 T50 Master Schematic (Sheet 1)

Sheet 1, referred to as the T50 Master Schematic, is a top level sheet, showing five circuit blocks, and their interconnection with each other, as well as the interconnection with all connectors and external switches. JP12 is the connector, on the printed circuit board, for the microphone input. P3 represents the rear female DB25 connector. J1 is the nominal 1W RF output (BNC) connector, which is used to connect to the External Power Amplifier. J4 is an optional BNC connector for an external reference clock. If an external reference clock, with power level from +5 to +26dBm is attached here, the firmware will automatically track the channel VCO to the reference. Note that the external reference frequency is limited to: 500kHz, or any multiple any multiple of 128KHz greater than or equal to 512kHz any multiple of 160KHz greater than or equal to 480kHz and cannot be greater than 10MHz in Rev 4 or older versions. In Rev 5, the external frequency can be as high as 20MHz. P1 is the front panel DB9 RS-232 connector for attachment to a terminal, a terminal emulator, or to an IBM PC running the WinTekHelp software. JP2 is for the attachment of an LCD display module. This has been included for later development. This connector, is not normally fitted JP3, and JP4 are specialised connectors for test and factory configuration use only. RV100 represents the front panel LINE potentiometer. SW1 represents the PTT test pin. D102, D103, and D104 represent the three front panel LEDs.

5.2 Micr opr ocessor (Sheet 2)

Sheet 2 describes the basic microprocessor circuitry. The core CPU is the Motorola XC68HC12A0. It is configured in 8 bit data width mode. The CPU is clocked by a 14.7456MHz crystal oscillator circuit (top left) comprising the JFET Q202, and two switching transistors Q203 and Q204. The CPU contains an 8 channel A/D converter whose inputs are identified as AN0, AN1, , AN7. AN7 and AN6 are used as LOCK detect inputs from the two Phase Locked Loop (PLL) circuits (see 5.6) AN5 is used to sense whether or not the dc supply is within spec or not. 9

AN4 is multiplexed between the LINE control potentiometer and the Channel reference crystals temperature sense. Which analogue input drives this analogue input, is defined by the state of TEMP_LEVEL_IN which is a CPU output signal. AN3 and AN1 are inputs from the PLL circuits that sense the bias voltage on the VCO control varactor for each VCO. AN2 is used to sense the average peak voltage of the audio input. AN0 is used to sense the average peak voltage of the RF output. FRDY is an output from the flash. It goes low when the Flash starts to write a byte of data, or erase a block, or erase the whole chip, and it returns to its default high state when the action requested has completed. FPSW1 is the switch input from the PTT Test pin. FPSW2, and FPSW3 are two pins that have been reserved for future use as switch inputs. LOOP/VOLTS_SEL is a CPU output that when high applies 12V of dc feed to the audio output. TONE_DEV_U/D and TONE_DEV_INC are CPU outputs that are used to control the digital potentiometer that sets the TONE deviation level. (see 5.5) EXT_TONE_SEL is a CPU output that when low enables differential analogue input from the TONE+/TONE- pair. (see 5.5) LINEINP_ADSEL is a serial bus select pin. It selects the quad Digital to Analogue converter (DAC) that sets the levels for the two Line input Voltage Controlled Amplifiers, the output RF power amplifier bias voltage, and the LCD bias circuit. (see 5.4) LINEINP_DSEL is also a serial bus select pin. It is used to select the shift register that is used to control most of the analogue switches in the audio Line input circuitry, as well as the digital POT used to set the maximum deviation level. (See 5.4) PWR_CNTRL_HIGH is a CPU output that can be low, tri-state, or high. This adjusts, slightly, the range of the power amplifier bias circuitry allowing finer control of the output power level. (see 5.4 and 5.8) CTCSS_SEL is a serial bus select pin. It is used to select the FX805 chip(U500), which is used to generate CTCSS tones. (see 5.5) CHAN_PLL_SEL is a serial bus select pin. It is used to select the PLL chip in the Channel PLL circuit (U604). (See 5.6) SIGGEN_ADSEL is a serial bus select pin. It is used to select the quad DAC in the RF area. This DAC controls the reference oscillator bias voltages, and the BALANCE voltage controlled amplifier. (See 5.6) CHAN_VCO_EN is a CPU output that enables (when high) the Channel VCO. (See 5.6 and 5.7) EXT_REF_DIV is a CPU timer input. It is the output of the external reference clock divided by 3200. The software can measure what the reference frequency is, and then use this input to calculate the frequency error of the channel PLL reference oscillator. It can then adjust the channel reference oscillator to reduce this error to less than 0.3ppm. (See 5.6) SPARE_SEL is a serial bus select. It has been reserved for future use, and has been brought out to the rear DB25 connector. (see 5.1) 10

CH_EN is a serial bus select. It is brought out to the rear panel and is used to interface to the channel encoder on the rear daughter-board. (See 5.1) Any GPS pulses are isolated from the on-board electronics by the opto-isolator U212. The output of that opto-isolator is then connected to the GPS timer input of the CPU. This has been included for future use to be able to auto-adjust the reference oscillator frequencies to low, or high frequency clock pulses from an external clock reference of a GPS receiver. TERM_EN2 and TERM_EN1 are used to enable (when low) 600 ohm termination of Line2, and Line1 respectively. (See 5.3) The Fo outputs from the Modulation PLL and the Channel PLL are divided by two, and these are called FO_MOD_2 and FO_CHAN_2 respectively. They should be 200Hz square waves, except for brief periods when frequencies are being changed. (See 5.6) ECLK is a pin that at start-up only, should have the CPU system clock of 7.3728MHz on it. TX_LED, ALARM_LED, are CPU outputs that drive (when low) the TX LED, and the ALARM LED on. T/R_RELAY_H, when high, drives the T/R RELAY output low, and also enables the RF power amplifier. The T/R RELAY output can activate at least one conventional 12V relay. (See 5.1) SCLK, and MOSI are used as the core of a serial bus. SCLK is a clock pin, and MOSI is a bi-directional data pin. PA_CS is a serial select pin. It is passed, via the rear DB25 connector to the External Power Amplifier (PA). (See 5.1) DBGTX_TTL, DBGRX_TTL are RS232 transmit and receive (TTL) data pins which are connected to the debug port after conversion to/from RS232 compatible voltage levels by U202 and U201. TXD_TTL, RXD_TTL, RTS_TTL, CTS_TTL, DTR_TTL, DSR_TTL, are RS232 data pins which are connected to the main front panel serial port after conversion to/from RS232 compatible voltage levels by U202 and U201. PTT_uPHONE is a CPU input and it reflects the state of the PTT pin on the microphone handset. TONE_INT is a CPU input that comes from the FX805 (U500). This pin is used to indicate when a Tone has been decoded, or there is some other need to service the FX805. As yet, this pin is not used in the T50. (See 5.5) LOOP_DET is a CPU pin that is asserted low if there is dc loop current detected through the centre tap input of Line2. (See 5.3) FILTER_OFF is a CPU output that is used to by-pass, when low, the low pass filter in the Tone Input Circuitry. (See 5.5) PTT-in is an input from the rear DB25 connector that causes the INT pin of the CPU to be asserted (low) when 1mA of current is drawn via that pin. If PTT-in is pulled to ground, through a resistance of at most 3.9kohms, it will cause INT to be asserted. If it is pulled low via a 2K2 resistor, and as many as three diodes in series, it will still cause the INT pin to be asserted. This latter example shows that quite complex diode logic can be used on this pin. BKGD is a bi-directional I/O pin used to communicate with the core of the CPU. It is connected to the debug port and is utilised by specialised hardware to control the CPU externally, even without any firmware being present in the Flash. 11

MORSE is a CPU output that can be used to generate a CWID (Continuous Wave Identification) code. This is a 1028Hz tone which is keyed on and off in a Morse code as a staion identifier. (See 5.4) The RESET pin is both a low active input and a low active output to the CPU. If generated externally to the CPU, it forces the CPU into reset, and if the CPU executes a RESET instruction, this pin will be driven low by the CPU. Whenever there is insufficient volts (< 4.65V) on pin 2 of the MC33064D (U203), it will keep its RES output low. After the voltage has met the right level it will assert its output low for another 200 milliseconds. Thus the CPU will be held in reset until VCC is at the correct level. Thus the PWR_OK LED will only light when VCC is within specification, and RESET has been released. S200 is a momentary push-button switch that, when pressed, will cause the CPU to be reset. MOD_PLL_SEL is a serial bus select pin. It is used to select the Modulation PLL chip (U602). (See 5.6) LCD_DB7, LCD_RS, LCD_R/W, and LCD_E are reserved for interfacing to an LCD display module. Note that this feature has not been implemented. U205 is used to select whether the Flash or RAM is to be read or written. U207 is a single supply, 5V, TSOP40 Flash chip of size 8, 16, or 32 Megabits, and is used to store the firmware. U208 is a 1, or 4, Megabit Static RAM in an SOP-32 package, and is used for both code and data. The code in the RAM is copied from the Flash, at start-up.

5.3 Audio Pr ocessing Section (Sheet 3)

Sheet 3 is a schematic, which itself refers to two other sheets. Sheet 3 shows how the two Line inputs go to audio transformers T300 and T301, are then optionally terminated by analogue switches U301B, and U301C, before being passed to the audio input stages described by Sheet 4. It also shows how the Direct Audio (TONE) signal is passed to the Tone circuitry (sheet 5). It also shows how dc current in Line1 will cause the opto-isolator (U300) to generate the CPU input LOOP_DET. Relay RL300 is used to drive current back through an externally generated dc loop, when the CPU output LOOP/VOLTS_SEL is high. The output of the Tone circuitry and the Audio circuitry are mixed (summed) and amplified by U302. It is then passed through a high order low pass filter (3.1kHz), before being attenuated by digital POT U303. U403D adds an extra 1.8% gain of the summed modulation signal. It effectively adds another bit of control to the maximum deviation level. The Digital POT (U303), in conjunction with U403D, set the Maximum deviation. U302C then adds 6dB of gain before sending the audio to the modulator. R317, D307, and C304, act as an average peak detector. This enables the CPU to determine the size of signals being handled by the audio section. 12

Note that the Line inputs, and the TONE input, are protected by transils and fuses against accidental connection to damaging voltages. The fuses (F300, F301, and F302) are not user replaceable. They are surface mount devices and must be replaced by authorised service personnel.

5.4 Line Input Pr ocessing Section (Sheet 4)

The two audio inputs are passed, after transformer coupling, to sheet 4. In Sheet 4, the two Line Inputs are input to a transconductance amplifier (U402A, and U402B). A transconductance amplifier is a current controlled, current amplifier, i.e. it amplifies input current, but its level of amplification is controlled by the level of current that is injected into pin1 (or pin16). By converting a DAC output into a current, and converting the input voltage into an input current, U402A and U402B are converted into Voltage Controlled, Amplifiers(VCAs). Two of the DAC outputs are converted to currents by U400B, U400C, Q401, and Q400, and these currents are used to control the gain of the transconductance amplifiers. The input voltages are converted to current by the input load resistors R402, and R403. The output currents are converted to voltages by resistors R420 and R424. The outputs of the transconductance amplifiers are buffered by the darlington buffers provided with the amplifiers (U402C, and U402D). The output of each VCA is then amplified by U405B and U405C respectively. The level of amplification of each VCA is adjusted in software in accordance with any adjustments made to the LINE POT. The software converts the linear range of the LINE POT into a logarithmic scale, such that if the LINE POT is wound down to zero, the amplification of each VCA is reduced by 12db relative to its centre position. Similarly if the POT is wound to its maximum position, both amplifiers increase their gain by 12dB. The outputs of these amplification stages are then attenuated. Analogue switches U404A and U404Bare used to select which attenuation circuit is used for Line 2, and U404D and U404C are used to select which attenuation circuit is used for Line 1. If the resistive divider formed by R425, R426, and R439 is selected then the Line 2 audio signal frequency response is unaffected (it is Flat). If the reactive divider defined by C402, R431, and R439 is selected, then higher frequencies of the Line 2 audio signal are attenuated less than lower frequencies, i.e. Pre-emphasis is applied to the audio signal. Line 1 has an identical circuit. The outputs of these pre-emphasis/flat frequency response attenuators are then buffered by U405A, and U405D respectively. The microphone input is amplified by U400D, after being limited by D400. It is passed through a pre-emphasis network (defined by C404, R433, and R436), and is enabled, or disabled by switch U403A. The outputs of the Line 1 conditioning circuit, the Line 2 conditioning circuit, and the microphone input amplifier, are then mixed (summed) and amplified by U407A. Its output is, in turn, amplified by U407B, but the gain of U407B is either 2.7 or 27 depending on the state of analogue switch U403B. The CPU is capable of injecting a signal into the audio path. This can be achieved via the MORSE output. This is partially filtered by R446 and C421. C420 provides DC 13

isolation, and R446, and R448 set the level to be approximately 30% of maximum deviation. The output of U407B is passed (signal LINE_INP) to the Line Level Sense circuitry (sheet 3) so that the CPU can determine the input line level. U407Bs output is also passed to the limiter defined by D402, and D401. Resistors R442, and R444 are used to soften the clipping, i.e. to round off the edges as the voltage hits the clipping levels. This reduces the level of the lower order harmonics produced. U407C then buffers the output for mixing with the tone output circuitry. The PWR_CNTRL_RAW DAC output is used to control the bias to the on-board RF amplifier (see Sheet 8). The CPU output pin PWR_CNTRL_HIGH is effectively summed with the DAC output to define three control ranges: State of PWR_CNTRL_HIGH TriState Low (0V) High (5V) Table 9: Power Control Ranges. Note that in practice only the first two power ranges are used. U401 is an octal shift register and octal latch combined. When there is a rising edge on LINEINP_DEN, the 8 shift register outputs are latched into the octal latch. The outputs of the octal latch are the outputs Q0 to Q7. Thus the last 8 data bits clocked onto MOSI, by SCLK, before LINEINP_DEN is clocked high, will appear on Q0 to Q7. U406 is a quad 8 bit DAC. The CPU communicates with the DAC via SCLK, MOSI, and the select signal LINEINP_ADSEL, which is low when the DAC is selected. U302B is used to convert the DAC output into a bias level for the LCD. Note that, at this stage, the LCD display option is not developed. PWRCNTRL Voltage Range 2.98 5.86 0.6 3.0 3.55 - 5.96

5.5 Tone Gener ation Section (Sheet 5)

U500 is a CTCSS tone encoder and decoder. The integrated circuit is also capable of generating DCS signals. The CPU accesses U500 via the serial bus using MOSI, SCLK, and the low active Select signal CTCSS_SEL. The output of the tone generator is mixed (summed) with any signals that are allowed through analogue switch U301D. U502 is set up as a balanced differential amplifier. The resistors R530, R531, R508, R509, R510, R532, R533, and R511, are precision resistors to improve the CMRR of the differential amplifier. U502A amplifies, as well as mixes, the two audio inputs, and its output is either passed through a low pass filter (at 250Hz), or not, depending on the state of analogue switch U301A. The output of U502C is then attenuated by a digital POT, before being buffered by U502D.

14

The digital POT performs two functions. It is used to help set the maximum CTCSS tone deviation. It does this in conjunction with U500, as it is also possible for the CTCSS tones that are launched by U500 to be adjusted using software. The second function of the digital POTs is enabled when U301D is enabled. The level of attenuation by the digital POT is adjusted as part of the calibration procedure to set the tone deviation caused when a signal is applied to the tone input. R526, D502, and D503, form a limiter, that prevents any signal arriving from the TONE pair from ever exceeding 3kHz deviation.

5.6 Fr equency Synthesiser (Sheet 6)

This circuit also includes Sheet 7 as a block diagram. Sheet 7 contains the schematic for the two Voltage Controlled Oscillators. There are two complete Phase Locked Loops. One is called the Modulation PLL, and the other is referred to as the Channel PLL. The Modulation PLL does change frequencies slightly, but by less than +/- 240kHz. The Channel PLL is the principal PLL that changes frequencies when the exciter changes frequency. As its name suggests, modulation is performed on the Modulation PLL. The modulation is a conventional 2 point FM modulation. Modulation by signals, whose frequency components are well below the PLL loop frequency, is effected by modulating the reference oscillator of the Modulation PLL. Frequencies well above the PLL loop frequency are effected by modulating the Modulation VCO directly, and frequencies in the cross-over region are a combination of the two. The heart of this schematic are the two PLL chips U602, and U604. Each is, in fact, a dual PLL chip, but only one PLL, in each, is used. All that is used of the second PLL chip is its dividers. The outputs of these dividers can be switched to the FoLD output pin, which is then converted to a square wave by a further division of 2 by U606A and U606B. By using the second PLLs dividers it is possible to divide the reference oscillator, and the VCO output down to frequencies that can be handled by the Timer inputs of the CPU, without causing excessive interrupt load to the CPU.

5.6.1

The Modulation PLL

U602 and the Modulation VCO (see Sheet 7) form the modulation PLL. U602 acts as its own crystal oscillator for its reference oscillator. X600 is a 5ppm, 12MHz, crystal. Its resonant point is adjusted by the bias applied to varactor D600. The bias applied to varactor D600 is a combination of the potentials at two DAC outputs (MOD_ADJ and MOD_ADJ_FINE), plus the modulating signal arriving at MOD_IN (which is the same signal as MOD_OUT in Sheet 3). The summing of these three voltages is performed by U607. The Phase detector output of the PLL chip is then passed through the loop filter network defined by C612, R618, C625, R617, C613, and C718 (see Sheet 7). L713 is used to filter out any residual noise (outside of the audio bandwidth), including the phase detector frequency, and/or any switch-mode noise from the dc voltage rails. The loop filter signal is then fed as a control voltage to the Modulation VCO (MOD_PLL_IN). 15

The output of the Modulation VCO is connected back to the PLL for phase detection via signal path MOD_VCO_OUT. The phase detector output is also buffered and attenuated for the analogue input of the CPU. This is the function of U600, R622, and R625. In this way the CPU can monitor the VCO bias to ensure that it is within specification (>0.5V, and < 4.5V). The FoLD pin, of U602, can be used for many purposes. It can be connected to the output of any of the 4 internal dividers, or be used as a LOCK-DETECT monitor, or as a user programmable output pin. In this circuit it is used as a LOCK-DETECT output when the frequency is being changed, but otherwise it is connected internally to the unused reference divider of U602, to deliver a 400Hz pulse train to FoLD. U602 is set up with a phase detector frequency of 20kHz.

5.6.2

The Channel PLL

U604 and the Channel VCO (see Sheet 7) form the Channel PLL. U604 acts as its own crystal oscillator for its reference oscillator. X601 is a 5ppm, 12MHz, crystal. Its resonant point is adjusted by the bias applied to varactor D601. The bias applied to varactor D601 is adjusted by the CHAN_ADJ DAC output. The Phase detector output of U604 is then passed through the loop filter network defined by C622, R620, C626, R619, C623, and C725 (see Sheet 7). L718 is used to filter out any residual noise (outside of the audio bandwidth), including the phase detector frequency, and/or any switch-mode noise from the dc voltage rails. The loop filter signal is then fed as a control voltage to the Channel VCO (CHAN_PLL_IN). The output of the Channel VCO is connected back to the PLL for phase detection via signal path CHAN_VCO_OUT. The phase detector output is also buffered and attenuated for the analogue input of the CPU. This is the function of U608, R623, and R624. In this way the CPU can monitor the VCO bias to ensure that it is within specification (>0.5V, and < 4.5V). The FoLD pin, of U604, can be used for many purposes. It can be connected to the output of any of the 4 internal dividers, or be used as a LOCK-DETECT monitor, or as a user programmable output pin. In this circuit it is used as a LOCK-DETECT output when the frequency is being changed, but otherwise it is connected internally to the unused reference divider of U604, to deliver a 400Hz pulse train to FoLD. U604 is set up with a phase detector frequency of 31.25kHz. The signal CHAN_VCO_EN is an output from the CPU that is used to turn on (when High) or turn off (when low) the Channel VCO.

5.6.3

The External Reference Divider

The external Reference Input (EXT_REF_IN) is buffered by an attenuator network formed by R628,R633, and R630 in parallel with R635. This also forms a 50 ohm termination network for the reference input. R628 is a 1 watt resistor, and so, in theory levels as high as +30dBm can be accepted. To be safe, though, the largest signal that is approved to be accepted is +26dBm. Q600 is set up as a switching transistor, and with a sufficiently high input signal level (> +5dBm), it will clock U605. U605 is set up as a divide by 128 circuit, and its output is then divided by U606 by 25.

16

The two unused, divide by two, stages of U606 are then used to convert the 400Hz FoLD pulse trains into 200Hz square waves for the Timer inputs of the CPU.

5.6.4

The DAC

U601 is a quad DAC. It is programmed by the CPU via the serial bus (SCLK and MOSI). It is selected by the low active signal SIGGEN_ADSEL. Three of its outputs are used to adjust the reference oscillators. In the presence of an external reference oscillator, the software will automatically track the channel VCO to the external clock. The modulation reference oscillator is always tracked as closely as possible to the Channel reference oscillator. Because of this need for very close tracking, two DAC outputs are summed. In this way, the CPU is given coarse, as well as fine control. The CPU can sense a phase difference of 136ns in 4 seconds, i.e. as little as 0.034ppm between the two PLL reference oscillators. Each step of the MOD_ADJ_FINE DAC output will move the frequency about 2% of this amount. The other DAC output (BALANCE) is used to adjust the BALANCE VCA (see sheet 7). The user programmable digital output of the DAC (MOD_VCO_EN) is used to enable the modulation VCO (when High)

5.6.5

The VCOs and the RF Output

These are more closely described in 5.7, but it is worth noting that there are three primary outputs of the VCOs. There is each VCO output itself, but also the signal VCO_OUT. This is the difference frequency between them. Generally the modulation VCO is set to oscillate at 320MHz. To get an output of 40MHz, the Channel VCO is set to 280MHz. But if you wanted an output frequency of, for example, 40.00125MHz, then the modulation VCO would change to 319.78125 MHz (i.e. it drops by 218.75kHz), and the Channel VCO would become 279.78MHz (i.e. dropping by 220kHz). By such small changes in the modulation VCO (maximum delta is +/- 240kHz), each multiple of 1250Hz can be accommodated, without any need to ever change the two phase detector frequencies.

5.7 Voltage Contr olled Oscillator s (Sheet 7)

JFETS Q704, and Q705 are the heart of two Colpitts oscillators. The capacitor feedback divider for Q704 (modulation VCO) is defined by C732 and C733, and this shapes the negative impedance looking into the drain of Q704. In the Channel VCO, C740 is effectively in series with Cgs of Q705. These, then define the negative impedance looking into the drain of Q705. L716, in parallel with L726 forms the tank coil for the modulation oscillator, and the resonant capacitance is defined by the series combination of C750 and the capacitance across D701. L712 has +ve reactance and it acts to reduce the minimum effective capacitance seen back through C750, thereby increasing the tuning range slightly. Similarly, L719 is the tank coil for the channel oscillator, and the resonant capacitance is defined by the series combination of C751 and the capacitance across D704. L717 has +ve reactance and it acts to reduce the minimum effective capacitance seen back through C751, thereby increasing the tuning range slightly. 17

The VCO frequencies are controlled by the bias applied to D701 and D704 respectively, which is set by signals MOD_PLL_IN and CHAN_PLL_IN. These signals are the phase detector outputs from the Modulation PLL and the Channel VCO respectively (see Sheet 6). Diodes D700 and D703 are used to provide some AGC for the JFETs. These Schottky diodes will increase the ve bias on the gate of the JFETs (thereby decreasing the drain current) if the oscillation level should increase, and similarly the gate bias will reduce if the ve peaks of the oscillation should reduce. The Modulation bias is also adjusted by the modulation input (MOD_IN). This signal is amplified by a VCA. The BALANCE DAC output is converted to a current by U707 and Q700, and that then is used to set the gain of the VCA. The output of the VCA is then attenuated by R725/R729, and this bias is then applied to varactor D701. Note that the modulation bias is in anti-phase to the PLL bias. Each VCO has its own gyrator feed circuit (Q707 and Q702). This is done to remove any possible noise on the voltage rails from modulating either VCO. The drain current of each VCO can be switched off or on by MOSFETs Q701 and Q703. Q701 is switched on when MOD_VCO_EN is high. MOD_VCO_EN is the user programmable digital output from DAC U601 (see Sheet 6). Q703 is switched on when the CPU output CHAN_VCO_EN (see Sheet 2) is high. The output of each VCO is sniffed, by a high impedance attenuator. In the modulation VCO, R737 in series with the 50 ohm input impedance of U702 forms this attenuator. In the Channel VCO, R745, R736, and the input impedance of U706 form one such attenuator, and R741 in series with the input impedance of U703 forms the other. Note that there is a low pass filter in the front of U702, and U706 to reduce the level of spurious signals generated by intermod in these two amplifiers, U702 amplifies the modulation VCO signal, which is then amplified again by U701, then filtered to reduce harmonics, before arriving at the LO input of MX700 at a level of around +5 - +7dBm. The output of U702 also has a low pass filter to reduce the level of harmonics arriving at the mixer. The output of the MOD VCO is also attenuated by R733, and then re-amplified before becoming MOD_VCO_OUT. MOD_VCO_OUT is then passed to the Modulation PLL (U602, see Sheet 6). U705s primary role is to ensure that noise that becomes coupled by the PLL chip, back onto its VCO input, does not couple back into the path to the mixer. If this isnt done, then the mixers LO input contains many harmonics of the reference oscillator. U703 performs both an amplification role, and an isolation role similar to U703s. Its output (CHAN_VCO__OUT) is fed back to the Channel PLL (U604, see Sheet 6). The output of U706 is attenuated by the network R714, R742, and R724, and it is filtered to reduce harmonics as much as possible. This filtered VCO output is then brought to the RF pin of the mixer at a level of about 19dBm. The output of the mixer is then run through a low pass filter to remove frequencies other than (Fmod - Fvco). U700 then amplifies this signal to a level of about 6 to 8dBm. The external output signal of T/R_RELAY, which is asserted low whenever the exciter is keyed up, is used to switch MOSFET Q706 off. When Q706 is off, amplifier U700 is enabled. When T/R_RELAY is high, then U700 is deprived of bias current and VCO_OUT is then completely disabled.

18

5.8 1W Br oadband HF/VHF Power Amplifier (Sheet 8)

The RF output of Sheet 7 (VCO_OUT) becomes the primary input to this circuit (RF_IN). This RF input is first amplified to a level of about +2 to +4dBm by U800, then it is amplified by Q801 to about +20dBm (with full bias), and then it is amplified by Q804 and Q805 to +30dBm. The output stage gain is less above about 42MHz, so that the peak output power falls to about +26dBm at 50MHz. The effective gain of Q801 is controlled by adjusting the bias level (PWRCNTRL). This can vary from 0.6V to nearly 6V, and is adjusted by a DAC output and a CPU digital output, in Sheet 4. The software monitors the forward power sense in the External Power Amplifier(PA) as well as the Reverse Power, temperatures, drain currents etc. It does this via the serial bus (formed by SCLK and MOSI) and the select pin for the ADC converter on the External PA (PA_CS). The software then automatically adjusts the PWRCNTRL bias to: 1) 2) Keep the forward power at the level defined by parameter PA_SET_FWD_PWR (see 4.1), unless, If the reverse power is > PA_SET_FWD_PWR*REV_PWR_ALARM/100.0 then the forward power is reduced until the reverse power stops exceeding this limit, or, The temperature of the PA output stage FETs exceeds 120C, in which case forward power is reduced until this stops occurring.

3)

5.9 Power Generation Section (Sheet 9)

There are three switch mode dc-dc converters in the board. These use monolithic converters based on the National LM2595. Two of the converters are 12V converters and one is a 5V converter. The power in to the whole exciter is the voltage rail 28V. U907 converts this down to 12V. U908 is set up as an inverter, and uses the 12V rail to create 12V. U909 converts the +12V rail to +5V for all the digital circuitry. The +12V rail is used to power the on-board relay, as well as up to one extra off-board relay. It is also dropped, via a linear regulator (U910) to produce the +10V rail, which in turn is dropped by another linear regulator U911 to produce +5Q, which, in turn, is dropped by a further linear regulator (U912) to produce +2.5V. Similarly U913, U914, and U915 are linear regulators that produce 10V, -5V, and 2.5V from the 12V output of U908. +10, +5Q, and +2.5V, -10V, -5V, and 2.5V rails are used in the audio and RF sections. D911 is a 4.096V (3%) reference diode. Its output is buffered by U906 which then produces a reference voltage rail Vref, which is used by the CPUs A/D converter, and the DACs, and also in the voltage to current converters of the VCAs (see Sheet 4, and Sheet 7).

19

6 FIELD ALIGNMENT PROCEDURE

6.1 Standar d Test Equipment
Some, or all of the following equipment will be required: AF signal generator, 75 - 3000Hz frequency range, with output level set to 387mV RMS and, if the microphone input is to be tested, 10mV rms output. Power supply set to 28Vdc, with current >10A. RF 50 load(s), 250W rated, return loss <-20dB, and total attenuation of 50dB Reference Clock. At least +6dBm output. The external reference frequency is limited to: 500kHz, or any multiple, any multiple of 128KHz greater than or equal to 512kHz, any multiple of 160KHz greater than or equal to 480kHz In Rev 4 or earlier revision systems, the external reference clock is limited to 10MHz. In Rev 5 or later systems, the external reference clock can be as high as 24 MHz, and can have an output level as low as 0dBm. The accuracy should be at least 0.5ppm, preferably 0.1ppm RF Peak Deviation Meter True RMS AC voltmeter, and a DC voltmeter. RF Power Meter (accurate to 2%, i.e. 0.17dB) Some means of measuring Reverse Power, and a known 3:1 mismatched load.

6.2 Invoking the Calibration Pr ocedur e Manually

From Version 4 of the firmware, and version 1.4 of WinTekHelp, the calibration procedure can be performed through a Windows front end program. This is documented in the WinTekHelp manual. As well as the Windows based calibration procedure, the firmware still supports the older command prompt method, which is described in this section. The T50 has in-built firmware to perform calibration. This firmware requests the user for information as to meter readings, and/or to attach or adjust an AF signal generator. The firmware based calibration program can be accessed from a terminal, a terminal emulator, or the WinTekHelp terminal emulator. If the user selects the Go to the Prompt Window option from the main menu, they can manually type commands to invoke the calibration procedure. When the exciter is ready to accept commands it echoes the following prompt: T50> Via a terminal, or a terminal emulator, a user can type various commands in. The basic command to start the calibration procedure is: T50> cal calibration_type Where calibration_type is one of: a) misc: Miscellaneous parameters are defined and calibrated 20

b) c) d) e) f)

dev: Maximum deviations are set (automatically forces a cal line and a cal tone) line: Line1, Line 2, Dir Aud (Tone), and microphone inputs are tested and calibrated. pwr: The External PA attached to this unit is calibrated. ref: The reference oscillators are adjusted and calibrated tone: The maximum tone deviations are calibrated

6.2.1

The Miscellaneous Calibration Procedure

T50> cal misc

This procedure should not normally be invoked as part of any field maintenance. The program will print out the Model Name and Serial Number of the exciter. If these parameters havent already been defined (e.g. at an initial calibration, at the factory, the service personnel will be prompted to enter these values). Then it will ask the operator to enter the value of Vref (as measured at TP913, see 5.9). Measure the voltage, at TP913 (Vref) and type it on the command line... Unless the reference diode D911 has been replaced, this should not be done. The user should simply hit the Enter key to bypass this operation. If, though, D911 has been replaced for some reason, then, the reference voltage can be measured either on TP913 or pin 4 of P3. Then the exciter low battery alarm level will be asked for. If the current value is acceptable, the User need only hit the Enter key on the keyboard. If another value is preferred, then that value can be typed in. For example: The Exciter's Low Battery Alarm is 24V If this is correct enter < RET> , else enter the new value: 26 In this example, the low Battery Alarm level is changed to 26V. Then the user will be prompted for serial port baud rates, parities etc. At present only No parity and No flow control are supported. The WinTekHelp software will expect 57600 BPS, and No Parity, and No Flow Control. Note well, that if you do change any of these, the change will not take effect until you power down the exciter and then power it up again. (As an alternative to power cycling the exciter, and if the cover is off the exciter, you may simply press the momentary push-button switch S200 (see 5.2). The next thing the calibration program tests is the state of the LINE pot. The program will ask the user to adjust this pot. If the Potentiometer is below centre, it will ask the user to adjust it up (i.e. adjust it clockwise). If it is above centre, it will ask the user to adjust it down (i.e. adjust it counter clockwise). When the POT has been centred, or, the User hits the Enter key, the program will terminate. This last step is normally only done as part of a factory install, and it is done to ensure that the POT is centred before being shipped to customers. For field maintenance purposes, the step should be skipped in order to leave the LINE POT at the setting formerly desired.

6.2.2

The Reference Calibration Procedure

T50> cal ref 21

To compensate for crystal ageing and other component parameters that drift over time, the following procedure should be performed approximately once per year. If your exciter is fitted with the external reference option (an extra BNC connector on the rear panel), the user can connect an external reference directly to the rear BNC connector. If the exciter does not have this option, then the top cover of the exciter should be removed and an external reference oscillator should be connected via a 50 ohm probe to J4 (just to the right of the DC voltage regulators and converters). The external reference clock, should have a power level from +6 to +26dBm and any frequency that meets the following criteria: 500kHz, or any multiple, or, any multiple of 128KHz, greater than or equal to 512kHz, or, any multiple of 160KHz, greater than or equal to 480kHz. The frequency should be 10MHz or less in Rev 4 or older versions. In Rev 5, and later versions the frequency can be as high as 24MHz, and at power levels as low as 0dBm. No User input is required, except to hit the Enter key when the external reference is connected. The firmware will automatically adjust both reference oscillators, and save the new DAC adjustments in FLASH (as parameters) to be used to centre the oscillators each time the unit powers up. The user should see the following output. (Note that the temperatures, frequencies, error values, serial number, etc, indicated are examples only) Connect an external reference input or the clock output from a GPS receiver to the GPS input. Enter < RET> when this has been done. External Reference is 10.0MHz Ensure that the displayed reference frequency (10.0MHz in the above example) is the same as the frequency of your oscillator. Waiting for a GPS clock. ...... The system waits here for a GPS reference to be seen. At this stage, this method of calibrating the clocks has not been validated by RFT Engineering, so do not attempt to use this option. Then the firmware continues. Have not observed a GPS clock System Frequency relative to external clock is 7372654.32 The crystal temperature is 32C. Waiting up to 1 minute for clocks to stabilise. ...... The crystal temperature is 32 C The channel ref error = 1 cnts or, 1.63 Hz The mod ref error = 1 cnts or, 1.63Hz The user may see the following error message. The Model Name is T50_REV4 and the Serial Number is RT11500 Please take note of the Model, DAC values, serial number and crystal temperature, and report this problem to RFT Engineering. 22

If a message, similar to this is seen, it indicates a potential fault condition. If the final text indicates that the channel and mod reference errors are within specification (the last text output), then the unit is able to be used, but nonetheless, it is advisable that an email be sent to RF Technology indicating the problem. Such a problem may be caused by a crystal having aged to such an extent, that it is getting close to the region where it may soon, no longer be adjusted, or that, with further degradation, the low frequency performance may be compromised. As no other calibration procedure requires the top cover to be removed, you should replace the cover, should you have had to remove it for this procedure.

6.2.3

The Deviation Calibration Procedure

T50> cal dev

This procedure should not normally be invoked as part of any field maintenance. The only conceivable time that it might ever be used, would be if a non standard maximum deviation was required. Note that the nominal output power of the exciters output is 1W. Whilst the power level is not set to the maximum level, the deviation meter should either have an input power rating of at least +30dBm, or suitable attenuation is required between the exciter and the deviation meter. Note that for this test the nominal RF output frequency is 37.5MHz. The first stage begins with the following message: This procedure sets the Balance and Max Deviation Levels Connect an audio signal generator to the External Tone input Set the output to be a sine wave, 3.87 V rms and 120Hz Disconnect the RF connection to the PA and connect a deviation meter to the exciter's BNC output, and use a CRO to monitor the Audio output from the deviation meter. The Channel VCO Bias is 2.5V The Modulation VCO Bias is 2.3V. Enter + or to increase or decrease the Balance, until the CRO signal is as symmetric as possible. ? Here the user can hit the +, p, or P, keys to increase the Balance, or -, m, or M keys to decrease it. In response, the firmware, which has opened up the maximum deviation digital POT (U303) to maximum gain, will adjusted the Balance VCA accordingly. This test applies a very high level to the External Tone Input which becomes saturated by the limiter for the Tone input. The result is a square wave with a slight ring on the edges. The ringing is caused by the elliptical filter used as a 3kHz low pass filter. If the modulation balance is not working properly, the top edges of the resulting modulated signal will be slewed. Then the firmware will make the following request. change the signal input to Line 1, and adjust the frequency till the deviation peaks When this has been done, the User needs to hit the Enter key, and the following will appear again. Enter + or - to increase or decrease the deviation, and < RET> when the deviation is 5kHz 23

? In response to the +, or keys (or m, p, M, or P), the firmware adjusts the deviation digital POT. The user should do this until the deviation is about 200Hz below the value shown. The firmware will now repeat this for the following standard deviations, 5.0kHz, 4.5kHz, 4.0kHz, 3.5kHz, 3.0kHz, 2.5kHz, 2.0kHz, and 1.5kHz.

6.2.4

The Tone Deviation Calibration Procedure

T50> cal tone

This procedure should not normally be invoked as part of any field maintenance. Note that if the deviations are calibrated, then this procedure will be automatically invoked. This procedure is similar to the maximum deviation procedure (See 6.5). The Line 1 and Line 2 audio paths are turned off for this procedure, as is the Direct Audio (TONE) input. The only signal sent to the modulator is a tone of 107.2Hz. The program starts off, with the following message: This procedure sets the maximum tone deviations for a Max Deviation of 5kHz. Note that the actual maximum tone deviations automatically scale with the Max Deviation. eg a 500Hz tone deviation would be a 250Hz tone deviation when a 2.5kHz Max Deviation was chosen. Disconnect the RF connection to the PA, and connect a deviation meter to the exciter's BNC output. The audio is being switched off, and 107.2Hz tone generated Thence a procedure that is almost identical to that used for setting maximum deviations is used to set these tone deviations. There is one significant difference, though, and that is, as well as using + (or p, or P), and (or m, or M) keys to step the deviation up or down, one can also use the < key, or the > key. These last two keys will step down, or up, the level of signal transmitted by U500, whereas the other keys will modify the setting of the digital POT U503 (see 5.5). This procedure is used to set tone deviations of 750Hz, 700Hz, 650Hz, 600Hz, 550Hz, 500Hz, etc down to 150Hz.

6.2.5

The Line Calibration Procedure

T50> cal line

This procedure should not be used as part of any usual field maintenance, unless any component has been replaced that might affect the gain of any of the audio inputs. Note that if the deviations are calibrated, then this procedure will be automatically invoked. The program begins: Calibrating Line 1 and Line 2 audio levels Attach an audio signal generator to Line 1 Set the output to be a sine wave, 388mV rms and 1kHz Disconnect the RF connection to the PA and connect a deviation meter to the exciter's BNC output. Enter + or - to increase or decrease the deviation, and < RET> when the deviation is 3kHz. ? 24

This is the same mechanism that is used in 6.5 and 6.6. The user enters +, p, or P to increase the Line 1 gain, to increase the deviation, or, -, m, or M to decrease the gain. The user hits the Enter key when the desired deviation is set. Now attach the audio signal generator to Line 2 Enter + or - to increase or decrease the deviation, and < RET> when the deviation is 3kHz ? Again the user enters +, p, or P to increase the Line 2 gain, or, -, m, or M to decrease the gain. The user hits the Enter key when the desired deviation is set. The firmware goes on to open the microphone audio path (note that the microphone PTT switch does not need to be depressed for this). Note also that the application of a 10mV test input is a factory only test. An adequate test in field testing, would be to speak into the microphone and see that the deviation meter responded accordingly. Testing the microphone input. Attach an audio signal generator to the microphone input. Set the output to be a sine wave, 10mV rms and 1kHz. Ensure that the deviation is between 2.7 and 3.3kHz Enter < RET> when measurement complete. Alert Engineering if there is a failure. Then the Direct Audio input (with the low pass filter off) is tested. Testing the Tone input. Attach an audio signal generator to the Tone input. Set the output to be a sine wave, 129mV rms, and 1kHz. Enter + or - to increase or decrease the deviation, and < RET> when the deviation is 1kHz ? And then user then follows the same procedure as defined for setting the Line 1 and Line 2 gains.

6.2.6

The Power Calibration Procedure

T50> cal pwr

All Power Amplifiers are calibrated ex-factory. All the important parameters, such as the forward and reverse power sense adjustment, and drain bias settings are not dependent on the exciter, and thus any factory calibrated PA50 power amplifier can be connected to, and work correctly with any T50 exciter. The frequency range of the amplifier is defined by three jumper settings on the external PA, which the CPU can detect. Thus the CPU knows (on power up) what frequencies are, or are not, possible to be used with the PA. The exciter may store some PA specific parameters, such as the Serial Number of the PA, and also some offset values for the pre-amp drain current, and the output stage drain current. These latter offsets improve the accuracy of the over current alarm testing, (but are not strictly necessary). In order to set these parameters, it is advised that this procedure be performed every time an exciter is used with a new External Power Amplifier. Note that many of the stages can be skipped if they have been performed before. The program begins:

25

This procedure is used to calibrate an External Power Amplifier. The existing PA's SERIAL NO is: 002356 Enter the new PA serial no: Simply hit the Enter key here if the Serial Number is correct. Take the lid off a PA, and set all three bias Pots (R238,R239, and R240) fully clockwise. Enter < RET> when done. Now we will set the Bias currents in the PA. Attach power to the PA. Each mV read across TP100(+ ve lead), and TP101(-ve lead), corresponds to 1mA of 1st stage Bias current. For power control in the range 50 - 150W, set the 1st stage bias to 35 - 40mA. For power control in the range 20 - 60W, use a bias of 15 - 20mA. Attach the millivoltmeter, and adjust R238 for the bias required. Unless one of the RF power transistors has been replaced, the user should simply skip these last four stages by hitting the Enter key four times. Attach the Power Amplifier to the Exciter, and ensure the PA is powered up. Attach the PA output to a reflectometer, the reflectometer to a 50dB (nominal) attenuator, and the attenuator to a calibrated power meter Enter < RET> when this has been done Adjust C209 in the Power Amplifier until there is a minimum in the dc voltage measured at TP204 Enter < RET> when done. Adjust the Forward Power Sense POT (R228) unti tthe measured output power (adjusted for the attenuator and reflectometer losses) is equal to the Preset Forward Power. Enter < RET> when done. Unless something has been modified in the power sense circuits, these last three stages should be skipped by simply hitting the Enter key three times. This next step allows the firmware to compute an offset in the output stage drain current, so that the exciters ability to measure the output stage drain current is significantly more accurate. Measure the voltage across TP102(+ ve lead) and TP103(-ve lead), and enter the value measured This next step allows the firmware to compute an offset in the pre-amp stage drain current, so that the exciters ability to measure the pre-amp stage drain current is significantly more accurate. Measure the voltage across TP100(+ ve lead) and TP101(-ve lead), and enter the value measured The next two stages can be skipped by simply hitting the Enter key twice. Attach the reflectometer to an open circuit Enter < RET> when this has been done Adjust the Reverse Power Sense POT (R227) until 26

the displayed reverse power equals 50W. Enter < RET> when this has been done. This then completes all the calibration procedures.

7 SPECIFICATIONS
7.1 Over all Descr iption
The transmitter is a frequency synthesized, narrow band, HF/VHF, FM unit, used to drive an external 120 watt amplifier. All necessary control and 600 line interface circuitry is included.

7.1.1

Channel Capacity

Although most applications are single channel, the T50 can be programmed for up to 256 channels, numbered 0-255. This allows a network administrator to program every exciter, in every site, the same way. By setting each site up to select which of the 256 channels is appropriate, any exciter can be plugged into any position, in any site, without the need to perform on-site re-programming. This can be convenient in maintenance situations. Channel information consists of two independent and complete sets of information, which may differ or be the same. One set defines the parameters to be used, if the unit is keyed up from PTT-in being grounded, and the other set defines the parameters to be used if the unit is keyed up for any reason other than PTT-in being grounded. The parameters that can be defined on a per channel basis are: a) b) c) d) e) The frequency The CTCSS tone (if any) to be generated, or, the DCS code (if any) to be generated. The delay from the initiation of the exciter to RF output being generated (Is specified in hundredths of a second, 0 999) The transmit tail; the length of time after the exciter is released before transmission stops. (Is specified in seconds 0 999). The No Tone period; a length of time after the expiry of (d) in which transmission continues, but with no tone being generated. (Is specified in tenths of a second, 0 999) Whether audio from Line 1, or Line 2, or both, (or neither!) is enabled, and whether or not Pre-emphasis is required, or not, on each line, and whether or not an extra gain pad (of 20dB) is required. What Nominal Tone Deviation, and Maximum Deviation should be used (See Tables 7 and 8)

f)

g)

7.1.2

CTCSS

Full EIA subtone Capability is built into the modules. The CTCSS tone can be programmed for each channel. This means that each channel number can represent a unique RF and tone frequency combination.

7.1.3

DCS

From Rev. 4 hardware and Rev. 4 firmware, support for DCS codes is supported. DCS code generation can be enabled on a per channel basis. If enabled, the 23 bit Golay 27

code containing the selected DCS code word will be generated continuously after the exciter is keyed up.

7.1.4

Channel Programming

The channel information is stored in non-volatile memory and can be programmed via the front panel connector using a PC, and/or RF Technology software.

7.1.5

Channel Selection

Channel selection is by eight channel select lines connected to the rear panel that mounts on the rear DB25 female connector. A BCD active high code applied to the lines selects the required channel. This can be supplied by pre-wiring the rack connector so that each rack position is dedicated to a fixed channel. Alternatively, thumb-wheel switch panels are available. By redefining illegal BCD codes, users can also encode channels from 100 255.

7.1.6

Microprocessor

A microprocessor is used to control the synthesizer, tone squelch, PTT functions, external reference monitoring, calibration, fault monitoring and reporting, output power level control, volume adjustment, line selection, option setting, and facilitate channel frequency programming.

7.2 Physical Configur ation

The transmitter is designed to fit in a 19 inch rack mounted sub-frame. The installed height is 4 RU (178 mm) and the depth is 350 mm. The transmitter is 63.5 mm or two Eclipse modules wide.

7.3 Fr ont Panel Contr ols, Indicator s, and Test Points

7.3.1 Controls
Transmitter Key - Momentary Contact Push Button Line Input Level - screwdriver adjust multi-turn pot

7.3.2

Indicators

Power ON - Green LED Tx Indicator - Yellow LED Fault Indicator - Flashing Red LED

7.3.3

Test Points

There are no front panel test points. All important test points are monitored by the firmware.

7.4 Electr ical Specifications

7.4.1 Power Requirements
Operating Voltage - 16 to 32 Vdc Current Drain 0.33A Maximum, typically 0.32A Standby Polarity - Negative Ground

28

7.4.2

Frequency Range and Channel Spacing

25 kHz T50 20kHz 15kHz 12.5 kHz T50 T50 T50 10 kHz T50 7.5 kHz T50 6.25 kHz T50

The T50, as a single model, covers the full band, and all channel spacing. Frequency 25 - 50 MHz

7.4.3 7.4.4

Frequency Synthesizer Step Size Frequency Stability

The specified frequency can be any multiple of 1250Hz. 5 ppm over 0 to +60 C, standard 12 ppm over -30 to +60 C.

7.4.5 7.4.6

Number of Channels Output power

256, numbered 00 - 255

The T50 needs an external PA50 power amplifier. The output power is factory set to 100W by default, the reverse power level is set to fold back the output power when the PA50 sees a load with VSWR of 3:1 or higher (i.e. when the reverse power is 25% or more of the forward power).

7.4.7
100%

Transmit Duty Cycle Spurious and Harmonics

7.4.8

Less than 0.25W, when connected to a PA50 operating at an output power level of 100W.

7.4.9

Carrier and Modulation Attack Time

Less than 36ms (Rev 3 and Rev 4). Less than 20ms (Rev 5 or higher).

7.4.10

Modulation

Type - Two point direct FM with optional pre-emphasis Frequency Response - 1 dB of the selected characteristic from 300-3000Hz Maximum Deviation - Maximum deviation set on a per channel basis to 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, or 5.0 kHz.

7.4.11 7.4.12

Distortion Residual Modulation and Noise

Modulation distortion is less than 3% at 1 kHz and 60% of rated system deviation.

The residual modulation and noise in the range 300 - 3000 Hz is typically less than 50dB with 5kHz maximum deviation (i.e. a test level of 3kHz).

7.4.13

600 Line Input Sensitivity

Adjustable from -32 to +12 dBm for rated deviation on two symmetric, independent, transformer coupled Line inputs. 29

7.4.14 7.4.15

Test Microphone Input External Tone Input

200 dynamic, with PTT

Compatible with all RF Technology receivers. Each unit is factory configured to give 20% of maximum deviation for an external tone input of 129mV.

7.4.16

T/R Relay Driver

An open drain MOSFET output is provided to operate an antenna change over relay or solid state switch. The transistor can sink up to 250mA. A 1W flywheel diode connects to the 12V rail to prevent damage to the FET from inductive kick from a relay coil.

7.4.17

Channel Select Input/Output

Coding - 8 lines, BCD coded 00 99; illegal BCD codes used to encode channels 100 255. If the MSN (Most Significant Nibble) is greater than 9, then the channel number is defined by the formula: 16*MSN + LSN; where the LSN is the Least Significant Nibble. If the MSN is less than 9, but the LSN is greater than 9, then the channel number is defined by the formula: 10*LSN+MSN; Logic Input Levels - High for <1.5V, Low for >3.5V Internal pull up resistors select channel 00 when all inputs are O/C.

7.4.18

DC Remote Keying

An opto-coupler input is provided to enable dc loop keying over balanced lines or local connections. The circuit can be connected to operate through the 600 line.

7.4.19

PTT in

An external input that when grounded with at least 1mA of current, will cause the exciter to key up. The current is drawn from the PTT in input which attempts to pull up anything that grounds it. It can be grounded with a short to 0V, or any resistance up to 3.9k ohm. If the resistance of the ground connection is less than 2.2k ohms, then up to three diodes in series can be part of the grounding path. This allows systems installers to use quite complex diode logic to enable or disable exciters. It would normally be grounded by the COS output of a receiver.

7.4.20

Programmable No-Tone Period

A No-Tone period can be appended to the end of each transmission to aid in eliminating squelch tail noise which may be heard in mobiles with slow turn off decoders. The NoTone period can be set from 0-99.9 seconds in 0.1 second increments.

7.4.21

Firmware Timers

The controller firmware includes some programmable timer functions. Repeater Hang Time(Transmit Tail) - A short delay or ``Hang Time'' can be programmed to be added to the end of transmissions. This is usually used in talk through repeater applications to prevent the repeater from dropping out between mobile 30

transmissions. The Hang Time can be individually set on each channel for 0 - 999 seconds. Time Out Timer - A time-out or transmission time limit can be programmed to automatically turn the transmitter off. The time limit can be set from 0-10million seconds. The timer is automatically reset when the PTT input is released. Zero seconds disables the timer, and allows continuous transmission.

7.4.22

CTCSS

CTCSS tones can be provided by an internal encoder or by an external source connected to the external tone input. The internal CTCSS encoding provides programmable encoding of any tone, accurate to 0.1Hz, including all EIA tones, from 67.0Hz to 257Hz.

7.4.23

DCS codes

DCS codes can be generated. The 9 bit DCS codes can be specified as a 3 digit octal number and individual codes can be assigned to each channel. The exciter computes the 23 bit golay code for each DCS code, which is then continuously transmitted as NRZ data at a bit rate of 134.4 bits per second when the exciter has keyed up. This feature is only available from Rev. 4 units or later revisions.

7.4.24

CWID

CWID messages are transmitted as Morse Code streams. The transmit rate is a nominal 20 words per minute. Each dot is a burst of 1028Hz tone at a deviation level of 1.5kHz for 60ms. Each dash is the same tone, at the same level for 180ms.

7.5 Connector s
7.5.1 7.5.2 7.5.3 RF Output Connector Power & I/O Connector External Reference Connector (optional)
BNC connector on the module rear panel.

25-pin D Female Mounted at the top of the rear panel

BNC connector mounted in the middle of the rear panel connector.

31

Engineering Diagrams

There is only one printed circuit board covering all models of the T50. There is only one option for this product, which is the external reference clock option. That option adds a rear connector, and a small length of coaxial cable and a fixed coaxial cable mount to the parts list. Unlike other products in the Eclipse range, CTCSS is no longer an option. All units have the ability to transmit CTCSS tones, and from Rev. 4, DCS codes.

A.1 A.2

Block Diagr am Cir cuit Diagr ams

Figure 1 shows the block signal flow diagram.

Figure 2 shows the detailed circuit diagram with component numbers and values for the main (exciter) PCB. Figure 3 shows the detailed circuit diagram with component numbers and values for the higher-power PA variation. Figure 4 shows the detailed circuit diagram with component numbers and values for the lower-power PA variation.

A.3

Component Over lay Diagr ams

Figure 5 shows the PCB overlay guide with component positions for the main (exciter) PCB. Figure 6 shows the detailed circuit diagram with component numbers and values for the higher-power PA variation. Figure 7 shows the detailed circuit diagram with component numbers and values for the lower power PA variation.

32

B T50 Parts List (Rev 4)

Ref
C100 C101 C102 C103 C201 C202 C203 C204 C205 C206 C207 C208 C209 C210 C211 C214 C215 C216 C217 C219 C220 C221 C222 C224 C225 C226 C227 C300 C301 C302 C304 C305 C306 C307 C308 C309 C310 C311 C312 C400 C401 C402 C403 C404 C405 C406 C407 C408 C409 C410 C411 C412 C413 C414 C415 C416 C417 C418 C419 C420 C421

Descr iption
Four EMI filters in a 1206 package, 100pF Four EMI filters in a 1206 package, 100pF Four EMI filters in a 1206 package, 100pF Four EMI filters in a 1206 package, 100pF 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 10nF Cer. Cap, X7R, 0603, 10% 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 3u3F SMD, Electrolytic cap, A body, 10% 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 22uF Electrolytic Capacitor, 35V, Bipolar 22uF Electrolytic Capacitor, 35V, Bipolar 2n2F Cer. Cap, NPO, 1206, 5% 3u3F SMD, Electrolytic cap, A body, 10% 10nF Cer. Cap, NPO, 1206, 5% 120pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 1uF, X7R, 1206 15uF SMD, low ESR Electrolytic cap, C body 10nF Cer. Cap, X7R, 0603, 10% 3n3F Cer. Cap, NPO, 1206, 5% 3n3F Cer. Cap, NPO, 1206, 5% 3n3F Cer. Cap, NPO, 1206, 5% 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 1nF, 25V, X7R, 0603

Par t #
34/NFA3/1100 34/NFA3/1100 34/NFA3/1100 34/NFA3/1100 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63X1/010N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 42/STA1/03U3 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 41/BP01/022U 41/BP01/022U 46/26N1/02N2 42/STA1/03U3 46/26N1/010N 46/63N1/120P 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 45/X7R1/1U16 41/SELC/015U 46/63X1/010N 46/26N1/03N3 46/26N1/03N3 46/26N1/03N3 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63X1/001N

33

C422 C423 C425 C426 C427 C428 C500 C501 C502 C503 C506 C507 C508 C509 C510 C511 C512 C513 C514 C515 C516 C600 C601 C602 C603 C604 C605 C606 C607 C608 C609 C610 C611 C612 C613 C614 C615 C616 C617 C619 C620 C621 C622 C623 C624 C625 C626 C627 C628 C629 C630 C631 C634 C635 C636 C637 C638 C639 C640 C641 C642 C643 C644 C645 C646 C649 C650

100nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 1uF, X7R, 1206 Ceramic Capacitor, 16V, 1uF, X7R, 1206 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 1uF, X7R, 1206 22pF Cer. Cap, NPO, 0603, 5% 22pF Cer. Cap, NPO, 0603, 5% Ceramic Capacitor, 16V, 1uF, X7R 100nF, 25V, Y5V, decoupler, 0603 100pF Cer. Cap, NPO, 0603, 5% 100pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 1uF, X7R, 1206 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 15uF SMD, low ESR Electrolytic cap, C body 15uF SMD, low ESR Electrolytic cap, C body Ceramic Capacitor, 16V, 22nF, X7R,10% 100nF, 50V, NPO, TH, 5mm 1n2F Cer. Cap, NPO, 1206, 5% 10nF Cer. Cap, X7R, 0603, 10% 100nF, 25V, Y5V, decoupler, 0603 10nF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% Ceramic Capacitor, 16V, 1uF, X7R, 1206 10nF Cer. Cap, X7R, 0603, 10% 100nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 1uF, X7R, 1206 Ceramic Capacitor, 16V, 1uF, X7R, 1206 10nF Cer. Cap, X7R, 0603, 10% 470pF Cer. Cap, NPO, 0603, 5% 1nF Cer. Cap, X7R, 0603, 10% 470nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 220nF, X7R, 10% 15pF Cer. Cap, NPO, 0603, 5% 3p3F Cer. Cap, NPO, 0603, 5% 10nF Cer. Cap, X7R, 0603, 10% 100nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 1uF, X7R, 1206 33pF Cer. Cap, NPO, 0603, 5% Ceramic Capacitor, 16V, 1uF, X7R, 1206 470nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 220nF, X7R, 10% Ceramic Capacitor, 16V, 1uF, X7R, 1206 3u3F SMD, Electrolytic cap, A body, 10% 3u3F SMD, Electrolytic cap, A body, 10% 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 1uF, X7R, 1206 Ceramic Capacitor, 16V, 1uF, X7R, 1206 10nF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% 8p2F Cer. Cap, NPO, 0603, 5% 10nF Cer. Cap, X7R, 0603, 10% 56pF Cer. Cap, NPO, 0603, 5% 10nF Cer. Cap, X7R, 0603, 10% 100nF, 25V, Y5V, decoupler, 0603 8p2F Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 100pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 1uF, X7R, 1206 Ceramic Capacitor, 16V, 1uF, X7R, 1206 10pF Cer. Cap, NPO, 0603, 5% 10pF Cer. Cap, NPO, 0603, 5%

46/63Y1/100N 45/X7R1/1U16 45/X7R1/1U16 46/63Y1/100N 46/63Y1/100N 45/X7R1/1U16 46/63N1/022P 46/63N1/022P 45/X7R1/1U16 46/63Y1/100N 46/63N1/100P 46/63N1/100P 46/63Y1/100N 45/X7R1/1U16 46/63Y1/100N 46/63Y1/100N 41/SELC/015U 41/SELC/015U 45/X7R1/022N 47/2007/100N 46/26N1/01N2 46/63X1/010N 46/63Y1/100N 46/63X1/010N 46/63X1/010N 45/X7R1/1U16 46/63X1/010N 46/63Y1/100N 45/X7R1/1U16 45/X7R1/1U16 46/63X1/010N 46/63N1/470P 46/63X1/001N 46/63Y1/470N 45/X7R1/220N 46/63N1/015P 46/63N1/03P3 46/63X1/010N 46/63Y1/100N 45/X7R1/1U16 46/63N1/033P 45/X7R1/1U16 46/63Y1/470N 45/X7R1/220N 45/X7R1/1U16 42/STA1/03U3 42/STA1/03U3 46/63Y1/100N 46/63Y1/100N 45/X7R1/1U16 45/X7R1/1U16 46/63X1/010N 46/63X1/010N 46/63N1/08P2 46/63X1/010N 46/63N1/056P 46/63X1/010N 46/63Y1/100N 46/63N1/08P2 46/63Y1/100N 46/63N1/100P 46/63Y1/100N 46/63Y1/100N 45/X7R1/1U16 45/X7R1/1U16 46/63N1/010P 46/63N1/010P

34

C651 C652 C700 C701 C702 C703 C704 C705 C706 C707 C708 C709 C710 C711 C712 C713 C714 C715 C716 C718 C719 C720 C721 C722 C723 C724 C725 C726 C727 C728 C729 C730 C731 C732 C733 C734 C735 C736 C737 C738 C739 C740 C742 C743 C744 C745 C746 C747 C748 C749 C750 C751 C752 C753 C754 C755 C756 C757 C758 C759 C760 C761 C762 C763 C764 C765 C766

100nF, 25V, Y5V, decoupler, 0603 10nF Cer. Cap, X7R, 0603, 10% 100nF, 25V, Y5V, decoupler, 0603 10nF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% 100nF, 25V, Y5V, decoupler, 0603 220pF Cer. Cap, NPO, 0603, 5% 220pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 220pF Cer. Cap, NPO, 0603, 5% 220pF Cer. Cap, NPO, 0603, 5% 220pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 10nF Cer. Cap, X7R, 0603, 10% 3u3F SMD, Electrolytic cap, A body, 10% 100nF, 25V, Y5V, decoupler, 0603 10nF Cer. Cap, X7R, 0603, 10% 100nF, 25V, Y5V, decoupler, 0603 220pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 1uF, X7R, 1206 10nF Cer. Cap, X7R, 0603, 10% 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 3u3F SMD, Electrolytic cap, A body, 10% 10nF Cer. Cap, X7R, 0603, 10% 100nF, 25V, Y5V, decoupler, 0603 12pF Cer. Cap, NPO, 0603, 5% 12pF Cer. Cap, NPO, 0603, 5% 12pF Cer. Cap, NPO, 0603, 5% 15pF Cer. Cap, NPO, 0603, 5% 10nF Cer. Cap, X7R, 0603, 10% 15pF Cer. Cap, NPO, 0603, 5% 5p6F Cer. Cap, NPO, 0603, 5% 3p3F Cer. Cap, NPO, 0603, 5% 12pF Cer. Cap, NPO, 0603, 5% 12pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 10nF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% 4p7F Cer. Cap, NPO, 0603, 5% 10nF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% 12pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 10nF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% 15pF Cer. Cap, NPO, 0603, 5% 33pF Cer. Cap, NPO, 0603, 5% 12pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 22pF Cer. Cap, NPO, 0603, 5% 12pF Cer. Cap, NPO, 0603, 5% 47pF Cer. Cap, NPO, 0603, 5% 47pF Cer. Cap, NPO, 0603, 5% 22pF Cer. Cap, NPO, 0603, 5% 15uF SMD, low ESR Electrolytic cap, C body 22pF Cer. Cap, NPO, 0603, 5% 10nF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% 6p8F Cer. Cap, NPO, 0603, 5% 68pF Cer. Cap, NPO, 0603, 5% 10pF Cer. Cap, NPO, 0603, 5%

46/63Y1/100N 46/63X1/010N 46/63Y1/100N 46/63X1/010N 46/63X1/010N 46/63Y1/100N 46/63N1/220P 46/63N1/220P 46/63Y1/100N 46/63N1/220P 46/63N1/220P 46/63N1/220P 46/63Y1/100N 46/63X1/010N 42/STA1/03U3 46/63Y1/100N 46/63X1/010N 46/63Y1/100N 46/63N1/220P 46/63Y1/100N 45/X7R1/1U16 46/63X1/010N 46/63Y1/100N 46/63Y1/100N 42/STA1/03U3 46/63X1/010N 46/63Y1/100N 46/63N1/012P 46/63N1/012P 46/63N1/012P 46/63N1/015P 46/63X1/010N 46/63N1/015P 46/63N1/05P6 46/63N1/03P3 46/63N1/012P 46/63N1/012P 46/63Y1/100N 46/63X1/010N 46/63X1/010N 46/63X1/010N 46/63N1/04P7 46/63X1/010N 46/63X1/010N 46/63N1/012P 46/63Y1/100N 46/63X1/010N 46/63X1/010N 46/63X1/010N 46/63X1/010N 46/63N1/015P 46/63N1/033P 46/63N1/012P 46/63Y1/100N 46/63Y1/100N 46/63N1/022P 46/63N1/012P 46/63N1/047P 46/63N1/047P 46/63N1/022P 41/SELC/015U 46/63N1/022P 46/63X1/010N 46/63X1/010N 46/63N1/06P8 46/63N1/068P 46/63N1/010P

35

C767 C768 C769 C770 C771 C772 C773 C775 C776 C801 C802 C803 C804 C805 C806 C807 C810 C811 C820 C821 C822 C823 C824 C825 C826 C827 C828 C829 C830 C901 C902 C903 C904 C915 C920 C923 C924 C925 C926 C927 C928 C929 C930 C931 C932 C933 C934 C935 C936 C937 C938 C939 C940 C941 C942 C943 C944 C945 D102 D103 D104 D200 D202 D203 D300 D301 D302

12pF Cer. Cap, NPO, 0603, 5% 15pF Cer. Cap, NPO, 0603, 5% 68pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 Ceramic Capacitor, 16V, 1uF, Y5V 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF Cer. Cap, X7R, 1206, 10% 1n2F Cer. Cap, X7R, 0603, 10% 1nF Cer. Cap, NPO, 0603, 5% 68pF Cer. Cap, NPO, 0603, 5% 470pF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% 10nF Cer. Cap, X7R, 0603, 10% 100nF Cer. Cap, X7R, 1206, 10% 100uF Electrolytic Capacitor, 35V 470pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 10nF Cer. Cap, X7R, 0603, 10% 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 220pF Cer. Cap, NPO, 0603, 5% 3u3F SMD, Electrolytic cap, A body, 10% 10 uF Electrolytic capacitor 150pF Cer. Cap, NPO, 0603, 5% 100nF, 25V, Y5V, decoupler, 0603 68pF Cer. Cap, NPO, 0603, 5% 100uF SMD, low ESR Electrolytic cap, D body 470uF Electrolytic Capacitor, Low ESR, 35V 33uF SMD, low ESR Electrolytic cap, C body 3u3F SMD, Electrolytic cap, A body, 10% 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 100nF, 25V, Y5V, decoupler, 0603 470uF Electrolytic Capacitor, Low ESR, 35V 33uF SMD, low ESR Electrolytic cap, C body 100uF SMD, low ESR Electrolytic cap, D body 100uF SMD, low ESR Electrolytic cap, D body 100uF SMD, low ESR Electrolytic cap, D body 33uF SMD, low ESR Electrolytic cap, C body 33uF SMD, low ESR Electrolytic cap, C body 33uF SMD, low ESR Electrolytic cap, C body 33uF SMD, low ESR Electrolytic cap, C body 33uF SMD, low ESR Electrolytic cap, C body 33uF SMD, low ESR Electrolytic cap, C body Radially mounted LED Radially mounted LED Radially mounted LED Dual Series Diode Gen. Purpose 1N4004 diode in SMD pkg Zener Diode Bi-directional Transil Bidirectional Transil Bidirectional Transil

46/63N1/012P 46/63N1/015P 46/63N1/068P 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 45/Y5X7/1U16 46/63Y1/100N 46/63Y1/100N 46/3310/100N 46/63X1/01N2 46/63N1/01N0 46/63N1/068P 46/63X1/470P 46/63X1/010N 46/63X1/010N 46/3310/100N 41/2001/100U 46/63N1/470P 46/63Y1/100N 46/63X1/010N 46/63Y1/100N 46/63Y1/100N 46/63N1/220P 42/STA1/03U3 41/2001/010U 46/63N1/150P 46/63Y1/100N 46/63N1/068P 41/SELD/100U 41/200L/470U 41/SELC/033U 42/STA1/03U3 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 46/63Y1/100N 41/200L/470U 41/SELC/033U 41/SELD/100U 41/SELD/100U 41/SELD/100U 41/SELC/033U 41/SELC/033U 41/SELC/033U 41/SELC/033U 41/SELC/033U 41/SELC/033U 21/1010/LEDR 21/1010/LEDY 21/1010/LEDG 21/3010/AV99 24/SMA1/4004 21/1040/C3V3 24/TRSL/012V 24/TRSL/012V 24/TRSL/012V

36

D303 D304 D305 D306 D307 D400 D401 D402 D403 D500 D501 D502 D503 D600 D601 D700 D701 D703 D704 D800 D906 D907 D908 D909 D910 D911 F300 F301 F302 J1 JP12 JP2 JP3 JP4 L100 L101 L102 L104 L200 L202 L203 L204 L205 L500 L600 L700 L701 L702 L703 L704 L705 L706 L708 L709 L710 L711 L712 L713 L714 L715 L716 L717 L719 L720 L721 L722 L723

Dual Series Diode Dual Series Diode Dual Series Diode Gen. Purpose 1N4004 diode in SMD pkg Dual Schottky, Comm. Cathode, Diode Dual Series Diode Dual Series Diode Dual Series Diode Dual Series Diode Dual Series Diode Dual Series Diode Dual Series Diode Dual Series Diode Varactor Varactor Schottky diode Varactor Schottky diode Varactor Dual Schottky, Comm. Cathode, Diode Power Fast Schottky diode Power Fast Schottky diode Power Fast Schottky diode Power Fast Schottky diode Gen. Purpose 1N4004 diode in SMD pkg 4.096V Reference Diode SMD (1206 pkg), 125mA fuse SMD (1206 pkg), 125mA fuse SMD (1206 pkg), 125mA fuse BNC Connector 4 Pin SIL Header 14 Pin SIL Header 10 pin DIL Header 10 pin DIL Header Ferrite, 1206 pkg, 120 ohm, 3A Ferrite, 1206 pkg, 600 ohm, 200mA Ferrite, 1206 pkg, 600 ohm, 200mA Ferrite, 1206 pkg, 600 ohm, 200mA 220uH Choke Ferrite, 1206 pkg, 600 ohm, 200mA Ferrite, 1206 pkg, 600 ohm, 200mA Ferrite, 1206 pkg, 600 ohm, 200mA Ferrite, 1206 pkg, 600 ohm, 200mA Ferrite, 1206 pkg, 600 ohm, 200mA Ferrite, 1206 pkg, 600 ohm, 200mA 27nH Inductor 33nH Inductor 27nH Inductor 27nH Inductor 47nH Inductor 27nH Inductor 330nH Inductor 330nH Inductor 330nH Inductor 330nH Inductor 330nH Inductor 220nH Inductor 1206 47R resistor 330nH Inductor 330nH Inductor Inductor - Air Core, 12.5nH 100nH Inductor Inductor - Air Core, 18.5nH 24nH Inductor 24nH Inductor 24nH Inductor 330nH Inductor

21/3010/AV99 21/3010/AV99 21/3010/AV99 24/SMA1/4004 24/3BAT/54C1 21/3010/AV99 21/3010/AV99 21/3010/AV99 21/3010/AV99 21/3010/AV99 21/3010/AV99 21/3010/AV99 21/3010/AV99 21/3060/V109 21/3060/V109 21/3030/0017 21/3060/V109 21/3030/0017 21/3060/V109 24/3BAT/54C1 24/BRM1/40T3 24/BRM1/40T3 24/BRM1/40T3 24/BRM1/40T3 24/SMA1/4004 29/VREF/0001 39/1206/A125 39/1206/A125 39/1206/A125 35/5BNC/RA01 35/2501/0004 35/2501/0014 35/7026/0010 35/7026/0010 37/P034/0001 37/P033/0001 37/P033/0001 37/P033/0001 37/3320/P103 37/P033/0001 37/P033/0001 37/P033/0001 37/P033/0001 37/P033/0001 37/P033/0001 37/8551/027N 37/8551/033N 37/8551/027N 37/8551/027N 37/8551/047N 37/8551/027N 37/3320/330N 37/3320/330N 37/3320/330N 37/3320/330N 37/3320/330N 37/8551/220N 51/3380/047R 37/3320/330N 37/3320/330N 37/AC51/12N5 37/8551/100N 37/AC51/18N5 37/6351/024N 37/6351/024N 37/6351/024N 37/3320/330N

37

L724 L725 L726 L800 L801 L803 L804 L807 L808 L809 L810 L811 L812 L813 L901 L902 L903 L904 L905 L906 L907 L908 L909 LC700 LC701 LC702 M1 M1C M2 MX700 P1 P3 Q200 Q201 Q202 Q203 Q204 Q205 Q206 Q300 Q301 Q302 Q400 Q401 Q500 Q501 Q600 Q700 Q701 Q702 Q703 Q704 Q705 Q706 Q707 Q801 Q804 Q805 R100 R101 R102 R103 R104 R105 R201 R202 R203

330nH Inductor 3u3H Choke 33nH Inductor Ferrite, 1206 pkg, 600 ohm, 200mA Ferrite, 1206 pkg, 600 ohm, 200mA Inductor - Air Core, 538nH Inductor - Air Core, 538nH 220uH Choke 3u3H Choke 180nH Inductor 1uH Choke 3u3H Choke 150nH Inductor 150nH Inductor Ferrite, 1206 pkg, 600 ohm, 200mA SMD High Current, Shielded, 330uH Choke SMD High Current, Shielded, 470uH Choke SMD High Current, Shielded, 330uH Choke Ferrite, 1206 pkg, 600 ohm, 200mA Ferrite, 1206 pkg, 120 ohm, 3A Ferrite, 1206 pkg, 120 ohm, 3A Ferrite, 1206 pkg, 120 ohm, 3A Ferrite, 1206 pkg, 120 ohm, 3A 70MHz SMD Filter, 0805 pkg 70MHz SMD Filter, 0805 pkg 70MHz SMD Filter, 0805 pkg Tinned BeCu, used as RF screen. RF Screen Cover (Small) Conductive Foam Inserts +7dBm0 Mixer, Surface Mount DB9 Female with filtered pins DB25 Female with filtered pins Gen. Purpose NPN transistor in SOT-23 N channel, Enhancement Mode MOSFET N Channel Junction FET(low Freq) NPN Switching transistor in SOT-23 NPN Switching transistor in SOT-23 Gen. Purpose PNP transistor in SOT-23 Gen. Purpose NPN transistor in SOT-23 N channel, Enhancement Mode MOSFET Gen. Purpose PNP transistor in SOT-23 Gen. Purpose PNP transistor in SOT-23 Gen. Purpose PNP transistor in SOT-23 Gen. Purpose PNP transistor in SOT-23 Gen. Purpose PNP transistor in SOT-23 Gen. Purpose PNP transistor in SOT-23 Gen. Purpose NPN transistor in SOT-23 Gen. Purpose PNP transistor in SOT-23 N channel, Enhancement Mode MOSFET Gen. Purpose NPN transistor in SOT-23 N channel, Enhancement Mode MOSFET N Channel Junction FET(UHF) N Channel Junction FET(UHF) N channel, Enhancement Mode MOSFET Gen. Purpose NPN transistor in SOT-23 SOD-89A RF Transistor(1W) SOD-89A RF Transistor(1W) SOD-89A RF Transistor(1W) 0805, 1%, 4K7 resistor 0805, 1%, 4K7 resistor 0805, 1%, 4K7 resistor 1206 180R resistor 1206 270R resistor 0805, 1%, 4K7 resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor

37/3320/330N 37/3320/P101 37/8551/082N 37/P033/0001 37/P033/0001 37/AC52/558N 37/AC52/558N 37/3320/P103 37/3320/P101 37/8551/180N 37/3320/P200 37/3320/P101 37/3320/150N 37/3320/150N 37/P033/0001 37/MSP1/330U 37/MSP1/470U 37/MSP1/330U 37/P033/0001 37/P034/0001 37/P034/0001 37/P034/0001 37/P034/0001 37/85LC/0135 37/85LC/0135 37/85LC/0135 94/BECU/24XH 80/9209/0001 83/0001/0000 37/MIXR/P028 35/5012/009F 35/5012/025F 27/3020/3904 27/30B5/5138 27/3020/5484 27/3020/2369 27/3020/2369 27/3010/3906 27/3020/3904 27/30B5/5138 27/3010/3906 27/3010/3906 27/3010/3906 27/3010/3906 27/3010/3906 27/3010/3906 27/3020/3904 27/3010/3906 27/30B5/5138 27/3020/3904 27/30B5/5138 27/3030/J309 27/3030/J309 27/30B5/5138 27/3020/3904 27/300B/FQ17 27/300B/FQ17 27/300B/FQ17 51/8511/04K7 51/8511/04K7 51/8511/04K7 51/3380/0180 51/3380/0270 51/8511/04K7 51/8511/010K 51/8511/010K 51/8511/010K

38

R204 R205 R206 R207 R208 R209 R210 R211 R212 R213 R214 R215 R216 R217 R218 R219 R220 R221 R222 R223 R224 R225 R226 R227 R228 R229 R230 R231 R232 R233 R234 R235 R236 R237 R238 R239 R240 R241 R242 R243 R244 R245 R300 R301 R302 R303 R304 R305 R306 R307 R308 R309 R310 R311 R312 R313 R314 R315 R316 R317 R318 R319 R320 R321 R322 R323 R324

0805, 1%, 10K resistor 0805, 1%, 2K2 resistor 0805, 1%, 2K2 resistor 0805, 1%, 68K resistor 0805, 1%, 22K resistor 0805, 1%, 330R resistor 0805, 1%, 10K resistor 0805, 1%, 220R resistor 0805, 1%, 220R resistor 0805, 1%, 1M resistor 1206 180R resistor 0805, 1%, 120R resistor 0805, 1%, 1K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 560R resistor 0805, 1%, 1K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 1206 180R resistor 0805, 1%, 56R resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 120R resistor 0805, 1%, 120R resistor 0805, 1%, 560R resistor 0805, 1%, 22K resistor 0805, 1%, 1K resistor 0805, 1%, 4K7 resistor 0805, 1%, 22K resistor 0805, 1%, 47K resistor 0805, 1%, 1K resistor 0805, 1%, 1K resistor 0805, 1%, 10K resistor 0805, 1%, 47R resistor 0805, 1%, 47K resistor 0805, 1%, 220R resistor 0805, 1%, 10R resistor 0805, 1%, 10K resistor 0805, 1%, 27R resistor 0805, 1%, 27R resistor 0805, 1%, 27R resistor 0805, 1%, 27R resistor 0805, 1%, 330R resistor 0805, 1%, 330R resistor 0805, 1%, 10R resistor 0805, 1%, 4K7 resistor 0805, 1%, 2K2 resistor 0805, 1%, 560R resistor 0805, 1%, 560R resistor 0805, 1%, 22K resistor 0805, 1%, 22K resistor 0805, 1%, 22K resistor 0805, 1%, 1K resistor 0805, 1%, 22K resistor 0805, 1%, 1K resistor 0805, 1%, 1K resistor 0805, 1%, 120K resistor 0805, 1%, 120K resistor 0805, 1%, 120K resistor 0805, 1%, 68K resistor 0805, 1%, 68K resistor 0805, 1%, 68K resistor 0805, 1%, 1K resistor

51/8511/010K 51/8511/02K2 51/8511/02K2 51/8511/068K 51/8511/022K 51/8511/330R 51/8511/010K 51/8511/220R 51/8511/220R 51/8511/01M0 51/3380/0180 51/8511/120R 51/8511/01K0 51/8511/010K 51/8511/010K 51/8511/010K 51/8511/010K 51/8511/560R 51/8511/01K0 51/8511/010K 51/8511/010K 51/8511/010K 51/3380/0180 51/8511/056R 51/8511/010K 51/8511/010K 51/8511/120R 51/8511/120R 51/8511/560R 51/8511/022K 51/8511/01K0 51/8511/04K7 51/8511/022K 51/8511/047K 51/8511/01K0 51/8511/01K0 51/8511/010K 51/8511/047R 51/8511/047K 51/8511/220R 51/8511/010R 51/8511/010K 51/8511/027R 51/8511/027R 51/8511/027R 51/8511/027R 51/8511/330R 51/8511/330R 51/8511/010R 51/8511/04K7 51/8511/02K2 51/8511/560R 51/8511/560R 51/8511/022K 51/8511/022K 51/8511/022K 51/8511/010K 51/8511/022K 51/8511/010K 51/8511/01K0 51/8511/120K 51/8511/120K 51/8511/120K 51/8511/068K 51/8511/068K 51/8511/068K 51/8511/01K0

39

R325 R326 R327 R328 R329 R330 R331 R332 R333 R335 R336 R337 R400 R401 R402 R403 R404 R405 R406 R407 R408 R409 R410 R411 R412 R413 R414 R415 R416 R417 R418 R419 R420 R421 R422 R423 R424 R425 R426 R427 R428 R429 R430 R433 R434 R435 R436 R437 R438 R439 R440 R442 R443 R444 R445 R446 R447 R448 R449 R450 R451 R453 R454 R455 R456 R457 R458

0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 68K resistor 0805, 1%, 1K resistor 0805, 1%, 22K resistor 0805, 1%, 22K resistor 0805, 1%, 1K8 resistor 0805, 1%, 330R resistor 0805, 1%, 270R resistor 0805, 1%, 22K resistor 0805, 1%, 22K resistor 0805, 1%, 12K resistor 0805, 1%, 5K6 resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 5K6 resistor 0805, 1%, 56K resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 10K resistor 0805, 1%, 1K resistor 0805, 1%, 560R resistor 0805, 1%, 560R resistor 0805, 1%, 560R resistor 0805, 1%, 560R resistor 0805, 1%, 2K2 resistor 0805, 1%, 22K resistor 0805, 1%, 120K resistor 0805, 1%, 22K resistor 0805, 1%, 120K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 22K resistor 0805, 1%, 22K resistor 0805, 1%, 47K resistor 0805, 1%, 22K resistor 0805, 1%, 22K resistor 0805, 1%, 47K resistor 0805, 1%, 270K resistor 0805, 1%, 4K7 resistor 0805, 1%, 1K resistor 0805, 1%, 4K7 resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 4K7 resistor 0805, 1%, 4K7 resistor 0805, 1%, 4K7 resistor 0805, 1%, 4K7 resistor 0805, 1%, 4K7 resistor 0805, 1%, 47K resistor 0805, 1%, 100K resistor 0805, 1%, 47K resistor 0805, 1%, 270K resistor 0805, 1%, 220R resistor 0805, 1%, 56K resistor 0805, 1%, 47K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 47K resistor 0805, 1%, 22K resistor 0805, 1%, 4K7 resistor

51/8511/047K 51/8511/047K 51/8511/047K 51/8511/010K 51/8511/010K 51/8511/047K 51/8511/047K 51/8511/068K 51/8511/01K0 51/8511/022K 51/8511/022K 51/8511/01K8 51/8511/330R 51/8511/270R 51/8511/022K 51/8511/022K 51/8511/012K 51/8511/05K6 51/8511/010K 51/8511/010K 51/8511/05K6 51/8511/056K 51/8511/047K 51/8511/047K 51/8511/010K 51/8511/01K0 51/8511/560R 51/8511/560R 51/8511/560R 51/8511/560R 51/8511/02K2 51/8511/022K 51/8511/120K 51/8511/022K 51/8511/120K 51/8511/010K 51/8511/010K 51/8511/022K 51/8511/022K 51/8511/047K 51/8511/022K 51/8511/022K 51/8511/047K 51/8511/270K 51/8511/04K7 51/8511/01K0 51/8511/04K7 51/8511/047K 51/8511/047K 51/8511/04K7 51/8511/04K7 51/8511/04K7 51/8511/04K7 51/8511/04K7 51/8511/047K 51/8511/100K 51/8511/047K 51/8511/270K 51/8511/220R 51/8511/56K 51/8511/047K 51/8511/010K 51/8511/010K 51/8511/010K 51/8511/047K 51/8511/022K 51/8511/04K7

40

R459 R460 R461 R462 R463 R464 R465 R466 R467 R500 R501 R502 R503 R504 R505 R506 R507 R508 R509 R510 R511 R512 R513 R514 R515 R516 R517 R518 R519 R520 R521 R522 R523 R525 R526 R527 R528 R529 R530 R531 R532 R533 R534 R535 R536 R537 R602 R603 R604 R605 R606 R607 R608 R609 R610 R611 R612 R613 R614 R615 R616 R617 R618 R620 R622 R623 R624

0805, 1%, 4K7 resistor 0805, 1%, 4K7 resistor 0805, 1%, 56K resistor 0805, 1%, 22K resistor 0805, 1%, 56K resistor 0805, 1%, 270K resistor 0805, 1%, 22K resistor 0805, 1%, 2K2 resistor 0805, 1%, 4K7 resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 22K resistor 0805, 1%,1K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 1M resistor 0805, 0.5%, 50ppm,15K resistor 0805, 0.5%, 50ppm,15K resistor 0805, 0.5%, 50ppm,15K resistor 0805, 0.5%, 50ppm,15K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 15K resistor 0805, 1%, 330K resistor 0805, 1%, 680R resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 270K resistor 0805, 1%, 1K resistor 0805, 1%, 10K resistor 0805, 1%, 2K2 resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 0.5%, 50ppm,15K resistor 0805, 0.5%, 50ppm,15K resistor 0805, 0.5%, 50ppm,15K resistor 0805, 0.5%, 50ppm,15K resistor 0805, 1%, 5K6 resistor 0805, 1%, 100K resistor 0805, 1%, 10K resistor 0805, 1%, 100K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 15K resistor 0805, 1%, 5K6 resistor 0805, 1%, 5K6 resistor 0805, 1%, 2K2 resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%, 47R resistor 0805, 1%, 47R resistor 0805, 1%, 47R resistor 0805, 1%, 47R resistor 0805, 1%, 1K resistor 0805, 1%, 1K resistor 0805, 1%, 1K2 resistor 0805, 1%, 5K6 resistor 0805, 1%, 5K6 resistor 0805, 1%, 22K resistor

51/8511/04K7 51/8511/04K7 51/8511/056K 51/8511/022K 51/8511/056K 51/8511/270K 51/8511/022K 51/8511/02K2 51/8511/04K7 51/8511/047K 51/8511/047K 51/8511/047K 51/8511/022K 51/8511/01K0 51/8511/010K 51/8511/010K 51/8511/01M0 51/85P1/015K 51/85P1/015K 51/85P1/015K 51/85P1/015K 51/8511/010K 51/8511/010K 51/8511/015K 51/8511/330K 51/8511/680R 51/8511/047K 51/8511/047K 51/8511/047K 51/8511/047K 51/8511/047K 51/8511/270K 51/8511/01K0 51/8511/010K 51/8511/02K2 51/8511/047K 51/8511/047K 51/8511/047K 51/85P1/015K 51/85P1/015K 51/85P1/015K 51/85P1/015K 51/8511/05K6 51/8511/100K 51/8511/10K 51/8511/100K 51/8511/010K 51/8511/010K 51/8511/010K 51/8511/015K 51/8511/05K6 51/8511/05K6 51/8511/02K2 51/8511/010K 51/8511/010K 51/8511/010K 51/8511/010K 51/8511/047R 51/8511/047R 51/8511/047R 51/8511/047R 51/8511/01K0 51/8511/01K0 51/8511/1K2 51/8511/05K6 51/8511/05K6 51/8511/022K

41

R625 R626 R627 R628 R629 R630 R631 R632 R633 R634 R635 R636 R637 R638 R639 R640 R646 R647 R648 R649 R650 R700 R701 R702 R703 R704 R705 R706 R707 R708 R709 R710 R711 R712 R713 R714 R715 R716 R717 R718 R719 R720 R721 R722 R723 R724 R725 R726 R727 R729 R730 R731 R732 R733 R734 R735 R736 R737 R738 R739 R740 R741 R742 R743 R745 R801 R802

0805, 1%, 22K resistor 0805, 1%, 2K2 resistor 1218, 5%, 150R, 1W, SMD resistor 1218, 5%, 150R, 1W, SMD resistor 0805, 1%, 270K resistor 1206, 1%, 120R resistor 0805, 1%, 47R resistor 0805, 1%, 47R resistor 1218, 5%, 150R, 1W, SMD resistor 1206, 1%, 120R resistor 0805, 1%, 560R resistor 0805, 1%, 220R resistor 0805, 1%, 5K6 resistor 0805, 1%, 5K6 resistor 0805, 1%, 10K resistor 1218, 5%, 150R, 1W, SMD resistor 0805, 1%, 4K7 resistor 0805, 1%, 10K resistor 0805, 1%, 4K7 resistor 0805, 1%, 10K resistor 0805, 1%, 5K6 resistor 0805, 1%, 120R resistor 0805, 1%, 100R resistor 0805, 1%, 100R resistor 0805, 1%, 100R resistor 0805, 1%, 100R resistor 0805, 1%, 100R resistor 0805, 1%, 220R resistor 0805, 1%, 100R resistor 0805, 1%, 4K7 resistor 0805, 1%, 10K resistor 0805, 1%, 2K2 resistor 0805, 1%, 10R resistor 0805, 1%, 56R resistor 0805, 1%, 10K resistor 0805, 1%, 56R resistor 0805, 1%, 10K resistor 0805, 1%, 47R resistor 0805, 1%, 10K resistor 0805, 1%, 100R resistor 0805, 1%, 10K resistor 0805, 1%, 100K resistor 0805, 1%, 330R resistor 0805, 1%, 22K resistor 0805, 1%, 10K resistor 0805, 1%, 56R resistor 0805, 1%, 5K6 resistor 0805, 1%, 47R resistor 0805, 1%, 22K resistor 0805, 1%, 10R resistor 0805, 1%, 100R resistor 0805, 1%, 560R resistor 0805, 1%, 22K resistor 0805, 1%, 1K resistor 0805, 1%, 4K7 resistor 0805, 1%, 22K resistor 0805, 1%, 56R resistor 0805, 1%, 330R resistor 0805, 1%, 100R resistor 0805, 1%, 10K resistor 0805, 1%, 100R resistor 0805, 1%, 1K resistor 0805, 1%, 220R resistor 0805, 1%, 560R resistor 0805, 1%, 330R resistor 0805, 1%, 12K resistor 0805, 1%, 100R resistor

51/8511/022K 51/8511/02K2 51/2851/0150 51/2851/0150 51/8511/270K 51/3380/120R 51/8511/047R 51/8511/047R 51/2851/0150 51/3380/120R 51/8511/560R 51/8511/220R 51/8511/05K6 51/8511/05K6 51/8511/010K 51/2851/0150 51/8511/04K7 51/8511/010K 51/8511/04K7 51/8511/010K 51/8511/05K6 51/8511/120R 51/8511/047R 51/8511/120R 51/8511/120R 51/8511/120R 51/8511/220R 51/8511/220R 51/8511/220R 51/8511/04K7 51/8511/010K 51/8511/02K2 51/8511/010R 51/8511/056R 51/8511/010K 51/8511/056R 51/8511/010K 51/8511/047R 51/8511/010K 51/8511/120R 51/8511/010K 51/8511/100K 51/8511/330R 51/8511/022K 51/8511/010K 51/8511/056R 51/8511/05K6 51/8511/047R 51/8511/022K 51/8511/010R 51/8511/100R 51/8511/560R 51/8511/022K 51/8511/01K0 51/8511/04K7 51/8511/022K 51/8511/056R 51/8511/330R 51/8511/100R 51/8511/010K 51/8511/100R 51/8511/01K0 51/8511/220R 51/8511/560R 51/8511/330R 51/8511/012K 51/8511/100R

42

R803 R804 R805 R806 R808 R809 R810 R811 R812 R813 R814 R815 R816 R819 R823 R918 R919 R920 R921 R922 R923 R924 R925 R926 R927 R928 R929 R930 R931 R932 R933 R934 R935 R936 RL300 RV100 S200 SW1 T300 T301 U201 U202 U203 U204 U205 U207 U208 U212 U300 U301 U302 U303 U400 U401 U402 U403 U404 U405 U406 U407 U500 U502 U503 U600 U601 U602 U603

1218, 5%, 150R, 1W, SMD resistor 1206 10R resistor 1206 10R resistor 1218, 5%, 150R, 1W, SMD resistor 0805, 1%, 10R resistor 0805, 1%, 27R resistor 0805, 1%, 10R resistor 0805, 1%, 27R resistor 0805, 1%, 100R resistor 1218, 5%, 150R, 1W, SMD resistor 0805, 1%, 10R resistor 0805, 1%, 1K resistor 0805, 1%, 10K resistor 7W Axial 68R resistor 0805, 1%, 4K7 resistor 0805, 1%, 47K resistor 0805, 1%, 47K resistor 0805, 1%, 1K resistor 0805, 1%, 560R resistor 0805, 1%, 220R resistor 0805, 1%, 1K resistor 0805, 1%, 680R resistor 0805, 1%, 220R resistor 0805, 1%, 2K2 resistor 0805, 1%, 220R resistor 0805, 1%, 220R resistor 0805, 1%, 220R resistor 0805, 1%, 220R resistor 0805, 1%, 220R resistor 0805, 1%, 220R resistor 0805, 1%, 560R resistor 0805, 1%, 560R resistor 0805, 1%, 120R resistor 0805, 1%, 120R resistor 12V Telecommunications DPDT Relay 100K, 11 turn, linear Pot. 4mm SMD PB switch Omron-6x6-RA switch High Isolation Audio Transformer High Isolation Audio Transformer Quad CMOS RS232 Driver SMD (SO-14) Quad CMOS RS232 Driver SMD (SO-14) Under-voltage sensor and Reset Generator Motorola Embedded 8/16 bit microcontroller One of 8 Selector 4 Megabyte TSOP (Std.) 5V (only) Flash 1,2,4 Megabit RAM in SOP package Hi Speed, TTL compatible, opto-isolator Opto-isolator with Darlington Output Quad SPST Analog Switch - low Rds On Low Power Quad Operational Amplifier 32 position digital pot. Low Power Quad Operational Amplifier 8-bit Shift reg. with output latch Transconductance Amplifier Quad SPST Analog Switch - low Rds On Quad SPST Analog Switch - low Rds On Low Power Quad Operational Amplifier Voltage Output, Quad 8 bit DAC Low Power Quad Operational Amplifier CTCSS and DCS encoder/decoder Low Power Quad Operational Amplifier 32 position digital pot. Gen. Purp. R2R Op. Amp. Voltage Output, Quad 8 bit DAC Dual PLL Temperature Sensor

51/2851/0150 51/3380/0010 51/3380/0010 51/2851/0150 51/8511/010R 51/8511/027R 51/8511/010R 51/8511/027R 51/8511/100R 51/2851/0150 51/8511/010R 51/8511/01K0 51/8511/010K 55/5W51/068R 51/8511/04K7 51/8511/047K 51/8511/047K 51/8511/01K0 51/8511/560R 51/8511/220R 51/8511/01K0 51/8511/680R 51/8511/220R 51/8511/02K2 51/8511/220R 51/8511/220R 51/8511/220R 51/8511/220R 51/8511/220R 51/8511/220R 51/8511/560R 51/8511/560R 51/8511/120R 51/8511/120R 96/2000/012V 53/THH1/100K 31/SMPB/0001 31/0005/E121 37/2040/5065 37/2040/5065 29/14C8/9A01 29/14C8/8001 29/MC33/064D 29/68HC/12A0 29/2030/C138 29/P006/0001 29/SRAM/P013 26/N137/0001 25/1010/4N33 29/00DG/411C 29/000L/M224 29/MAX5/161L 29/000L/M224 29/2030/C595 29/0LM1/3700 29/00DG/411C 29/00DG/411C 29/000L/M224 29/00MA/X534 29/000L/M224 29/00FX/805L 29/000L/M224 29/MAX5/161L 29/1M55/P021 29/00MA/X534 29/LMX2/335L 29/0001/LM61

43

U604 Dual PLL U605 Dual, Ripple Carry, 4 bit binary counter U606 Dual 4 bit, ripple carry, decade counters U607 Gen. Purp. R2R Op. Amp. U608 Gen. Purp. R2R Op. Amp. U700 MMIC Amplifier U701 MMIC Amplifier U702 MMIC Amplifier U703 MMIC Amplifier U704 Transconductance Amplifier U705 MMIC Amplifier U706 MMIC Amplifier U707 Gen. Purp. R2R Op. Amp. U800 MMIC Amplifier U906 Gen. Purp. R2R Op. Amp. U907 Simple (Buck) Switcher, 5V, 1A output U908 Simple (Buck) Switcher, 5V, 1A output U909 Simple (Buck) Switcher, 5V, 1A output U910 LDO Adjustable Positive Voltage Regulator U911 Positive Adjustable Voltage Reg. in SO8 package U912 Positive Adjustable Voltage Reg. in SO8 package U913 Negative Adjustable Voltage Reg. in SO8 U914 Negative Adjustable Voltage Reg. in SO8 U915 Negative Adjustable Voltage Reg. in SO8 X200 14.7456 MHz Crystal, 30ppm, SMD X500 4.0 MHz Crystal X600 12.0 MHz Crystal, 5ppm, SMD X601 12.0 MHz Crystal, 5ppm, SMD

29/LMX2/335L 29/2030/C393 29/2030/C390 29/1M55/P021 29/1M55/P021 24/3010/VAM6 24/3010/211L 24/3010/211L 24/3010/211L 29/0LM1/3700 24/3010/211L 24/3010/211L 29/1M55/P021 24/3010/211L 29/1M55/P021 29/REG1/0N12 29/REG1/0N12 29/REG2/00N5 29/00LM/1117 29/000L/M317 29/000L/M317 29/000L/M337 29/000L/M337 29/000L/M337 33/14M7/0001 32/2049/04M0 33/12M0/0001 33/12M0/0001

44

C T50 Parts List (Rev 3)

The following table highlights those components in Rev. 3 exciters, that differ from the parts in Rev. 4. The values indicated are the values used in Rev.3

Ref

Descr iption

Par t #

C212 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100N C420 NF C421 NF C502 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100N C512 NF C513 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16 C611 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N C612 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100N C622 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100N C645 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100N C646 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100N C719 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100N C726 3p9F Cer. Cap, NPO, 0603, 5% 46/63N1/03P9 C727 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015P C728 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015P C729 1p8F Cer. Cap, NPO, 0603, 5% 46/63N1/01P8 C731 NF C734 3p9F Cer. Cap, NPO, 0603, 5% 46/63N1/03P9 C735 2p2F Cer. Cap, NPO, 0603, 5% 46/63N1/02P2 C744 NF C752 NF C755 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047P C756 4p7F Cer. Cap, NPO, 0603, 5% 46/63N1/04P7 C757 120pF Cer. Cap, NPO, 0603, 5% 46/63N1/120P C758 120pF Cer. Cap, NPO, 0603, 5% 46/63N1/120P C759 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047P C760 NF C765 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047P C766 NF C767 NF C768 NF C769 NF C804 18pF Cer. Cap, NPO, 0603, 5% 46/63N1/018P C808 1p8F Cer. Cap, NPO, 0603, 5% 46/63N1/01P8 C809 NF C812 1p8F Cer. Cap, NPO, 0603, 5% 46/63N1/01P8 C813 100pF Cer. Cap, NPO, 0603, 5% 46/63N1/100P C815 56pF Cer. Cap, NPO, 0603, 5% 46/63N1/056P C816 33pF Cer. Cap, NPO, 0603, 5% 46/63N1/033P C818 10pF Cer. Cap, NPO, 0603, 5% 46/63N1/010P C819 68pF Cer. Cap, NPO, 0603, 5% 46/63N1/01P8 C828 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047P C830 NF D503 NF J4 NF JP4 NF L701 39nH Inductor 37/8551/039N L703 NF L704 NF L705 NF L713 220uH Choke 37/3320/P103 L720 220nH Inductor 37/3320/220N L721 270nH Inductor 37/3320/270N L722 220nH Inductor 37/3320/220N L726 82nH Inductor 37/8551/082N L805 120nH, air core 37/AC52/120N L806 169nH, air core 37/MAXI/169N L812 270nH Inductor 37/3320/270N L813 NF LC700 NF

45

LC701 LC702 Q402 R313 R314 R315 R316 R332 R333 R337 R404 R446 R448 R451 R452 R464 R514 R515 R522 R534 R535 R536 R537 R600 R602 R603 R604 R605 R609 R610 R612 R617 R619 R620 R621 R626 R627 R628 R633 R634 R640 R701 R702 R703 R705 R711 R712 R713 R714 R721 R725 R733 R736 R737 R738 R740 R741 R742 R745 R801 R803 R806 R807 R813 R814 R815

NF NF Gen. Purpose PNP transistor in SOT-23 0805, 1%, 120K resistor 0805, 1%, 22K resistor 0805, 1%, 100K resistor 0805, 1%, 22K resistor 0805, 1%, 180K resistor 0805, 1%, 1K resistor NF 0805, 1%, 10K resistor 0805, 1%, 10K resistor 0805, 1%,10K resistor 0805, 1%, 47K resistor 0805, 1%,10K resistor 0805, 1%, 330K resistor 0805, 1%, 22K resistor NF 0805, 1%, 68K resistor NF NF NF NF 0805, 1%, 4K7 resistor 0805, 1%, 27K resistor 0805, 1%, 27K resistor 0805, 1%, 100K resistor 0805, 1%, 18K resistor 0805, 1%, 22K resistor 0805, 1%, 47K resistor 0805, 1%, 100K resistor 0805, 1%, 560R resistor 0805, 1%, 680R resistor 0805, 1%, 680R resistor 0805, 1%, 4K7 resistor 0805, 1%, 4K7 resistor NF 1218, 5%, 68R, 1W, SMD resistor 1206, 1%, 120R resistor 1206, 1%, 120R resistor NF 0805, 1%, 47R resistor 0805, 1%, 120R resistor 0805, 1%, 120R resistor 0805, 1%, 220R resistor 0805, 1%, 56R resistor NF 0805, 1%, 100K resistor 0805, 1%, 120R resistor NF 0805, 1%, 22K resistor 0805, 1%, 330R resistor 0805, 1%, 220R resistor 0805, 1%, 1K resistor 0805, 1%, 220R resistor 0805, 1%, 120R resistor 0805, 1%, 4K7 resistor 0805, 1%, 180R resistor 0805, 1%, 220R resistor 0805, 1%, 22K resistor 1218, 5%, 100R, 1W, SMD resistor 1218, 5%, 100R, 1W, SMD resistor 1218, 5%, 100R, 1W, SMD resistor 1218, 5%, 100R, 1W, SMD resistor NF NF

27/3010/3906 51/8511/120K 51/8511/022K 51/8511/100K 51/8511/022K 51/8511/180K 51/8511/01K0 51/8511/010K 51/8511/010K 51/8511/010K 51/8511/047K 51/8511/010K 51/8511/330K 51/8511/022K 51/8511/068K

51/8511/04K7 51/8511/027K 51/8511/027K 51/8511/100K 51/8511/018K 51/8511/022K 51/8511/047K 51/8511/100K 51/8511/560R 51/8511/680R 51/8511/680R 51/8511/04K7 51/8511/04K7 51/2851/0068 51/3380/120R 51/8511/120R 51/8511/047R 51/8511/120R 51/8511/120R 51/8511/220R 51/8511/056R 51/8511/100K 51/8511/120R 51/8511/022K 51/8511/330R 51/8511/220R 51/8511/01K0 51/8511/220R 51/8511/120R 51/8511/04K7 51/8511/180R 51/8511/220R 51/8511/022K 51/2851/0100 51/2851/0100 51/2851/0100 51/2851/0100

46

D EIA CTCSS TONES

Fr equency No Tone EIA Number

67.0 71.9 74.4 77.0 79.7 82.5 85.4 88.5 91.5 94.8 100.0 103.5 107.2 110.9 114.8 118.8 123.0 127.3 131.8 136.5 141.3 146.2 151.4 156.7 162.2 167.9 173.8 179.9 186.2 192.8 203.5 210.7 218.1 225.7 233.6 241.8 250.3

A1 B1 C1 A2 C2 B2 C3 A3 C4 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 A11 B11 A12 B12 A13 B13 A14 B14 A15 B15 A16 B16 A17

47

uP

uP

CTCSS Generator

Summing Amplifier

uP Buffer

Tone+ Digital Potentiometer uP uP Buffer Limiter

Low Pass Filter (250Hz)

Tone-

Pre-emphasis

Balanced Differential Line 2 Amplifier Deviation uP Control

PLL: Phase Locked Loop VCA: Voltage Controlled Amplifier

Summing Amplifier

Line2+ uP

T300 Maximum Tone Deviation Setting and Dir. Aud. (Tone IN) Deviation Control Buffer uP uP Summing Amplifier Digital Potentiometer uP Amplifier 6dB gain Maximum Deviation Line Level Sense Setting uP Low Pass Filter (3kHz)

uP

VCA

VCO: Voltage Controlled Oscillator uP: Microprocessor Input or Output

Line2-

Flat

uP

Pre-emphasis

Line 1 Deviation Control uP Limiter Amplifier 20dB gain Peak Detector

Vref Line Level In uP Line Potentiometer

Line2+

T301

VCA

uP

Line2Modulation Balance VCA uP uP Centre Frequency Adjustment Reference Oscillator

Flat uP

Pre-emphasis

Loop/Volts Select

Microphone input

uP uP Set Synthesiser Dividers Modulation PLL RF Amplifier VCO

+12V

uP Lock Detect and Reference Osc. Detect Varactor Bias uP uP Low Pass Filter (350MHz) RF Amplifier RF Amplifier Varactor Bias uP Passive Mixer Low Pass Filter (55MHz) uP

Loop Detect

uP

RF Output

External Ref. Div. VCO RF Amplifier Channel PLL

External Reference Input

3200

uP

RF Amplifier Low Pass Filter (300MHz)

RF Amplifier

Voltage Controlled Low Pass RF Filter (55MHz) Amplifier

High Speed Coupler uP

GPS+

GPS-

GPS uP

Set Synthesiser Dividers

uP Lock Detect and Reference Osc. Detect Centre Frequency uP Adjustment Reference Oscillator Temp. Sensor Temp. uP

Title Block Flow Diagram of Audio and RF signals in 9154(T50)

Size:

A4

Number: 05/9 Print Date: 8-Apr-2003 Rev. Release Date: File: 10:28:51 Sheet 1 Originator: of 1

Revision: A

RF Technology Pty Ltd

Unit 10, 8 Leighton Place Hornsby, NSW 2077 Australia
D:\Protel Files\Copies from Crocodile\t50_4.ddb - Issue4\BLOCK_DIAGRAM.Sch

5V_PROT

D10 R20 PA_CS 180R

BAV99

GND 5V_PROT FD1 FIDUCIAL R21 SCLK FIDUCIAL 180R FD2

D11

BAV99

GND 5V_PROT

D12 R22 MOSI 180R BAV99 +5V GND R19 22R 5V_PROT D13 R1 74HC165 100K 100K 100K 100K 100K 100K BZX84C5V6 R2 C1 100nF R3 R4 100K R5 R6 R7 R8 R9 R10 100K R11 47K 47K 47K R13 R15 R17 R18 47K R12 R14 R16 47K 47K 47K 47K

J1

+28V

LK1

JUMPER

16

VCC

47K

47K

LK2 1 LK3

JUMPER

GND R23 R24 180R 180R

JUMPER LK4 10 JUMPER

PTT_IN T/R_RELAY LINE2+ LINE2TONE+ TONELINEGPS+ GPSLINE+ 15 2 9 7 1 C C Q Q PL

GND

CH_EN

Q1 BSS138 U1

I7 I6 I5 I4 I3 I2 I1 I0 SI

6 5 4 3 14 13 12 11 10

CH80 CH40 CH20 CH10 CH8 CH4 CH2 CH1

2 3 4 5 6 7 8 9

+5V Vref R25 180R D9 BAW56

5X2 Header
GND B

+12V

D1

D2

D3

D4

D5

D6

D7

13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1

DB25

BAV99

BAV99

BAV99

BAV99

BAV99

BAV99

BAV99

5V_PROT

D14 R26 CS2 180R BAV99

GND A Rev No. ECO No. Description of Change

Title Rear Panel Board for 9154 (T50) and 9155 (R50)
Size:

BAV99

D8

A3

Number: 05/9160 R7 Print Date: 16-Aug-2002 Rev. Release Date: File: 09:56:54 Sheet 1 Originator:
F:\Obsoleted Files\Old Files Backup\916x.ddb - T50_R50_rear_panel.Sch

Revision: 1 of 1

RF Technology Pty Ltd

Unit 10, 8 Leighton Place Hornsby, NSW 2077 Australia 4 5 6 7 8

FILTER_OFF

FILTER_OFF

C509

+5TONE

L500 U500 C508 BLM31A601 100nF +5V R512 10K

+5V

18

1uF C501 1 22pF C500 22pF CTCSS_SEL SCLK MOSI SCLK MOSI C502 100nF 14 13 15 20 19 21 C503 100nF 10 CTCSS_SEL 7 3 5 6 8 16 17 R507 1M XTAL

Vbias

VCC

24

GND

GND

X500 4MHz 2

XTAL/CLK CS ADDR SCLK Din Dout

IRQ

TONE_INT

C513 TONE_OUT 9 CTCSS_OUT 1uF

R514 10K TP500 TONE+CTCSS R503 22K DG411 C R519 47K C515 100nF (NPO) C516 1n2F (NPO) GND

RX_SUB_IN RX_SUB_OUT RX_IN+ RX_INRX_OUT NO_TONE COMP+ COMPCOMP_OUT AUDIO_IN AUDIO_OUT 11

1
U301A 2 3 R518 47K

22

2 3

U502A 1 LM224 R527 47K

R517 47K

10 9

U502C 8 LM224

WAKE

GND

R516 680R

C514 22nF (X7R - 10%) GND

23

12

FX805 -10V

GND +10V

GND +10V R528 47K C510 100nF GND -10V +2.5V R523 1K R522 68K U502D 12 14 13 LM224 R525 R526 2K2 D502

D500 R530 TONEP7K5 R500 47K C506 100pF C507 100pF R531 TONEP+ 7K5 7K5 +10V R533 7K5 R511 7K5 7K5 R508 BAV99

R530, R531, R508, R509, R532, R533, R510, AND R511 Should be 0.25%, 50ppm TC or better R510 7K5 R532 7K5 TP501 TONE_IN U502B 7 5 LM224 R502 47K DG411 15 U301D 14 R504 560R U502E LM224

TONE_OUT D503 BAV99

TONE_OUT

V+

V-

U503

VDD

11

2 R524 NF 1 R534 NF

10K

R529 47K

BAV99 GND GND B

GND R501 47K

-10V R509

100nF GND

MMBT3906 R505 Q500 10K R520 47K

GND

D501 BAV99

-10V

C511

+2.5V

5 4

INC U/D

-10V GND MAX5161L

16

+5V R513 10K

-2.5V

-10V

GND EXT_TONE_SEL

-2.5V +2.5V

TONE_DEV_INC R506 TONE_DEV_U/D 10K MMBT3906 R521 47K Q501

-2.5V A Rev No. ECO No. Description of Change A

Title Tone Generation Section

Size:

A3

Number:

9154
23:41:52 Sheet 5 Originator: of 9

Revision:

RF Technology Pty Ltd

Unit 10, 8 Leighton Place Hornsby, NSW 2077 Australia

Print Date: 20-Feb-2002 Rev. Release Date: File: 1 2 3 4 5 6

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - tonetx.sch

3 +5Q

4 +5Q

R631 47R C630 1uF C631 10nF GND C621 GND

+5Q R616 47R 4 3 +5Q C604 C609 10nF GND R618 1K PDOUT_MOD C612 100nF 12 5 8 C634 +5Q U602 LMX2335L 10nF R615 47R GND C649 10pF GND +5Q C608 1uF C616 10nF 4 3 TS971LT R619 +5Q 3u3F R617 1K L713 TS971LT C613 * 220nF GND 3 14 C625 + ** C618 +5V NF R621 4K7 R648 4K7 MOD_PLL_SENSE C645 100nF GND R649 10K MOD_PLL_SENSE 1uF

MOD_IN

MOD_IN

5
U600 1 R622 5K6 C628 R625 22K D MOD_BIAS MOD_BIAS

R605 27K

R609 10K +5Q +5Q

R613 47R C602 10nF

R608 D C601 100nF GND Vref 2K2

16

1 3 TS971LT

R602 27K C610 470pF GND

R603 27K C611

15

U607

220uH

1uF

-5V

100nF GND

VCC1

VCC2

Vp2

R611

GND 6 X600 12M 7 11 9 10

Xin

2K2 R637 5K6

-5V

MMBV109 D600

10nF

C614 C615 C643 R607 5K6 100nF R604 100K C624 1uF -5V MOD_PLL_SEL +5Q R614 47R R612 -5V C 100K C629 1uF D601 C638 GND CHAN_PLL_SEL R629 270K R606 5K6 +5Q Vref C617 100nF GND RESET B SIGGEN_ADSEL SCLK MOSI RESET 5 7 6 9 10 11 U601 CHAN_PLL_SEL SCLK MOSI MOD_ADJ_FINE R610 47K 10nF MMBV109 C636 10nF C640 8p2F R632 47R C603 10nF GND 6 X601 12M 7 11 9 10 C619 1uF C607 1uF C600 C605 15pF 15pF 10nF 33pF C620 SCLK MOSI

Xout LE CLK DATA

Vp1
DO1 DO2 Fin2 Fin1

GND Fo_MOD

GND

GND 13

FoLD

MOD_PLL_SEL

GND

GND

5
U608 1 R623 5K6 C627 R624 22K C CHAN_BIAS CHAN_BIAS

16

15

10nF

GND

VCC1

VCC2

Vp2

Vp1

C635 8p2F GND

C637 56pF

Xin

DO1 DO2

3 14 12 5 8 C652 C650 10pF

PDOUT_CHAN

680R C622 100nF R620 680R C647 GND 10nF +5V C626 + 3u3F R600 4K7 GND R646 4K7 C646 100nF R647 10K NF **

-5V

100nF GND

Xout LE CLK DATA

Fin2 Fin1

GND

GND

FoLD

C639 R650 100nF 5K6 GND VCO Section vco.sch C648 MOD_IN 2PORT_MOD 100nF OUTA OUTB OUTC OUTD 2 1 16 15 8 4 CHAN_ADJ BALANCE BALANCE

13

MOD_ADJ

U604 LMX2335L

GND

GND

Fo_CHAN

CHAN_PLL_SENSE

CHAN_PLL_SENSE

13

CHAN_VCO_OUT MOD_VCO_OUT

VCC

Vref

PDE CLR LDAC CS SCLK Din

GND L718 220uH * C613 AND C623 CAN BE X7R(10%) ** C625 and C626 should be 10% Tantalums Case Size A

CHAN_PLL_IN C623 MOD_VCO_EN 220nF GND *

+5Q

DGND

AGND

SIGGEN_ADSEL SCLK MOSI

Dout UPO

MOD_VCO_EN CHAN_VCO_EN

U603

1
LM61

U400A 2 1 Vt 3 LM224 C651 100nF R638 5K6 R639 10K TEMP TEMP

V+

Placed near X601 2

MAX534

12

14

T/R_RELAY +5V MOD_PLL_IN L600 BLM31A601

Vo

GND CHAN_VCO_EN T/R_RELAY

GND

14

16

C606 100nF

C644 100nF

VCO_OUT

GND

VCO_OUT

74HC393

Divide by 128
R635 560R C642 100pF Q600 R633 120R R628 68R R630 120R R634 120R MMBT3904 13 12 QA 1A QB R QC QD 74HC393 U605B 1 2 11 10 9 8 GND R636 220R 1 2 U605A QA 1A QB R QC QD 74HC393 3 4 5 6

GND

74HC390
U606C

GndVcc

GndVcc

GND

U605C

C641 A EXT_REF_IN 100nF

GND Fo_MOD_2 U606A Fo_MOD 1 4 2 1A QA 1B QB QC R QD 74HC390 GND 3 3 5 6 7 U606B Fo_CHAN 15 12 14 1A QA 1B QB QC R QD 74HC390 GND 5 6 13 11 10 9 Fo_CHAN_2 Fo_CHAN_2 Size: EXT_REF_DIV Fo_MOD_2 Rev No. ECO No. Description of Change

Title Frequency Synthesiser

A3
Number:

9154
23:40:44 Sheet 6 Originator: of 9

Revision:

RF Technology Pty Ltd

Unit 10, 8 Leighton Place Hornsby, NSW 2077 Australia

GND

Print Date: 20-Feb-2002 Rev. Release Date: File:

Divide by 25
4

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - siggen.sch

TP908 +5Q 12V D L909 28V BLM31P121SG C902 + 470uF 2 5 Vin EN FB 4 L902 1 DS5022P-224 + C938 D907 MBRM140T3 100uF U907 LM2595S-12 Max output current is 1A 12V TP909 12V L901 33uH + C903 33uF C923 100nF 3 1 U910 LM1117DTX-ADJ 4 Vin Vo 2 Vo ADJ R925 220R TP910 +10V +10V 1 C926 + C940 100nF 33uF GND 5 NC U911 LM317LM Vin Vout Vout Vout Vout NC 2 3 7 6 8 R927 220R +5Q 1 C942 + 33uF C931 5 100nF NC U912 LM317LM Vin Vout Vout Vout Vout NC 2 3 7 6 8 R929 220R +10V +10V +5Q TP916 +2.5V +2.5V +2.5V C944 + 33uF D

GND GND

Vout

ADJ

GND GND R920 1K C924 C930 100nF 100nF R921 560R 12V GND D906 C MBRM140T3 2 C915 C935 + Low Impedance Type 35V, 10mm dia 470uF R918 47K 5 R919 47K U908 LM2595S-12 -10V Vin EN FB 4 L903 1 DS5022P-334 + C937 D908 MBRM140T3 100uF L905 220uH D910 GND SM4004 -12V 2 3 7 6 5 U913 LM337LM -Vin -Vin -Vin -Vin NC -Vout 1 C941 U914 LM337LM 2 3 7 6 5 -Vin -Vin -Vin -Vin NC -Vout 1 C943 R928 220R C933 100nF 2 3 7 6 5 U915 LM337LM -Vin -Vin -Vin -Vin NC -Vout 1 TP911 -10V -10V TP914 -5V -5V -5V GND R935 120R GND R933 560R C932 100nF R930 220R

GND

Tantalum, ESR <= 0.3 ohms

GND

ADJ

3 6

GND

GND GND

Vout

100nF

TP917 -10V -2.5V -2.5V -2.5V C945 R931 220R

3 6

Tantalum, ESR <= 0.3 ohms

ADJ

ADJ

100nF

R922 220R

33uF

100nF

33uF

GND R923 1K C925 100nF R924 560R

GND GND R934 560R C928 100nF R936 120R GND GND C934 100nF R932 220R

GND

B GND

TP913 Vref GND

U909 LM2595S-5 12V 2 5 + C936 33uF Vin EN FB 4

Output Current is 750mA (max) TP912 L904 1 DS5022P-224 + C939 D909 MBRM140T3 100uF L906 BLM31P121SG 100nF L907 BLM31P121SG L908 BLM31P121SG +5D3 +5D2 ZRC400F01 GND 3u3F +5D1 +5V +5V +5V +10V R926 2K2 D911 C929 4 1 3 TS971LT C904 +5Q TP915 U906 Vref Vref GND GND GND

GND GND

Vout

3 6

Tantalum, ESR <= 0.3 ohms

GND

Tantalum, ESR <= 0.3 ohms

A Rev No. ECO No. Description of Change

Title Power Generation Section

Size:

A3

Number:

9154
23:40:01 Sheet 9 Originator: of 9

Revision:

Print Date: 20-Feb-2002 Rev. Release Date: File: 1 2 3 4 5 6

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - power.sch

100uF

NC

C927

NC

ADJ

C901

C920

NC

8 33uF

RF Technology Pty Ltd

Unit 10, 8 Leighton Place Hornsby, NSW 2077 Australia

28V R813 C801 C827 + 100nF +10V C R802 47R GND R807 100R 10uF 35V 100R R806 100R L800 BLM31A601 L801 BLM31A601 Murata Ferrite SMD Choke C810 C811 + 100nF GND L804 558nH 100uF 35V R819 68R C802 1n2F Coilcraft Maxi Spring Coils 10nF GND C L803 558nH

C806

C823 100nF GND C824 L811 3u3H 100nF GND RF_in 1 MSA0311 3 U800 220pF C804 47pF C825 L809 180nH R811 27R Q801 BFQ17 C822 10nF R808 10R Q804 Q805 BFQ17 BFQ17 C805 C814 470pF NF C815 56pF 1n2F C808 1p8F C812 1p8F RF_out C816 33pF C813 100pF C817 NF C818 10pF C819 68pF C809 NF D800 BAT54C RF_out R812 220R L810 1uH L805 120nH L806 169nH

C807

GND

C820 470pF

R804 10R

R805 10R

GND

R803 100R R809 27R C826 + 100nF 3u3F C829 L808 3u3H R810 10R

C821 GND 100nF

GND

C803 1nF

R816 10K LOC_FWD_PWR

L807 PWRCNTRL 220uH

GND

R823 4K7

GND GND

A Rev No. ECO No. Description of Change

Title Broadband Power Amplifier

Size:

A3

Number:

9154
23:39:04 Sheet 8 Originator: of 9

Revision:

RF Technology Pty Ltd

Unit 10, 8 Leighton Place Hornsby, NSW 2077 Australia

Print Date: 20-Feb-2002 Rev. Release Date: File: 1 2 3 4 5 6

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - pa.sch

3 +5D2

4 +5D2 +5D3 +5D1

7 +5LCD R224 10K R225 10K R223 10K

R241 C222 L200 100nF C214 LINE_LEVEL_IN GND 100nF X200 14M7456 11 U403C 28V R207 68K R213 1M 100nF R237 47K GND CHAN_PLL_SENSE MOD_PLL_SENSE LINE_LEVEL_SENSE CHAN_BIAS MOD_BIAS LOC_FWD_PWR R238 1K 100nF 220uH C220 R236 22K R235 4K7 Q203 MMBT2369 C221 R239 1K MMBT2369 47R R240 10K R243 220R R242 47K

R244 10R

Vref C225 100nF C224 100nF C226 C205 100nF C204 100nF C206 100nF C207 100nF

85

GND

DG411 D TEMP TEMP 10

46 Q204 47 44

EXTAL

Vddpll VCC VCC VCC VCC VCC

Vref

Q202 MMBF5484

43 14 42 79 95 2

100nF

LCD_RS LCD_R/W LCD_E +5D3 +5D1 R219 10K +5D2 CS0 U209 C E I7 I6 I5 I4 I3 I2 I1 I0 C212 D

U204 PF6 PF3 PF2 PF1 74 71 70 69

GND MOD_PLL_SEL LCD_RS LCD_R/W LCD_E MOD_PLL_SEL

R220 10K

GND R202 12V 10K D202 SM4004 T/R_RELAY Q201 BSS138 R208 22K +5TONE T/R_RELAY_H R201 10K 100nF C203

XTAL XFC

20
100nF

R/W L205 +5D1 11 1 D7 D6 D5 D4 D3 D2 D1 D0 3 18 4 17 7 14 8 13

16

VIN_SENSE GND

BLM31A601 U205 C208 100nF 7 9 10 11 12 13 14 15 GND

VCC

CHAN_PLL_SENSE MOD_PLL_SENSE LINE_LEVEL_SENSE CHAN_BIAS LINE_LEVEL_IN MOD_BIAS LOC_FWD_PWR FRDY FPSW1 FPSW2 FPSW3 LOOP/VOLTS_SEL TONE_DEV_U/D TONE_DEV_INC EXT_TONE_SEL LINEINP_ADSEL LINEINP_DSEL TEMP_LEVEL_IN PWR_CNTRL_HIGH CTCSS_SEL CHAN_PLL_SEL SIGGEN_ADSEL CHAN_VCO_EN EXT_REF_DIV SPARE_SEL CH_EN GPS TERM_EN2 TERM_EN1 Fo_MOD_2 Fo_CHAN_2 LCD_DB7 ECLK TX_LED

94 93 92 91 90 89 88 87 27 26 25 24 23 22 21 20 84 83 82 81 78 77 76 75 112 111 110 109 108 107 106 105 51 48 39 104 103 102 101 100 99 98 97

AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 PE7 PE4 PE3 SS SCK MOSI MISO TxD1 RxD1 TxD0 RxD0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 XIRQ IRQ CSO CSD CSP0 R/W 68 72 73 38

GND 2 19 5 16 6 15 9 12 LCD_DB7 LCD_DB6 LCD_DB5 LCD_DB4 LCD_DB3 LCD_DB2 LCD_DB1 LCD_DB0 LCD_DB7 LCD_DB6 LCD_DB5 LCD_DB4 LCD_DB3 LCD_DB2 LCD_DB1 LCD_DB0

6 4 5 3 2 1 74HC138

EN1 EN2A EN2B S2 S1 S0

6N137

C227 100nF R216 1K

VCC

R214 GPS+ C 180R D203 BZX84C3V3

NC A K NC

Ve Vo

7 GND 6

GND

1 2 3 4 R215 120R

FPSW1 FPSW2 FPSW3 LOOP/VOLTS_SEL TONE_DEV_U/D TONE_DEV_INC EXT_TONE_SEL LINEINP_ADSEL LINEINP_DSEL PWR_CNTRL_HIGH CTCSS_SEL CHAN_PLL_SEL SIGGEN_ADSEL CHAN_VCO_EN EXT_REF_DIV SPARE_SEL CH_EN TERM_EN2 TERM_EN1 Fo_MOD_2 Fo_CHAN_2

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

GND

GND

RAMRD RAMWT

O7 O6 O5 O4 O3 O2 O1 O0

VCC

74HC374 +5D1 +5D1 -12V GND +5D1 R217 10K CSP0 9 37 38 12 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 39 40 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 21 22 23 24 CE OE WE RESET A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 FWT FRD CSD R218 10K +5D2 C210 U207 100nF GND C217 100nF C211 100nF 100nF C201 L202 BLM31A601 GND 12V L204 BLM31A601 C215 C

GND

L203 BLM31A601

U212

10

R227 GPS56R U202D RTS 11 14C88 DBGTX 8 10 1 14C89A 3 2 C 4 5 DBGRX B 14C89A RXDATA 10 8 9 C 13 12 DTR 3 14C88 2 U202A +5D3 +5V R245 Q205 10K MMBT3906 R229 10K 10K R228 Q206 MMBT3904 GND C202 100nF A 3u3F GND C219 + R205 2K2 3 5 6 7 8 NC NC NC NC NC R209 +5D3 R206 2K2 +5D1 R204 10K R203 10K C U201C U201D 11 14C89A C U201A U201B 6 14C89A SCLK MOSI PA_CS 14C88 U202C 13 6 5 9 14C88 U202B 4 GND 12

31

10 14 1

VCC

VCC

100nF GND

32

GND

VGnd
U202E

RESET A21 A19 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 18 17 16 13 12 11 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 35 34 33 32 31 30 29 28 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

U208 RY/BY CS OE WE A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

VCC

36 FRDY

22 24 29 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 30 2 31 3 28 4 25 23 26 27 5 6 7 8 9 10 11 12

14C88

TXDATA DSR

TX_LED

CTS

GND

GND

GND

T/R_RELAY_H SCLK R230 SCK 120R MOSI SD 120R PA_CS R231 DBGTX_TTL DBGRX_TTL TXD_TTL RXD_TTL RTS_TTL DTR_TTL DSR_TTL CTS_TTL PTT_uPHONE TONE_INT LOOP_DET FILTER_OFF

D7 D6 D5 D4 D3 D2 D1 D0

35 34 33 32 28 27 26 25

D7 D6 D5 D4 D3 D2 D1 D0

GND D7 D6 D5 D4 D3 D2 D1 D0 21 20 19 18 17 15 14 13 D7 D6 D5 D4 D3 D2 D1 D0 +5D3

V+

GND

14

C216 U201E 100nF GND B

Gnd
14C89A GND

R232 560R R212 PTT_IN 220R R211 220R D200 C209 10nF BAV99

R234 1K

10 9 8 7 PTT_uPHONE 6 TONE_INT 5 LOOP_DET 4 FILTER_OFF 3 36 37

NC

29F032

K6T4008

30

29

11

GND A[0..21] D[0..7]

GND

INT DEV_H_L R221 BKGD 560R ALARM_LED RESET BKGD_ISO DEV_H_L ALARM_LED RESET R233 22K

GNDref

GNDpll GND GND GND GND GND

19 50 49 40

BKGD MODB MODA RESET

86

45 15 41 80 96 1

+5D3 R222 1K

MC68HC812A0 R226 PWR_OK GND R210 10K 180R A Rev No. Q200 MMBT3904 ECO No. Description of Change

330R U203 GND RES 1 RESET

VCC

S200 7914G

GND

Title Microprocessor
Size:

MC33064D

GND

A3

Number:

9154
23:32:55 Sheet 2 Originator: of 9

16

Revision:

V+

RF Technology Pty Ltd

Unit 10, 8 Leighton Place Hornsby, NSW 2077 Australia

Print Date: 20-Feb-2002 Rev. Release Date: File:

GND 1 2 3 4 5 6

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - micro.sch

JP12 uPHONE_IN AUDIO PROCESSING SECTION audio.sch LCD_BIAS FILTER_OFF D TP102 28V 28V LINE_LEVEL_SENSE CTCSS_SEL SCLK MOSI TONE_INT C100 NFA31CC102 SCLK PA_CS PTT_IN uPHONE_IN EXT_TONE_SEL LOOP/VOLTS_SEL LINEINP_DSEL LINEINP_ADSEL TERM_EN2 TERM_EN1 L2+ L2L2+ L2TONE+ TONEL1+ TONE_DEV_U/D L1C103 L1PWRCNTRL TONE_DEV_INC LOOP_DET PWRCNTRL MOD_OUT PTT_IN Vref NFA31CC102 GND 12V DB25RA/F L101 +5V RF SIGNAL GENERATOR siggen.sch MOD_IN SCLK MOSI RESET POWER AMPLIFIER pa.sch BNC Right Angle - Low Profile J1 RF_in RF_out PWRCNTRL LOC_FWD_PWR GND VCO_out T/R_RELAY SIGGEN_ADSEL MOD_PLL_SEL MOD_BIAS MOD_PLL_SENSE CHAN_PLL_SEL CHAN_BIAS CHAN_PLL_SENSE Fo_MOD_2 Fo_CHAN_2 EXT_REF_DIV EXT_REF_IN BNC-2 GND CHAN_VCO_EN CHAN_VCO_EN RTS RXDATA CTS TXDATA DTR DSR 5 9 4 8 3 7 2 6 1 P1 SG RI DTR CTS TXD RTS RXD DSR DCD DB9 TEMP TEMP T/R_RELAY SIGGEN_ADSEL MOD_PLL_SEL MOD_BIAS MOD_PLL_SENSE CHAN_PLL_SEL CHAN_BIAS CHAN_PLL_SENSE Fo_MOD_2 Fo_CHAN_2 EXT_REF_DIV SIGGEN_ADSEL MOD_PLL_SEL MOD_BIAS MOD_PLL_SENSE CHAN_PLL_SEL CHAN_BIAS CHAN_PLL_SENSE Fo_MOD_2 Fo_CHAN_2 EXT_REF_DIV T/R_RELAY PA_CS GPS+ GPSCH_EN SPARE_SEL PTT_IN BKGD T/R_RELAY PA_CS GPS+ GPSCH_EN SPARE_SEL RESET BKGD TONE_DEV_U/D TONE_DEV_INC LOOP_DET LINE_LEVEL_IN +5D3 JP3 1 2 3 4 5 6 7 8 9 10 CON10 GND L104 LCD_BIAS LCD_RS LCD_R/W LCD_E LCD_DB0 LCD_DB1 LCD_DB2 LCD_DB3 LCD_DB4 LCD_DB5 LCD_DB6 LCD_DB7 BLM31A601 GND Debug/Monitor Port 4K7 R105 RV100 100K C FPSW3 GND RESET PWR_CNTRL_HIGH DEV_H_L RESET SCLK MOSI LCD_BIAS MICROPROCESSOR CONTROL SECTION micro.sch GND FILTER_OFF PTT_uPHONE LINE_LEVEL_SENSE CTCSS_SEL SCLK MOSI TONE_INT EXT_TONE_SEL LOOP/VOLTS_SEL LINEINP_DSEL LINEINP_ADSEL TERM_EN2 TERM_EN1 RESET PWR_CNTRL_HIGH FPSW2 DEV_H_L ALARM_LED D103 TX_LED D104 PWR_OK POWER OK FPSW1 T/R_RELAY HiZ+ HiZTONE+ TONELINE_I/P4 C101 NFA31CC102 AMBER Tx Data GREEN R100 4K7 R101 4K7 R102 4K7 R103 180R R104 270R ALARM D102 RED +5D3 D PTT_uPHONE 1 2 3 4 4 HEADER

P3 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1

L100 BLM31P121SG

SW1
3 2
+5LCD L102 BLM31A601 JP2 1 2 3 4 5 6 7 8 9 10 11 12 13 14

LINE_I/P1

C102 NFA31CC102 GPS+ GPS-

C&K_PB
Vref

L1+

MOSI CH_EN SPARE_SEL

BLM31A601

GND

3
DBGTX DBGRX

+5D1

DBGTX DBGRX

HEADER 14

J4 B

LOC_FWD_PWR

LOC_FWD_PWR

RTS RXDATA CTS TXDATA DTR DSR

POWER SECTION power.sch 12V +10V 28V +5V +5Q A 28V Vref +2.5V GND GND -2.5V

12V +10V +5V +5Q Vref +2.5V Rev No. ECO No.

GND NB: connector signals reversed so that straight through cable can be used to PC

A Description of Change

Title T50 Master Schematic

Size:

A3

Number:

9154
23:28:58 Sheet 1 Originator: of 9

Revision:

-5V -10V -10V 71 -5V

-2.5V

RF Technology Pty Ltd

Unit 10, 8 Leighton Place Hornsby, NSW 2077 Australia

Print Date: 20-Feb-2002 Rev. Release Date: File:

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - Master.sch

5 +2.5V R446 10k DG411 Q402 MMBT3906 TEST_DEV

DEV_H_L +10V C417 100nF R402 22K GND 3 2 4 R414 560R R415 560R A U402A 5 7 R420 120K R423 10K R406 10K Io = Is(2Iabc/Id) : Io= Vo/Rl ; Is = Vs/Rs; Iabc = Vabc/Rabc; Id = Vd/Rd => Vo/Vs = 2*Rl*Rd*Vabc/(Rs*Rabc*Vd) = Vabc*0.11 => +10dBm peak voltage is transformed to 1.57V(max) to 6.15mV(min) (8 bit DAC, 4V reference) R425 2 U404A FLAT2 3 R428 22K DEV_H_L

1
U403A 2 DG411 R452 10k HIGH_GAIN 3

R448 10K LINE_INP

11

LINE2_GAIN

22K

LINE_IN2

LINE_IN2

VCC

R450 U402C C423 8 1uF R457 10K 6 7 5 LM224 R461 120K 3n3F R431 120K U405B C402 (NPO) 7

8
U403B -2.5V 7 DG411 1 R434 4K7 R458 R447 47K U407A R427 47K 2 1 3 LM224 1uF R437 47K R435 1K C428 R465 100K 6 7 5 LM224 R456 47K R438 47K R418 5k6 6 R449 5k6 R442 4K7 R464 270K U407B R443 4K7 D401 10 9 U407C LM224 8 AUDIO_OUT AUDIO_OUT D402 BAV99 +2.5V

LM13700

DG411 6 U404B R439 4K7 GND 3 2

U405A LM224

270K R410 47K

GND

-10V

GND

-10V GND

C418 100nF

4K7

R407 10K LINE_IN1 LINE_IN1 R403 22K 14 15 13 R417 560R C GND +10dBm max input => |Vin| < 3.46V For peak distortion of 0.3% max input to transimpedance amplifier is 100mV => need 25dB attenuation NB: Is max (3.46/18) is less than Id/2 (0.5ma) R416 560R

+10V LINE1_GAIN U402B

-10V PRE_EMPH2 -10V

16

VCC

R463 120K C425 9 R462 10K U405C 9 8 10 LM224 FLAT1 C403 (NPO) 10 3n3F R432 R409 120K R426 22K DG411 15 U404D 14 GND -10V

BAV99 -10V GND R444 4K7

B LM13700

12

10 R422 120K U402D R424 10K

R445 47K

16

1uF

R429 22K 12 DG411 11 R440 U404C 4K7 13

U405D LM224 14 R460 4K7 R459 4K7 R430 47K C409 100nF GND U403E DG411

+5V +10V

+10V C405 C410 100nF GND U400E LM224 -2.5V C411 GND 100nF

-10V +5V +10V C C412 100nF GND

12

13

GND

12 GND VL 5

V+

V-

270K R411 47K +5V D400 BAV99 R404 56K 13 12 LM224 R451 47K U400D 14 100nF R433 -10V (NPO) C407 C404 3n3F DG411 15 14 U403D EN_uPHONE GND

V-

GND U404E DG411 C406 100nF

PRE_EMPH1

-10V +5D1 R467 4K7

GND -10V 100nF GND R436 4K7

-10V GND GND D403 14 BAV99 PWRCNTRL -10V GND C416 100nF

C400 uPHONE_IN 33uF

R400

R401 270R

330R C401 10nF

PWR_CNTRL_HIGH

R453 10K

LM224 12 13 U407D

GND GND

+2.5V -10V

270K

16

C426

+10V

C413

GND 100nF PWR_CNTRL_HIGH B Vref C408 100nF +5V C419 6 100nF GND 13 12 10 11 G RCK SRCLR SRCK U400B LM224 7 Q401 MMBT3906 LINE1_GAIN GND R419 22K R421 22K PWR_CNTRL_HIGH

100nF GND R455 R408 5K6

R413 1K B

V+

U405E LM224

V+

U407E LM224

10K

V-

V-

GND

11

11

C427

C414

R405 5K6

LM224 5 6 U302B 7 LCD_BIAS

GND 100nF

-10V

100nF GND

R454 PWR_CNTRL_RAW LCD_BIAS_RAW R412 10K 10K

R466 2K2

16

+5V U401 Dout Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 74HC595A 9 7 PRE_EMPH2 6 FLAT2 5 PRE_EMPH1 4 FLAT1 3 TEST_DEV 2 HIGH_GAIN 1 AUDIO_DEV_U/D 15 AUDIO_DEV_INC C422

VCC

13

LINEINP_DEN RESET SCLK

LINEINP_DEN RESET SCLK

100nF GND 5 7 6 9 10 11

U406

+5V

VCC

Vref

PDE CLR LDAC CS SCLK Din

9 OUTA OUTB OUTC OUTD 2 1 16 15 8 4 10

LM224 U400C 8 Q400 MMBT3906 LINE2_GAIN

MOSI

Din

GND

MOSI

14

AUDIO_DEV_U/D AUDIO_DEV_INC

DGND

A GND MOSI SCLK RESET LINEINP_ADSEL

AGND

Dout UPO

C415

11

V-

V+

-10V

GND

GND VL

V+

13

100nF

12

14

A Rev No. ECO No. Description of Change

MAX534 EN_uPHONE GND

Title Line Input Processing Section

Size:

A3

Number:

9154
23:31:21 Sheet 4 Originator: of 9

Revision:

LINEINP_ADSEL

RF Technology Pty Ltd

Unit 10, 8 Leighton Place Hornsby, NSW 2077 Australia

Print Date: 20-Feb-2002 Rev. Release Date: File:

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - lineinp.sch

TERM_EN2 TERM_EN1 R317 uPHONE_IN AUDIO_XFRMR D F300 L2+ 120mA 1.5KE11CA L227R 22uF D300 R301 * C300 27R 7 DG411 R300 T300 LINE_IN2 TP300 U301B 6 Line Input Processing Section lineinp.sch uPHONE_IN LINE_IN2 LINE_INP LINE_IN1 PWRCNTRL RESET F301 L1120mA 27R 10 R303 L1+ 27R 1.5KE11CA D301 * C301 22uF R306 GND TERM_EN1 DG411 R310 560R R302 AUDIO_XFRMR T301 LINE_IN1 TP301 U301C 11 GND LCD_BIAS 1K + C304 3u3F D307 BAT54C R324

+5V

LINE_LEVEL_SENSE 1k D305 BAV99 R312 22K D

GND LINE_INP PWRCNTRL LCD_BIAS PWRCNTRL LCD_BIAS

GND

TERM_EN2

R309 560R

PWR_CNTRL_HIGH DEV_H_L AUDIO_DEV_INC AUDIO_DEV_U/D LINEINP_ADSEL LINEINP_DEN SCLK MOSI AUDIO_OUT AUDIO_DEV_INC AUDIO_DEV_U/D

C312 12V GND D306 SM4004 MR62-12 1uF AUDIO_OUT R313 22K R315 22K Q300 BSS138 2 3 GND R307 4K7 R311 22K R316 10K GND +5D3 R308 2K2 R314 10K -10V GND B C E 4N32 GND TONE GENERATION SECTION tonetx.sch 6 5 R326 47K LOOP_DET +2.5V +2.5V R328 Q301 10K TP303 R330 47K TONE_OUT 5 4 -10V -10V U303 LM224 U302A 1 R321 68K R325 47K C302 2n2F R322 68K (NPO) C305 10nF R323 68K (NPO) C306 12 14 13 LM224 R336 22K R335 22K R327 47K 120pF (NPO) GND R318 120K R319 120K R320 120K U302D R332 68K 10 9 TP305 MOD_OUT LM224 8 MOD_OUT MOD_OUT C TP302

3 5

8
10R RL300

R304 330R

R305 330R

GND

U302C

LOOP/VOLTS_SEL

LOOP/VOLTS_SEL

GND

D303 BAV99 1 D304 BAV99 2 3

U300 A K NC

LOOP_DET

TONE_OUT

AUDIO_DEV_INC

VDD

MMBT3906

R333 1K R334 NF B GND

RESET PWR_CNTRL_HIGH B DEV_H_L LINEINP_ADSEL LINEINP_DSEL FILTER_OFF CTCSS_SEL SCLK MOSI F302 TONE+ 120mA 1.5KE11CA TONEEXT_TONE_SEL TONE_DEV_U/D TONE_DEV_INC D302

INC U/D

TONE_OUT MMBT3906 R329 10K

-2.5V +2.5V

GND

MAX5161L

FILTER_OFF CTCSS_SEL SCLK MOSI TONEP+ TONE_INT TONE_INT AUDIO_DEV_U/D

-2.5V Q302

R331 47K

TONEPEXT_TONE_SEL TONE_DEV_U/D TONE_DEV_INC +10V +5V +10V

-2.5V

12

13

C307 100nF GND

C309 100nF GND U301E DG411

C310 100nF GND

V+

V-

V-

* C300, and C301 are Bipolar electrolytic capacitors

U302E LM224

GND VL

V+

A Rev No. ECO No. Description of Change

11

Title Audio Processing Section

C311 100nF Size:

-10V

C308 100nF GND

GND -10V

A3

Number:

9154
23:30:34 Sheet 3 Originator: of 9

Revision:

RF Technology Pty Ltd

Unit 10, 8 Leighton Place Hornsby, NSW 2077 Australia

Print Date: 20-Feb-2002 Rev. Release Date: File:

GND 1 2 3 4 5 6

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - audio.sch

4 +10V R703 120R

R716 C748 10nF 47R C724 L714 330nH 10nF

Q707 MMBT3904 R717 C754 100nF + 10K C723 3u3F

+10V

+10V

R718 120R C721

R730 220R L706 330nH C722 100nF

C736 R738 220R GND 100nF GND C772 GND L708 330nH R733 330R

100nF GND C702 MOD_VCO_OUT 10nF

GND C737 GND C732 R737 1K C733 12pF 5p6F D700 BAT17 R709 10K Q704 MMBFJ309 10nF C739 10nF L716 12n5H A04T C750 D701 D702 NF C718 100nF Vref C762 10nF L724 330nH GND GND R744 Q701 BSS138 C743 C745 10nF GND -5V R729 10R GND GND R707 R704 C703 100nF 120R C774 8 +10V 100nF 7 R723 10K U704A 3 A 2 4
VCC

D L712 220nH MOD_PLL_IN

100nF

U705 1

C708

22pF MMBV109 L726 82nH

MSA0611

22pF

+10V

4
U702 1

R701 47R C715 100nF GND

R740 120R 100nF C770 L709 330nH C705 22pF GND C709

C704

GND

GND 3

22pF GND 1

MSA0611

22pF

GND R722 22K

GND

U701

MSA0311 R711 100K C760 1uF

+5Q C719 C752 100nF 1uF GND R725 22K Q700 1 3 MMBT3906 TS971LT BALANCE BALANCE

R734 4K7 R735 22K

5
U707 4

10K

MOD_VCO_EN Q706 BSS138 R710 T/R_RELAY 2K2 C C749 10nF L725 3u3H C713 100nF 100nF R706 220R R700 120R C700 L700 27nH C726 3p9F MX700 MIXER L722 220nH C757 120pF L721 270nH C758 120pF L720 220nH C759 47pF 2 LO IF RF 6 3 GND 100nF L710 330nH L701 39nH C727 15pF L702 27nH C728 15pF C734 3p9F C771 220R GND +10V

100nF

2
-5V +10V C776 100nF GND R727 2PORT_MOD 22K

C714 VCO_OUT 150pF C765 56pF 3

GND

GND GND GND

10nF

GND

MSA0611 C755 47pF

L703

L704 47nH C729 15pF

L705 27nH C735 3p9F

R742 820R R724 56R

C707 3 22pF R714 56R MSA0611

U706 1

R715 10K

LM13700 5 R720 100K

C716

5 4 1

27nH C717 C731 15pF

22pF

-10V

GND 3p9F

6
R731 560R

C756 10pF

U704C

11

U700 1

GND C763

C775 100nF

R743 560R

GND -10V +10V

GND

R736 1K C730 10nF R745 220R GND

R726 47R

Q702 MMBT3904 R719 C753 100nF GND C738 + 10K 3u3F C712

+10V GND -10V GND

120R R705 220R B C710 100nF GND L711 330nH

LM13700 C706 12 100nF B

16

R702

U704B 14 15 13

C720 L715 330nH 10nF

B C751 L717 100nH CHAN_PLL_IN 33pF D704 D705 NF MMBV109 C725 C711 C773 1uF R713 100K 100nF

GND GND C740 C761 R741 4K7 4p7F C741 NF GND

Q705 MMBFJ309 D703 BAT17 R739

10nF C747 10nF 10K L719 18n5H A05T L707 NF

C701 CHAN_VCO_OUT 10nF 3

U703 1 C764 6p8F

MSA0611

22pF

L723 330nH C742

GND

10nF GND

-5V

GND

GND R708 4K7 R732 22K M1 A RFSCREEN1 GND Size: GND Rev No. ECO No. Description of Change A C746 10nF Q703 BSS138 10nF

CHAN_VCO_EN

CHAN_VCO_EN

GND

Title Voltage Controlled Oscillators

A3
Number:

9154
23:42:46 Sheet 7 Originator: of 9

Revision:

RF Technology Pty Ltd

Unit 10, 8 Leighton Place Hornsby, NSW 2077 Australia

Print Date: 20-Feb-2002 Rev. Release Date: File: 1 2 3 4 5 6

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - vco.sch