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Asynchronous Asynchronous Sequential Circuits
Asynchronous Asynchronous Sequential Circuits
Chapter Objectives
2
Sequential circuits that are not synchronized by a clock Asynchronous circuits Analysis of Asynchronous circuits Synthesis of Asynchronous circuits Hazards that cause incorrect behavior of a circuit
fundamental mode
Asynchronous behavior
4
R S Y
y Q
Present
Y = (y + S) + R
state y 0 1
stable state
Present state A B
Next state
SR = 00
A B
01 A A
10 B B
11 A A
Output Q 0 1
SR 10 00 01 11 A0 01 11 B1 00 10
11 A A
Output Q 0 1
Y = R (S + y) = R (S + y) = ( R + ( S + y )) = ( R + ( S + y )) z=y
11 Y 0 0
R S Y y Q
State-assigned table
Output, Q 11 A A 00 0 1 01 0 10 1 11 0
there is little to be gained in trying to make output Q go to 1 a little sooner
Y = R (S + y) = R (S + y) = ( R + ( S + y )) = ( R + ( S + y )) Q= y
Terminology
8
Asynchronous circuits
state table -> flow table state-assigned table -> transition table or excitation table
table
Present state A B
CD 0x x0
Y1 w1 w2 Y2
y1
y2
Y1 = y1 y2 + w1 y2 + w1w2 y1 Y2 = y1 y2 + w1 y2 + w2 + w1w2 y1 z = y1 y2
11 Y2 Y1 11 11 10 10
Output z 0 0 1 0
11 D D C C
Output z 0 0 1 0
Output p 11
z
0 0 1 0
D C C
C C
w2w1
00
A/0
01
B/0
01
10
00
00 11
1x x1
C/1
1x x1
D/0
00
11
Output z 0 0 1 0
C C
w 1 nickel
Next-state Next state and output expressions are derived from the circuit The excitation table is derived A flow table is obtained A corresponding state diagram is derived from the flow table if desired
17
1
A/0 1
0
B/1 0 1 C/1 0
0 1 D/0
A/0
B/1
0 D/0 1
C/1
State assignment
21
Present P t state y 2y 1 00 01 10 11 00 10 10 00 Next state w= 0 w= 1 Output z 01 01 11 11 0 1 1 0
Y 2Y 1
Present state y 2y 1 00 01 11 10
Y 2Y 1 00 11 11 00
Y1 = wy2 + w y1 + y1 y2 Y2 = wy2 + w y1 + y1 y2 z = y1
w y1 z
y2
D w
Q Q
Synchronous solution
Asynchronous solution
The asynchronous implementation is more complex than the synchronous one? It s negative-edge-triggered Its a negative edge triggered master/slave F/F
With the complement of its output connected to its D input
Master D Q ym
Slave D Q ys Q Q
Clk Q
Clk Q
Present state ym ys 00 01 10 11
CD
11 10 11 10 11
Output Q 0 1 0 1
(a) Excitation
Next state CD = 00 S1 S1 S4 01 S1 S4 S4 10 S1 S2 S1 S2 11 S3 S4 S3 S4
0x 11 10 S2 1 10
0x
S4 1
0x x1
Y1 = wy2 + w y1 + y1 y2 Y2 = wy2 + w y1 + y1 y2 z = y1
y1 = ym , y2 = y s w = C , y 2 = D, z = y1 = ym
D
w
y1=z
y2
Q Q
Clk Q
Clk Q
29
In I asynchronous circuits h i it
undesirable glitches on signals should not occur hazards
the glitches cause by the structure of a given circuit and propagation delays in the circuit
Definition of hazards
31
Usual solutions
wait until signals are stable by using a clock
preferable easiest to design when there is a clock synchronous circuits
Static hazards
33
x2 x1
f = x1 x2 + x1 x3
f = x1 x2 + x1 x3 + x2 x3
x2 x1
x3
x3
x3
hazard free hazard-free if more than one bit of inputs change simultaneously ?
Present state ym ys 00 01 10 11
CD
11 10 11 10 11
Output Q 0 1 0 1
(a) Excitation
CD ymys 00 01 11 10 1 1 1 1 00 01 11 1 1 1 1 10 ymys
00 00 01 11 10 1 1
01
11
10
Ym = CD + C ym + Dym Ys = C ym + C s + ym y s Cy
1 1 1 1
1 1
D ym C
D Ym
Ym Ys C Q Ys Q
ys
ys
Ym = CD + C ym + Dym Ys = C ym + C s + ym y s Cy
x1 x2
x3
x3
dynamic hazards
37
there exist multiple paths f a th i t lti l th for given signal change to propagate along neither easy to detect nor easy to deal with using t i two-level h l l hazard-free d f circuits
b x1 x2 x3 x4 (a) Ci it ( ) Circuit a c d f
38
Clock skew
39
Data Clock
Q Q
ff
ff
ff
ff
ff
ff
ff Clock ff
ff
ff
ff
ff
ff
ff
ff
ff
setup time tsu hold time th register delay or propagation delay trd output delay time tod
required for the change in Q to propagate to an output pin on the chip
t Data
Data
A
Clock
Out
at an output pin
tClock + trd + tod
Synchronizer Q0
Clock D Q Q1 D Q
Clock Q1
Clock
Clock
Never allow asynchronous inputs to be fanned out to more than one FF within the synchronous system
What Can Go Wrong Setup time violation! In is asynchronous Fans out to D0 and D1 One FF catches the signal, one does not impossible state might be reached!
In Q0 Q1 Clk
Synchronizer Failure When FF input changes close to clock edge, the FF may enter the metastable state: neither a logic 0 nor a logic 1 In out
D Q
It may stay in this state an indefinite amount of time, although this is not likely in real circuits
Logic 1
Logic 0
Logic 0
Logic 1
Time
Small, but non-zero probability that the FF output will get stuck in an in-between state
Oscilloscope Traces Demonstrating Synchronizer Failure and Eventual Decay to Steady State
Solutions to Synchronizer Failure the probability of failure can never be reduced to 0, but it can be reduced slow down the system clock this gives the synchronizer more time to decay into a steady state synchronizer failure becomes a big problem for very high speed systems use fastest possible logic in the synchronizer this makes for a very sharp "peak" upon which to balance S or AS TTL D-FFs are recommended cascade two synchronizers Synchronized Input Clk Synchronous System
Asynchronous Input