Professional Documents
Culture Documents
Cs623 Lec31 Full
Cs623 Lec31 Full
CS623
Timing Analysis
Identify the potential performance of a circuit Many variations in timing
Rise time vs Fall time Setup, Hold violations Gate delays and interconnect delays Exponential number of paths Clock skew and jitter
1 April 2007
CS623
1 April 2007
CS623
A Simplified Model
Assume rise and fall times are similar Gate delays are characterized ahead of time Many good models for predicting interconnect delay Assume clock skew = 0
1 April 2007
CS623
A Simple Problem?
Lets ignore interconnect delays for now What do we need to do :
Perform timing analysis between all flops to flops Find the worst case delay in each sequential stage Assign clock accordingly Design algorithms
Does not solve the inputs and the order of supply though
1 April 2007
CS623
A Nave Algorithm
Enumerate all paths Calculate delay on each path Find the worst case delay Problem?
Exponential Number of Paths Exponential algorithm
CS623
1 April 2007
CS623
Basic Sketch
Find when outputs are required at the different gates Find out when they are actually arriving If the signals arrive at every gate before they are required in every single gate, we are done
Circuit is safe
Else
Pick better gates Restructure the circuit
1 April 2007 8
CS623
Arrival Time
0 1 1 4 7 13 6 5 18
0 3
3 6
6 15
22
0 1
1 April 2007
1 4
7 5
14
18 4
CS623
Required Time
1 4 5 4 9 6 15 5 22
3 0 3
6 9
6 15 15
22
1 8
1 April 2007 10
4 9 13
5 18
4 22
CS623
Not every node is critical A path with all nodes that are critical is called the critical path
1 April 2007
11
CS623
7 9 9 9 7
13 6 15 5
18 22
15 6 15 7
22
6 3 1 4 9
13
14 18
18 4 22
CS623
Definitions
Arrival Time
AT(i) = max [AT(j)] + delay (i) where j fanin(i)
Required Time
RT(i) = min [RT(j)) delay (j)] where j fanout(i) Remember that delay (j) is subtracted here Also, notice that min encompasses subtraction
Define Slack
Slack(i) = RT(i) AT(i) Slack == 0 => Node is critical A path whose nodes all have slack 0 = critical path
13
1 April 2007
CS623
Slacks
4 1 4 4 2 6 2 5 4
6 0
8
1 April 2007
6 5
14
CS623
7 4 7 9 6 6 7 7 4 11 5 6
13 5 13
18 20
15 13 13
22 7
1 1 1 7
20
18 4 20
0 6
14 16
1 April 2007
15
CS623
Critical Edges
2 5
Failing Path
-2
-2
-2
6 -2
-2
6
1 April 2007
4 5
16
CS623
1 April 2007
Calculate Arrival Times as before Calculate slacks as before Check if there are paths that are violating timing
17
CS623
Observations on Slacks
For a circuit to run safely All slacks 0 When slacks are less than 0
Relax the constraints Pick gates with lesser delays
1 April 2007
18