5+

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

3.6864
MHz

20 pF


20 pF
10uF

PC Printer Port

5+

T0
XTAL 1
XTAL 2
RESET
SS
INT
EA
RD
PSEN
WR
ALE
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS

8048

VCC
T1
P27
P26
P25
P24
P17
P16
P15
P14
P13
P12
P11
P10
VDD
PROG
P23
P22
P21
P20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

1
2
3
4
5
6
7
8

5+

CLR
1Q
1Q
1D
2D
2Q
2Q
GND

74LS175

5+
4Q
4Q
4D
3D
3Q
3Q
CLK

16
15
14
13
12
11
10
9

5+

1
2
3
4
5
6
7
8

CLR
1Q
1Q
1D
2D
2Q
2Q
GND

74LS175

5+
4Q
4Q
4D
3D
3Q
3Q
CLK

16
15
14
13
12
11
10
9


















































































.1 uF

1
2
3
4
5
6
7
8
9
10

CS
I1
O8
I2
O7
I3
O6
I4
O5
GND

74LS244

5+
CS
O1
I8
O2
I7
O3
I6
O4
I5

20
19
18
17
16
15
14
13
12
11

1
2
3
4
5
6
7





74LS00

GND

14
5+
13
12
11
10
9
8


































1
2
3
4
5
6
7
8

5+

S0
S1
S2
EN3
EN2
EN1
Y7
GND

74LS138

5+
Y0
Y1
Y2
Y3
Y4
Y5
Y6

16
15
14
13
12
11
10
9




























1
2
3
4
5
6
7
8
9
10



5+


5+
1
2
3
4
5
6
7

1CLR
1D
1CLK
1SET
1Q
1Q
GND

74LS74

5+
2CLR
2D
2CLK
2SET
2Q
2Q

14
13
12
11
10
9
8



1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

GND
















1
2
3
4
5
6
7
8
9
10

5+

14
5+
13
12
11
10
9
8

1
2
3
4
5
6
7
8
9
10

CS
I1
O8
I2
O7
I3
O6
I4
O5
GND

CS
I1
O8
I2
O7
I3
O6
I4
O5
GND

74LS244

74LS244

5+
CS
O1
I8
O2
I7
O3
I6
O4
I5

5+
CS
O1
I8
O2
I7
O3
I6
O4
I5

20
19
18
17
16
15
14
13
12
11

20
19
18
17
16
15
14
13
12
11

04
03
02

01
Latched Command

db25 connector
1 GND
2 rst
14 p10
15 p11
16 p12
17 p13
18 p14
19 p15
20 p16
21 p17
22 p24
23 p25
24 p26
25 p27




5+
CS
O1
I8
O2
I7
O3
I6
O4
I5

20
19
18
17
16
15
14
13
12
11

5+
CS
O1
I8
O2
I7
O3
I6
O4
I5

20
19
18
17
16
15
14
13
12
11



74LS02

CS
I1
O8
I2
O7
I3
O6
I4
O5
GND

74LS244




CS
I1
O8
I2
O7
I3
O6
I4
O5
GND

74LS244

1
2
3
4
5
6
7

1
2
3
4
5
6
7
8
9
10



Data Bus 8048 route to out of 1st, 2nd command, in of nibble stat, and in of comm nibble
4 bit in from PC Printer Port routed to out nibbles on 244s
8 bit out from PC Printer Porte routed to 8048 data bus and 374 for latching next command

8 bit in to P1 nibbles
8 bit in to P2 nibbles
Port 2 low 4 route to nibble in and nibble latch in
Latched comm nibble

Design and drawings by Agatha Codrust. More details at http://coprolite.com

Notes:
.1 uF between GND and 5+ on all chips.

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10

OE
O0
D0
D1
O1
O2
D2
D3
O3
GND

CS
I1
O8
I2
O7
I3
O6
I4
O5
GND

74LS374

74LS244

5+
O7
D7
D6
O6
O5
D5
D4
O4
CP

5+
CS
O1
I8
O2
I7
O3
I6
O4
I5

20
19
18
17
16
15
14
13
12
11

20
19
18
17
16
15
14
13
12
11