A project synopsis of

Priority Interrupt Controller Design using HDL

Project Guide: Name: Mr. Ravi Payal Signature:

Name of Group members: Kunal Arora Harsh Gupta Abhishek behl

Project Co-ordinator: Name: Mr. Vinod Sharma Signature:

BLOCK DIAGRAM:

Fig. shows the internal block diagram of priority interrupt controller. It basically includes Eight Blocks Control Logic Read /Write Logic Data Bus Buffer Registers(IRR,ISR,IMR) Priority Resolver Cascade Buffer

TOOLS USED:
1. Mentor Graphics 2. Xilinx

ABSTRACT
A priority interrupt controller and synchronizer for a 8085/80C86 microprocessor have been designed with the help of the VHDL language, a silicon compiler and a standard cell library. IEEE Standard 1076 VHSIC Hardware Description Language defines this language as a tool for structural and behavioral specification for very high speed integrated circuits. VHDL supports a wide range of design abstractions. The paper examines the procedures and the use of hardware and software tools in the design and simulation of the circuit INTRODUCTION OF PIC

The Priority Interrupt Controller (PIC) is designed to relieve the system CPU from task of polling in a multi-level priority interrupt system. Let us look at the sequence of event that occur with PIC during an interrupt and service. In an 8080/85 based system:

1. One or more of the INTERRUPT REQUEST lines (IRO-IR7) are raised high, setting the corresponding bits in the INTERRUPT REQUEST REGISTER (IRR). 2. The interrupt is evaluated in the priority resolver. If appropriate, an interrupt is sent to the CPU via the INT line.

3. The CPU acknowledges the interrupt by sending a pulse on the INTA line. Upon reception of this pulse, the PIC responds by sending the opcode for a code instruction onto the data bus. 4. A second INTA pulse is sent from the CPU. At this time, the device will respond by placing the lower byte of the address of the appropriate service routine onto the data bus. 5. A final third pulse of INTA occurs and PIC responds by placing the upper byte of the address onto the data bus. The three byte call instruction is then complete. If the AEOI mode has been chosen, the bit set during the first INTA pulse in the ISR is reset at the end of the third INTA pulse.