F Pga Design

FPGADesignBasics
AltiumDesignerTrainingModule
FPGADesign
DocumentVersion1.2,February2008 Software,documentationandrelatedmaterials: Copyright2008AltiumLimited. Allrightsreserved.Youarepermittedtoprintthisdocumentprovidedthat(1)theuseofsuchisfor personaluseonlyandwillnotbecopiedorpostedonanynetworkcomputerorbroadcastinany media,and(2)nomodificationsofthedocumentismade.Unauthorizedduplication,inwholeorpart, ofthisdocumentbyanymeans,mechanicalorelectronic,includingtranslationintoanother language,exceptforbriefexcerptsinpublishedreviews,isprohibitedwithouttheexpresswritten permissionofAltiumLimited.Unauthorizedduplicationofthisworkmayalsobeprohibitedbylocal statute.Violatorsmaybesubjecttobothcriminalandcivilpenalties,includingfinesand/or imprisonment. Altium,AltiumDesigner,BoardInsight,CAMtastic,CircuitStudio,DesignExplorer,DXP,LiveDesign, NanoBoard,NanoTalk,Nexar,nVisage,PCAD,Protel,SimCode,Situs,TASKING,andTopological AutoroutingandtheirrespectivelogosaretrademarksorregisteredtrademarksofAltiumLimitedor itssubsidiaries. Microsoft,MicrosoftWindowsandMicrosoftAccessareregisteredtrademarksofMicrosoft Corporation.OrCAD,OrCADCapture,OrCADLayoutandSPECCTRAareregisteredtrademarksof CadenceDesignSystemsInc.AutoCADisaregisteredtrademarkofAutoDeskInc.HPGLisa registeredtrademarkofHewlettPackardCorporation.PostScriptisaregisteredtrademarkofAdobe Systems,Inc.Allotherregisteredorunregisteredtrademarksreferencedhereinarethepropertyof theirrespectiveownersandnotrademarkrightstothesameareclaimed.
Module1
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FPGADesign
FPGADesignBasics
1 FPGADesign......................................................................................................... 11 1.1 Learningobjectives..................................................................................... 11 1.2 Topicoutline............................................................................................... 11 IntroductiontoFPGADesign ............................................................................... 12 2.1 FPGAbasics .............................................................................................. 12 CreatinganFPGAproject..................................................................................... 13 3.1 Overview.................................................................................................... 13 3.2 Aquickwordaboutprojectsanddesignworkspaces................................... 13 3.3 FPGAproject.............................................................................................. 14 FPGAschematicconnectivity.............................................................................. 15 4.1 Overview.................................................................................................... 15 4.2 Wiringthedesign........................................................................................ 15 4.3 IncludingHDLsourcefilesinaschematic................................................... 15 4.4 Establishingconnectivitybetweendocuments............................................. 15 4.5 Usingbusesandbusjoiners....................................................................... 16 FPGAreadyschematiccomponents ................................................................... 19 5.1 Overview.................................................................................................... 19 5.2 Processorcores ......................................................................................... 19 5.3 DesktopNanoBoardportplugins .............................................................. 110 5.4 PeripheralComponents ............................................................................ 110 5.5 Genericcomponents ................................................................................ 110 5.6 Vendormacroandprimitivelibraries......................................................... 110 5.7 Exercise1CreateaPWM...................................................................... 111 Targetingthedesign........................................................................................... 113 6.1 Constraintfiles ......................................................................................... 113 6.2 Configurations .......................................................................................... 114 6.3 NanoBoardconstraintfiles........................................................................ 114 6.4 ConfigurationManager ............................................................................. 114 6.5 AutoConfiguringanFPGAproject ............................................................ 115 6.6 Definingconstraintsmanually ................................................................... 115 6.7 Editingaconstraintfile.............................................................................. 116 6.8 Exercise2ConfiguringMyPWM............................................................. 117 Runningthedesign ............................................................................................ 119 7.1 Overview.................................................................................................. 119 7.2 Controllingthebuildprocess..................................................................... 119 7.3 Understandingthebuildprocess............................................................... 120 7.4 Buttonregions .......................................................................................... 120 7.5 Accessingstagereports/outputs ............................................................. 121 7.6 Buildstages.............................................................................................. 121 7.7 Configuringabuildstage .......................................................................... 124 7.8 HowAltiumDesignerinteractswithbackendvendortools........................ 125 7.9 Exercise3RunMyPWMontheNanoBoard........................................... 125 Embeddedinstruments ...................................................................................... 126 8.1 Overview.................................................................................................. 126 8.2 OnChipdebugging .................................................................................. 126 8.3 CLKGEN .................................................................................................. 127 8.4 CROSSPOINT_SWITCH.......................................................................... 127 8.5 FRQCNT2 ................................................................................................ 127
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8.6 8.7 8.8 8.9 8.10 8.11 8.12 9
IOB_x....................................................................................................... 128 DIGITAL_IO ............................................................................................. 128 LAX_x ...................................................................................................... 129 TerminalConsole ..................................................................................... 131 Exercise4AUsingembeddedinstruments............................................. 131 WherearetheInstruments?..................................................................... 135 Enablingembeddedinstruments............................................................... 135
InteractingwiththeNanoBoard ......................................................................... 137 9.1 Overview.................................................................................................. 137 9.2 NanoBoardcommunications..................................................................... 137 9.3 Technicalbackground.............................................................................. 138 9.4 TheNanoBoardcontroller......................................................................... 140 9.5 FPGAI/Oview.......................................................................................... 141 9.6 Livecrossprobing .................................................................................... 142 9.7 Exercise4BViewMyPWMontheNanoBoard ....................................... 142 Creatingacorecomponent................................................................................ 143 10.1 Coreproject.............................................................................................. 143 10.2 CreatingacorecomponentfromanFPGAproject .................................... 143 10.3 AwordaboutEDIF ................................................................................... 144 10.4 Settingupthecoreproject ........................................................................ 144 10.5 Constrain/configure ................................................................................ 145 10.6 Creatinganewconstraintfile.................................................................... 146 10.7 Creatingaconfiguration............................................................................ 147 10.8 Synthesize............................................................................................... 148 10.9 Publish ..................................................................................................... 149 10.10 Creatingacoreschematicsymbol ............................................................ 149 10.11 Usingacorecomponent........................................................................... 151 10.12 Exercise5CreateacorecomponentfromMyPWM ............................... 152 FPGAdesignsimulation..................................................................................... 153 11.1 Creatingatestbench................................................................................ 153 11.2 AssigningtheTestbenchDocument.......................................................... 153 11.3 Initiatingasimulationsession ................................................................... 154 11.4 Projectcompileorder................................................................................ 154 11.5 Settingupthesimulationdisplay............................................................... 155 11.6 Runninganddebuggingasimulation ........................................................ 156 11.7 Exercise6CreateatestbenchandsimulateMyPWM ............................ 158 Review................................................................................................................. 159
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FPGADesign
1 FPGADesign
Theprimaryobjectiveofthisdayoftrainingistomakeparticipantsproficientintheprocessof developing,downloadingandrunninganFPGAdesignontheDesktopNanoBoard.Wewillgo throughtheFPGAdesignframeworkanddemonstratejusthowsimpleFPGAdesigniswithAltium Designer.
1.1
Learningobjectives
TobecompetentindevelopingFPGAdesignsusingstandardFPGAbasedlibrariesandthe schematiccaptureenvironment TounderstandandbeabletomakeuseoftheFPGAbuildprocess TobefamiliarwiththeperipheralcapabilitiesoftheDesktopNanoBoardandknowhowto incorporatetheiruseincustomFPGAdesigns. Toappreciatethedifferentcommunicationmechanismsusedbythesoftwaretocontrolandprobe arunningFPGAdesign. TobecompetentwiththeuseofvirtualinstrumentsinanFPGAdesign.
1.2
Topicoutline
CoreTopics FPGA Project Creation FPGA Schematic Extensions
FPGABuild Process FPGAdesign builtand loadedonto NanoBoard
NanoBoard Concepts
FPGA Instruments
AdvancedTopics(TimePermitting)
FPGACore Components
.
Digital Simulation
Figure1.TopicOutlineforPartIFPGADesignBasics.
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FPGADesign
2 IntroductiontoFPGADesign
2.1 FPGAbasics
FPGA:FieldProgrammableGateArray.Conceptuallyitcanbeconsideredasanarrayof ConfigurableLogicBlocks(CLBs)thatcanbeconnectedtogetherthroughavastinterconnection matrixtoformcomplexdigitalcircuits.
Figure2.ExplodedviewofatypicalFPGA
FPGAshavetraditionallyfounduseinhighspeedcustomdigitalapplicationswheredesignstendto bemoreconstrainedbyperformanceratherthancost.Theexplosionofintegrationandreductionin pricehasledtothemorerecentwidespreaduseofFPGAsincommonembeddedapplications. FPGAs,alongwiththeirnonvolatilecousinsCPLDs(ComplexProgrammableLogicDevices),are emergingasthenextdigitalrevolutionthatwillbringaboutchangeinmuchthesamewaythat microprocessorsdid. Withcurrenthighenddevicesexceeding2000pinsandtoppingbillionsoftransistors,thecomplexity ofthesedevicesissuchthatitwouldbeimpossibletoprogramthemwithouttheassistanceofhigh leveldesigntools. Xilinx,Altera,Actel,andLatticeallofferhighendEDAtoolsuitesdesigned specificallytosupporttheirowndeviceshowevertheyalsoofferfreeversionsaimedatsupporting thebulkofFPGAdevelopment.Thesevendorsunderstandtheimportanceoftoolavailabilityto increasedsiliconsalesandtheyallseemcommittedtosupportingafreeversionoftheirtoolsforthe foreseeablefuture. ThroughtheuseofEDAtools,developerscandesigntheircustomdigitalcircuitsusingeither schematicbasedtechniques,VHDL,Verilogoranycombinationofthesemethods.Priortothe AltiumDesignersystem,vendorindependentFPGAdevelopmenttoolswereextremelyexpensive. FurthermoretheywereonlyusefulforcircuitsthatresidedwithintheFPGAdevice.Oncethedesign wasextendedtoincludeaPCBandancillarycircuits,aseparateEDAtoolwasneeded.Altium DesignerhaschangedallofthisbybeingthefirstEDAtoolcapableofofferingcompleteschematic toPCBtoolintegrationalongwithmultivendorFPGAsupport. AltiummadethelogicalextrapolationoftrendsintheFPGAworldandrecognizedthatFPGAsare quicklybecomingastapleinmoderndesigns.Bymakingavailablearangeofprocessorcoresthat canbedownloadedontoanFPGAdeviceandbundlingthemwithacompletesuiteofembedded softwaredevelopmenttools,AltiumDesignerrepresentsaunifiedPCBandembeddedsystems developmenttool.
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3 CreatinganFPGAproject
3.1 Overview
AllcomponentsthatwillbecombinedtogetherintoasingleFPGAdesignmustbeencapsulated withinanFPGAProject. ThetermProjectreferstoagroupofdocumentsthatcombinetogethertoformasingletarget. Caremustbeexercisedwhencreatingaprojecttoensurethatthecorrectprojecttypeisselectedfor thedesiredtarget.
3.2
Aquickwordaboutprojectsanddesignworkspaces
Totheuninitiated,AltiumDesignerprojectsmayappearalittle confusingespeciallywhenprojectscontainotherprojects. Theimportantthingtorememberisthateachprojectcanonly haveoneoutput.Ifyouhaveadesignthatrequiresseveral PCBsthenyouwillneedaseparatePCBprojectforeach PCB.IfyouhaveadesignthatusesseveralFPGAsthenyou willalsoneedaseparateFPGAprojectforeachFPGAused onthefinaldesign. Projectsthatarerelatedtogetherinsomewaycanbegrouped togetherusingatypeofsuperprojectcalledaDesign Workspace.DesignWorkspacesaresimplyaconvenient wayofpackagingoneormoreprojectstogethersothatall projectsfromasingledesigncanbeopenedtogether. AltiumDesignersupportsafullyhierarchicaldesignapproach. Assuchitispossibleforsomeprojectstocontainother projectswithinthem. Figure3showsastructuralviewofthe SpiritLeveldesignthatisdistributedasanexampleinthe AltiumDesignerinstallation.Fromthisviewwecanobserve thehierarchyofthedifferentprojectsinvolved.Thetoplevel projectisaPCBprojectcalledSL1XilinxSpartanIIE Figure3.Anexampleofprojecthierarchy. PQ208Rev1.01 andhasthefilenameextensionPRJFPG. WithinthisPCBprojectisaninstanceofanFPGAProject FPGA_51_Spirit_Level.PrjFpg.RunningontheFPGAisa softcoreprocessor8051.Theprogramorsoftwarethatthisembeddedsoftcoreexecutesis containedwithinanotherprojectcalledSpiritLevel.PrjEmb. Thehierarchyofprojectsisgivenbelow.
PRJPCB PCBProject OutputisasinglePCB
PRJFPG
FPGAProject
OutputisasingleFPGA Sourcecodeforaprogramthatwillexecute onasinglesoftcore
PRJEMB
EmbeddedProject
Figure4.PossibleProjectHierarchyforadesigncontainingmultipleprojects
APCBProjectmaycontainoneormoreFPGAprojectsbutnevertheotherwayaround. Ifyouthink aboutityouwillrecognizethatitisquiteintuitiveaPCBcontainsFPGAswhereasanFPGAcant containaPCB.Similarly,anFPGAcouldcontainoneormorecustomFPGAcoresor microprocessorsoftcores.AlinkedEmbeddedProjectwilldefinethesoftwarethatexecutesoneach ofthesoftcores. 13
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3.3
FPGAproject
AnFPGAprojectshouldbeusedwhenthetargetisasingleFPGA.TheoutputofanFPGAproject willbeaconfigurationbitfilethatcanbeusedtoprogramanFPGA. ThesimplestwaytocreateaprojectisfromtheFilemenu(FileNewProject).
Figure5.CreatinganewFPGAproject
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4 FPGAschematicconnectivity
4.1 Overview
SchematicdocumentsusedinFPGAdesignsareconvertedtoeitherVHDLorVerilogintheprocess ofbeingcompiledintothedesign.Thisprocessistotallytransparenttotheuseranddoesnot requiretheusertoknowanythingspecificabouteitherofthesetwoHardwareDescription Languages(HDLs).ThisconversiontoHDLsdoesplacesomerequirementsontotheschematic documenthoweverthatmustbeconsideredtoensurethattheconversionprocessgoessmoothly andthattheresultantHDLsourcefileisvalid. Inthissectionwewilldiscusssomeoftheextensionsthathavebeenaddedtotheschematic environmentforthepurposesofservicingFPGAdesigns.
4.2
Wiringthedesign
Connectivitybetweenthecomponentpinsiscreatedbyphysicalconnectivity,orlogicalconnectivity. Placingwiresthatconnectcomponentpinstoeachothercreatesphysicalconnectivity.Matchingnet identifierssuchasnetlabels,powerports,portsandsheetentriescreateslogicalconnectivity.When thedesigniscompiledtheconnectivityisestablished,accordingtothenetidentifierscopedefined fortheproject. Notethatwhiletheenvironmentsupportscompilingprojectsusingeitheraflatorhierarchical connectivestructure,FPGAprojectsmustbehierarchical.
4.3
IncludingHDLsourcefilesinaschematic
Figure6.Linkingschematicsheetsymbolstolowerleveldocuments
VHDLorVerilogsubdocumentsarereferencedinthesamewayasschematicsubsheets,by specifyingthesubdocumentfilenameinthesheetsymbolthatrepresentsit.Theconnectivityisfrom thesheetsymboltoanentitydeclarationintheVHDLfileortheVerilogmodule.Toreferencean entitywithanamethatisdifferentfromthesourceHDLfilename,includetheVHDLEntityor VerilogModuleparameterinthesheetsymbolwhosevalueisthenameoftheEntity/Module declaredinthesourcefile(asshownabove).
4.4
Establishingconnectivitybetweendocuments
Hierarchicalnetandbusconnectivitybetweendocumentsobeysthestandardhierarchicalproject connectionbehavior,whereportsonthesubdocumentconnecttosheetentriesofthesamenamein thesheetsymbolthatrepresentsthatdocument,asshownbelow. 15
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Figure7.Connectivitybetweensheetsymbolsandlowerleveldocuments
4.5
Usingbusesandbusjoiners
U8 PORTA[7..0] O[7..0] IB[3..0] GND KEY[3..0]
Typicallytherearealargenumber ofrelatednetsinadigitaldesign. Busescanplayanimportantrole inmanagingthesenets,andhelp presentthedesigninamore readableform.
IA[3..0] J4B2_8B
Busescanbereordered, PORTB[7..0] O[7..0] U9 I0 renamed,split,andmerged.To I1 I2 managethemappingofnetsin I3 buses,thereisaspecialclassof I4 component,knownasabus I5 joiner.Busjoinerscanbeplaced I6 I7 fromtheFPGA J8S_8B Generic.IntLiblibrary(bus joinernamesallstartwiththe Figure8.Examplesofusingbusjoiners letterJ).Figure8showsexamples ofusingbusjoiners.Thereare alsomanyexamplesofusingbusjoinersintheexampledesignsinthesoftware.
LCD_BUSY VALIDKEY
GND
NotethatapartfromtheJBtypejoiner,allbusjoinerpinshaveanIOdirectionusethecorrect joinertomaintaintheIOflow.PinIOcanbedisplayedonsheetifyouenablethePinDirection optionintheSchematicPreferencesdialog. TheuseofbusjoinersinFPGAdesignsisasignificantdeparturefromhowbusconnectivityis establishedonotherschematicdocumentshoweverthebenefitsofbusjoinerssoonbecomeclear. Netsextractedfromabusjoinerneednotberelatedinanywayie.havethesamenameand differingonlybynumber(Data[0],Data[1],Data[2],etc).Thebusjoinerexampleaboveshows howasinglebuscanbeusedtorouteanumberofLCDandKeypadsignalstogether,evenallowing thejoiningofotherbussesintoasinglebusofalargerwidth.
4.5.1 Busjoinernamingconvention
Busjoinersfollowastandardizednamingconventionsothattheycanbeeasilyfoundwithinthe FPGAGeneric.IntLiblibrary. J<width><B/S>[Multiples]_<width><[B/S]>[Multiples] Forexample: J8S_8B:describesabusjoinerthatroutes8singlewirestoasingle,8bitbus. J8B_8S:describesabusjoinerthatroutesasingle,8bitbusinto8singlewires. J8B_4B2:describesabusjoinerthatroutesasingle8bitbusintotwo4bitbusses, J4B4_16B:describesabusjoinerthatroutesfour,4bitbussesintoasingle16bitbus.
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4.5.2 Busjoinersplitting/mergingbehaviour
Thebasicruleisthatbusjoinersseparate/mergethebits(orbusslice) fromleastsignificantbit(orslice)downtomostsignificantbit(orslice). Forexample,inFigure9,U17splitstheincoming8bitbusonpinI[7..0] intotwo4bitbusslices,OA[3..0]andOB[3..0].Obeyingtheleasttomost mappingattheslicelevel,thelowerfourbitsoftheinputbusmapto OA[3..0],andtheupperfourbitsmaptoOB[3..0].Followingthisthroughto thebitlevel,I0willconnecttoOA0,andI7willconnecttoOB3. ThejoinerU27mergesthefourincoming4bitslicesintoa16bitbus.With thisjoinerIA0connectstoO0,andID3connectstoO15.
4.5.3 Matchingbusesofdifferentwidthsusingthe JBtypebusjoiner
Figure9.Busjoiners
TheJBtypebusjoinerallowsyoutomatchnetsinbusesofdifferent mergeandsplitbuses widths.Itdoesthisvia2componentparameters,IndexAandIndexBthat mapfromonebusthroughtotheotherbus.TheseindicesmustbedefinedwhenyouuseaJB joiner.
Figure10.Joinbusesofdifferentwidths,andcontrolthenettonetmapping
ReadtheflowofnetsthroughaJBtypebusjoinerbymatchingfromthenetsintheattachedbus,to thefirstindexonthebusjoiner,tothesecondindexinthebusjoiner,tothenetsdefinedinthe secondbusnetlabel. LeftBusIndexAIndexBRightBus Therulesformatchingnetsateachofthepointsareasfollows:
Figure11.AnexampleofusingtheJBbusjoinertoachievesubsetmapping
Ifbothbusrangesaredescending,matchbysamebusindex(onerangemustliewithintheother forvalidconnections).InFigure11thematchingis:
IndexA9 IndexB9 ROMADDR9,thruto ADDR0 IndexA0 IndexB0 ROMADDR0

ADDR9
(InthisexampleROMADDR10thruROMADDR13willbeunconnected)
Figure12.Usingofabusjoinerforoffsetmapping
InFigure12thematchingis:
INPUTS15 INPUTS0
IndexA15 IndexB31 PORTB31,thruto IndexA0 IndexB0 PORTB16
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Figure13.Usingabusjoinerforrangeinversion
Ifonebusrangeisdescendingandanotherisascending,theindicesarematchedfromleftto right.InFigure13thematchingis:
IndexA15 IndexB31 PORTB31,thruto INPUTS15 IndexA0 IndexB16 PORTB16

INPUTS0
Figure14.Anotherexampleofusingabusjoinerforrangeinversion
InFigure14thematchingis:
INPUTS15 INPUTS0
IndexA15 IndexB31 PORTB0,thruto IndexA0 IndexB16 PORTB15
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5 FPGAreadyschematiccomponents
5.1 Overview
AwidevarietyofFPGAreadyschematic componentsareincludedwiththesystem,ranging fromprocessors,toperipheralcomponents,down togenericlogic.Placingandwiringthese schematiccomponents,orwritingVHDL,captures thehardwaredesign.TheFPGAreadyschematic componentsareliketraditionalPCBready components,exceptinsteadofthesymbolbeing linkedtoaPCBfootprinteachislinkedtoapre synthesizedEDIFmodel. Aswellascomponentsthatyouusetoimplement yourdesign,theavailableFPGAlibrariesinclude componentsforthevirtualinstruments,andthe componentsthataremountedontheNanoBoard andareaccessibleviathepinsontheFPGA. HelpforallFPGAreadycomponentscanbe accessedbypressingtheF1keywhilstthe componentisselectedinthelibrarylist.
5.2
Processorcores
Softcoreprocessorscanbeplacedfromthe \ProgramFiles\AltiumDesigner 6\Library\Fpga\FPGAProcessors.IntLib library.Atthetimeofreleaseofthismanual,the followingprocessorsandrelatedembedded softwaretoolsaresupported: TSK165Microchip165xfamilyinstructionset compatibleMCU TSK51/528051instructionsetcompatible MCU TSK80Z80instructionsetcompatibleMCU PPC405AEmbeddedPowerPCCore availableonsomeVirtexFPGAs TSK300032bitRISCprocessor Thereisalsofullembeddedtoolsupportfor: ActelCoreMP7softcore,whichrequiresthe appropriateActeldeviceandlicensetouse AlteraNiosIIsoftcore,whichrequiresthe appropriateAlteradeviceandlicensetouse XilinxMicroBlazesoftcore,whichrequiresthe appropriateXilinxdeviceandlicensetouse XilinxVirtex2ProbasedPowerPC405 AMCCPowerPC405discreteprocessorfamily ARM7,ARM9,ARM9E&ARM10Efamilies,supportedintheSharpBlueStreak(ARM20T) discreteprocessorfamily LPC2100,LPC2200,LPC2300&LPC2800ARM7baseddiscreteprocessorsfromNXP
Figure15.Thelibrariespanel
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5.3
DesktopNanoBoardportplugins
HardwareresourcesontheDesktopNanoBoardcanbeaccessedviatheuseofcomponentsfrom the\ProgramFiles\AltiumDesigner6\Library\Fpga\FPGANB2DSK01Port Plugin.IntLiblibrary.
5.4
PeripheralComponents
ManyofthehardwareresourcespresentontheNanoBoardcomewithperipheralmodulesthatcan beincludedintheFPGAdesigntoeaseinterfacingtotheexternalport. Peripheralscanbeplacedfromthe\ProgramFiles\AltiumDesigner 6\Library\Fpga\FPGAPeripherals.IntLiblibrary.
5.5
Genericcomponents
Genericcomponentscanbeplacedfromthelibrary \ProgramFiles\AltiumDesigner 6\Library\Fpga\FPGAGeneric.IntLib.This libraryisincludedtoimplementtheinterfacelogic inyourdesign.Itincludespinwideandbuswide versionsformanycomponents,simplifyingthe wiringcomplexitywhenworkingwithbuses.Aswell asabroadrangeoflogicfunctions,thegeneric libraryalsoincludespullupandpulldown componentsaswellasarangeofbusjoiners,used tomanagethemerging,splittingandrenamingof buses. Foradefinitionofthenamingconventionusedin thegenericlibraryandacompletelistingof availabledevices,refertothedocument:CR0118 FPGAGenericLibraryGuide.pdf. Wildcardcharacterscanbeusedtofilterwhen searchingthecomponentlibrary.
5.6
Vendormacroand primitivelibraries
Ifvendorindependenceisnotrequired,thereare alsocompleteprimitiveandmacrolibrariesforthe currentlysupportedvendors/devicefamilies.These librariescanbefoundintherespectiveActel, Altera,LatticeandXilinxsubfoldersin\Program Files\AltiumDesigner6\Library\.The macroandprimitivelibrarynamesendwiththe Figure16.Usingwildcardstoquicklyfindaspecific string*FPGA.IntLib.Notethatsomevendors componentintheGenericLibrary requireyoutouseprimitiveandmacrolibrariesthat matchthetargetdevice.Designsthatinclude vendorcomponentscannotberetargetedto anothervendorsdevice.
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5.7
Exercise1CreateaPWM
InthisexercisewewillcreateourfirstFPGAdesign.Inordertocompletethistaskyouwillneedto usethefollowingcomponentsfromtheirrespectivelibraries: Component

CLK_BRD
Library FPGANB2DSK01PortPlugin.IntLib
NameinLibrary CLOCK_BOARD
TEST_BUTTON
FPGANB2DSK01PortPlugin.IntLib
TEST_BUTTON
ON
SW[7..0]
1 2 3 4 5 6 7 8
FPGANB2DSK01PortPlugin.IntLib FPGANB2DSK01PortPlugin.IntLib FPGAGeneric.IntLib
DIPSWITCH LED CB8CEB
LEDS[7..0]
U1 CB8CEB Q[7..0] CE C CEO TC CLR
U2
FPGAGeneric.IntLib
INV
INV
U3 A[7..0] B[7..0] COMPM8B

I0 I1 I2 I3 I4 I5 I6 I7 U4
FPGAGeneric.IntLib
GT LT
COMPM8B
FPGAGeneric.IntLib
O[7..0]
J8S_8B
J8S_8B
1. 2. 3. 4.
OpenanewFPGAProject.SaveitasMyPWM.PrjFpg AddanewschematictoyourprojectandsaveitasMyPWM.SchDoc PlaceandwirethecomponentstocreatethePulseWidthModulator UsingcomponentsfromthetwolibrariesFPGAGeneric.IntLibandFPGANanoBoard PortPlugin.IntLib,placeandwiretheschematicshowninFigure17.
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U1 CB8CEB VCC CLK_BRD U2 TEST_BUTTON INV

ON
Q[7..0] CE C CEO TC CLR U3 A[7..0] B[7..0] COMPM8B GT LT I0 I1 I2 I3 I4 I5 I6 I7 U4 O[7..0] LEDS[7..0]
SW[7..0]
1 2 3 4 5 6 7 8
J8S_8B
GND
Figure17.Saveyourwork wewillcontinuewiththisschematicsoon
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6 Targetingthedesign
Theschematicthatwehavejustcreatedcontainsalloftheconnectivitythatmustoccurinternallyon ourFPGAdevicebutwestillneedsomefurtherinformationtomaptheportsontheFPGAschematic tophysicalpinsonanactualFPGAdevice.Thisprocessiscalledtargetingourdesign.
6.1
Constraintfiles
Ratherthanstoringdeviceandimplementationspecificdatasuchaspinallocationsandelectrical propertiesinthesourceHDLorschematicdocuments,thisinformationisstoredinseparatefiles calledConstraintfiles.ThisdecouplingofthelogicaldefinitionofanFPGAdesignfromitsphysical implementationallowsforquickandeasyretargetingofasingledesigntomultipledevicesandPCB layouts. BelowweseeaconceptualrepresentationofanFPGAdesignsittinginsideanFPGAdevice.The redlinesindicatetheporttopinmappingsthatwouldbehandledbytheconstraintfile.
Figure18.ConceptualviewshowingthelinkageofportsonanFPGAschematicroutedtophysicaldevicepins.
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6.2
Configurations
AConfigurationisasetofoneormoreconstraintfilesthatmustbeusedtotargetadesignfora specificoutput.Themigrationofadesignfromprototypetoproductionwillofteninvolveseveral PCBiterationsandpossiblyevendifferentFPGAdevices.Inthiscase,aseparateconfiguration wouldbeusedtobringtogetherconstraintfileinformationfromeachdesigniteration.Eachnew configuration(anditsassociatedconstraintfile(s)isstoredwiththeprojectandcanberecalledat anytime. Becauseconfigurationscancontainmultipleconstraintfiles,itcansometimesbehelpfultosplit constraintinformationacrossmultipleconstraintfiles.Usuallyonewouldseparatetheconstraintfiles accordingtotheclassofinformationtheycontain:
6.2.1 Deviceandboardconstraintinformation:
ThespecificFPGAdevicemustbeidentifiedandportsdefinedinthetoplevelFPGAdesignmustbe mappedtospecificpinnumbers.
6.2.2 Deviceresourceconstraintinformation:
Insomedesignsitmaybeadvantageoustomakeuseofvendorspecificresourcesthatareunique toagivenFPGAdevice.Someexamplesarehardwaremultiplicationunits,clockmultipliersand memoryresources.
6.2.3 Projectordesignconstraintinformation:
Thiswouldincluderequirementswhichareassociatedwiththelogicofthedesign,aswellas constrainsonitstiming.Forexample,specifyingthataparticularlogicalportmustbeallocatedto globalclocknet,andmustbeabletorunatacertainspeed.
6.3
NanoBoardconstraintfiles
ConstraintfilesforusewiththeNanoBoarddaughter/peripheralboardmodulescanbefoundinthe \ProgramFiles\AltiumDesigner6\Library\Fpgadirectory.Toprotectthesesystem filesfrominadvertentmodification,itisadvisabletomakethisdirectoryreadonly.
6.4
ConfigurationManager
ThegroupingofmultipleconstraintsintoasingleconfigurationismanagedviatheConfiguration ManageraccessiblebyrightclickingtheFPGAprojectintheProjectspanelandselecting ConfigurationManagerfromthemenu.
Figure19.ConfigurationManagershowingmultipleconfigurationsandconstraintfiles.
Figure19showstheConfigurationManagerdialogforaprojectthatcontainsmultipleconfigurations andconstraintfiles.TheConstraintfilesarelistedintheleftcolumnandcanbeincludedina Configuration(listedastheheadingsinthefourrightcolumns)byplacingatickattherow/column intersectionpoint.Althoughthisexampleonlyshowsoneconstraintfilebeingusedineachofthe configurations,thereisnoreasonwhyaconstraintfilecantbeusedbymorethanoneconfiguration noristhereanyreasonwhyaconfigurationcantmakeuseofmultipleconstraintfiles.
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6.5
AutoConfiguringanFPGAproject
Configuringadesignforuse withtheDesktopNanoBoard hasbeenalmostcompletely automatedwiththeintroduction oftheAutoConfigurationoption inAltiumDesigner.Fromthe DevicesViewlocatedunder ViewDevicesViewor alternativelyaccessedfromthe iconinthetoolbar,simply rightclicktheimageofthe DesktopNanoBoardandselect theoptionConfigureFPGA Project<ProjectName>.
Figure20.AutoconfiguringanFPGA
ThiswillautomaticallyconfiguretheFPGAProjecttoincludetheconstraintfilesrequiredtotargetthe hardwareontheDesktopNanoboardandwilllaunchtheConfigurationManagerdialogforthe currentFPGAproject.
Figure21.Autoconfigurationdisplayedintheconfigurationmanager
6.6
Definingconstraintsmanually
Oftenitisnecessarytomanuallycreatedesignconstraints.Theseincludeconstraintsforsuch physicalattributesasthefrequencyofasystemclock,ortheassociationofsignalstospecificdevice pins(suchasonemightexpecttofindwhentargetingadesignforauserboard).Tocreateauser constraintfile,rightclicktheFPGAprojectandselectAddNewtoProjectConstraintFile.This willcreateanewblankconstraintfileandaddittotheproject.
Figure22.Newblankconstraintfile
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6.7
Editingaconstraintfile
Constraintfileadditions/modificationscanbemadebymanuallyeditingtheconstraintfileorby usingtheDesignAdd/ModifyConstraint menu.
Figure23.Add/ModifyConstraintmenuoptions
6.7.1 Specifyingportconstraints
UsetheAdd/ModifyConstraintPortto applyaconstrainttoaportintheFPGA project.
Figure24.Add/ModifyPortConstraintdialogbox.
SelectingOKfromthedialogboxinFigure24willcausethefollowingconstrainttobeaddedtothe constraintfile:
Record=Constraint|TargetKind=Port|TargetId=CLK_BRD|FPGA_CLOCK_PIN=True
ThisconstraintwillensurethattheVendorFPGAtoolsroutetheCLK_BRDporttoaspecialized clockpinonthetargetdevice. Alternatively,theFPGA_PINNUM constraintcanbespecifiedtolocktheport toaspecificpinonthetargetdevice.
Figure25.Add/ModifyPortConstraintdialogbox.
SelectingOKfromthedialogboxinFigure25willaddtheconstraintFPGA_PINNUM=P185tothe CLK_BRDportconstraint. AcompletelistofthesupportedconstraintsandtheirsyntaxcanbefoundinthedocumentTR0130 ConstraintFileReference.PDFlocatedundertheKnowledgeCenterorfromtheAltiumwebsite.
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6.8
Exercise2ConfiguringMyPWM
buttoninthe
1. SwitchtotheDevicesViewunderViewDevicesViewsorbyhittingthe toolbaratthetopofthescreen.
2. RightClicktheimageofthe DesktopNanoboardatthetop ofthewindowandselect ConfigureFPGA ProjectMyPWM.PrjFpgas seeninFigure26. Becausewearetargetingour designfortheDesktop NanoBoard,wewillbeusing existingconstraintfiles locatedintheAltiumDesigner 6\Library\FPGAdirectory. Whenweelecttoauto configureaswehaveinthis Figure26.ConfiguringtheFPGAProjectAutomatically fashion,AltiumDesignerwill retrieveinformationaboutthe daughterboardandvariousperipheralboardsthatwehavepluggedintotheDesktop NanoBoardandaddconstraintfilesasrequired. 3. AfterlaunchingtheConfigureFPGAProjectcommand,theConfigurationManagerFor MyPWM.PRJFPGdialogshouldcomeupandshowalistingofalloftheconstraintsfilesthat havebeenautomaticallyincludedunderthisnewconfiguration.
Figure27.ConfigurationManagerwithconstraintfilesaddedbytheConfigureFpgaProjectcommand.
ClickOKtoclosethisdialogandtheHardJTAGChainshouldnowappearinthemain window.YoumaynoticethatanewSettingsfolderhasbeenaddedtotheproject.Inthis folderyouwillfindaConstraintFilesfolderwithallofthenewlyaddedconstraintfiles. Severalofthefileswillhaveashortcut symbol.
Figure28.BuildflowafterautoconfiguringtheFPGAdesign.
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4. TheautoconfigurationprocessdealswiththemappingofportsdefinedonthetoplevelFPGA schematicdocumentandtheirtargetFPGApins.Thereare,however,additionalconstraints (suchastheclockfrequency)thatareimportantforthedesignbutwhichcannotbehandled automatically.Inordertocapturethisinformation,itisbesttocreateanotherconstraintfilethat isreservedforthisinformationandaddittotheconfiguration.RightclicktheFPGAproject andselectAddNewtoProjectConstraintFiletoaddanew,blankconstraintfile. 5. 6. 7. 8. SavethenewconstraintfilewiththenameMyConstraint.constraint SelectDesign>>Add/ModifyConstraint>>Port . IntheAdd/ModifyPortConstraintdialogsettheTargettoCLK_BRD SettheConstraintKindtoFPGA_CLOCK_FREQUENCY
9. SettheConstraintValueto50MHz. 10. ClickOKtoclosetheAdd/ModifyPortConstraintdialog. 11. ObservethatanewconstraintrecordhasbeenaddedtoMyConstraints.Constraint. 12. Saveyourwork. 13. ReturntotheConfigurationManagerandaddMyConstraint.Constrainttotheexisting configuration. 14. Saveyourproject.
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7 Runningthedesign
HavingjustconfiguredourdesignfortheNanoBoardthenextstepistobuildandrunthedesignon theNanoBoard.
7.1
Overview
BeforeanFPGAdesigncanbedownloadedontoitstargethardware,itmustfirstundergoamulti stagebuildprocess.Thisprocessisakintothecompilationprocessthatsoftwareundergoesin ordertocreateaselfcontainedprogram.Inthissectionwewilldiscussthevariousstepsnecessary tobuildanFPGAdesigntothepointwhereitisreadytobedownloadedontothetargetdevice.
7.2
Controllingthebuildprocess
TheprocessofconvertingaschematicorVHDLdescriptionofadigitalcircuitintoabitfilethatcan bedownloadedontoanFPGAisquitecomplex.Fortunately,AltiumDesignergoestogreatlengths toensurethatnavigationthroughthisprocessisaseasyaspossible.Asavendorindependent FPGAdevelopmenttool,AltiumDesignerprovidesatransparentinterfacetothevendorspecific backendtools.CurrentlyAltiumDesignersupportsinteractionwithActelDesigner(Actel),QuartusII (Altera),ispLEVER(Lattice),andISE(Xilinx)toperformFPGAprocessing.Thisisallhandled seamlesslythroughtheDevicesView(ViewDevices).TheDevicesViewprovidesthecentral locationtocontroltheprocessoftakingthedesignfromthecapturestatethroughtoimplementingit inanFPGA.
Figure29.DevicesviewofanFPGAdesignthatisyettobeprocessed.
WhenrunintheLivemode,AltiumDesignerisintelligentenoughtodetectwhichdaughterboard deviceispresentontheDesktopNanoBoard.Intheaboveinstance,ithasdetectedthatthe Spartan3daughterboardisinstalled.Withthisinformation,itthensearchesthecurrentprojects configurationlisttoseeifanyconfigurationsmatchthisdevice.Ifmorethanoneconfigurationis found,thedropdownlistbelowthedeviceiconwillbepopulatedwithalistofvalidconfigurations.If noconfigurationcanbefound,thelistwilldisplaythefollowing:
Figure30.ThismessageindicatesthattheprojectisnotconfiguredtotargettheavailableFPGA.
Assumingavalidconfigurationcanbefound,thesimplestwaytobuildanddownloadadesignonto theNanoBoardistoleftclickontheProgramFPGAbutton.Thiswillinvoketheappropriatebuild processesthatneedtoberun.Intheaboveexamplewherenopreviousbuildshavetakenplace,all processeswillneedtoberun. Inothersituationswhereaprojecthasjustbeenmodified,itmaybe necessaryforonlyasubsetofthebuildprocessestorun.
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7.3
Understandingthebuildprocess
Figure31.NavigatingthroughtheBuildProcessflow.
BuildinganFPGAprojectrequiresprocessingthroughanumberofstages.Navigationthroughthe buildprocessisaccomplishedviathefourstepscircledinFigure31.Thefunctionofeachstagewill beexplainedshortly.
7.4
Buttonregions
Eachofthemainbuttonsdisplayedinthebuildflowhaveseveralregionsthatprovideinformationor controlovertheindividualbuildstage.
7.4.1 StatusLED
Thecoloredindicatortellsyouthestatusofthatparticularstepintheoverallbuildflow.
Grey Red Yellow NotAvailableThesteporstagecannotberun. MissingThesteporstagehasnotbeenpreviouslyrun. OutofDateAsourcefilehaschangedandthesteporstagemustberunagaininorder toobtainuptodatefile(s). RunningThesteporstageiscurrentlybeingexecuted. CancelledThesteporstagehasbeenhaltedbyuserintervention. FailedAnerrorhasoccurredwhilerunningthecurrentstepofthestage. UptoDateThesteporstagehasbeenrunandthegeneratedfile(s)areuptodate.
Blue Orange Magenta Green
7.4.2 Runall
Clickingonthearrowiconwillforcethecurrentstageandallpriorstagestorunregardlessof whethertheyhaveruntocompletionpreviously.Selectingthisiconwillforceatotallycleanbuild evenifthedesignhasbeenpartiallybuilt.
7.4.3 Run
Selectingthelabelregionwillrunthecurrentstageandanypreviousdependantstagesthatarenot uptodate.Thisisthequickestwaytobuildadesignasitonlybuildsthoseportionsofthedesign thatactuallyrequireit.
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7.4.4 Showsubstages
Selectingthedownarrowwillexposeadropdownlistofthevarioussubstagesforthecurrentbuild stage.ThestatusofthevarioussubstagesisindicatedbythecolorofthestatusLED.Wherea substagehasfailed,theassociatedreportfilecanbeexaminedtohelpdeterminethecauseofthe failure.
Figure32.Substagesavailableunderthemainbuildstage.
7.5
Accessingstagereports/outputs
Allgeneratedoutputfilesarestoredinafolderwiththesamenameastheconfigurationusedforthe associatedproject.ThisfolderislocatedattheoutputpathdefinedintheOptionstaboftheOptions forProjectdialog(ProjectProjectOptions).Ingeneralonlyfilesthatarecreatedaspartofthe buildprocessshouldbelocatedhere.Thisensuresthatprojectscanbecompactedbydeletingthis directorywithoutfearoflossofimportantinformation. Whereareportisavailableuponrunningastagestep,clickingontheassociated iconcanaccess it.Usethisfeaturetoaccessdetailedinformationrelatingtowhyaspecificstagemayhavefailedto build.
7.6
Buildstages
Wewillnowexplainthedifferentstagesinthebuildprocess.
7.6.1 Compile
Figure33.Compilestageoftheprocessflow.
Thisstageoftheprocessflowisusedtoperformacompileofthesourcedocumentsinthe associatedFPGAproject.Ifthedesignincludesanymicroprocessorcores,theassociated embeddedprojectsarealsocompiledproducingaHexfileineachcase. ThisstagecanberunwiththeDevicesviewconfiguredineitherLiveorNotLivemode. ThecompileprocessisidenticaltothatperformedfromtheassociatedProjectmenu.Runningthis stagecanverifythatthecapturedsourceisfreeofelectrical,draftingandcodingerrors. Note:ThesourceFPGA(andembedded)project(s)mustbecompiledeitherfromtheProjects panelorbyrunningtheCompilestageintheDevicesviewinordertoseeNexusenableddevice entriesintheSoftDevicesregionoftheDevicesview.
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7.6.2 Synthesize
Figure34.Synthesizestageoftheprocessflow.
ThisstageoftheprocessflowisusedtosynthesizethecompiledFPGAproject,aswellasanyother componentsthatneedtobegeneratedandsynthesizedtospecificdevicearchitectures.Thevendor placeandroutetoolssubsequentlyusethesynthesisfilesgenerated,duringthebuildstageofthe flow.Runningthisstagewilldeterminewhetherthedesignissynthesizableornot. ThisstagecanberunwiththeDevicesviewconfiguredineitherLiveorNotLivemode. TheactualstepsinvolvedinprovidingatoplevelEDIFnetlistandsatellitesynthesismodelfilesfor usebythenextstageintheprocessflowcanbesummarizedasfollows: Thecoresforanydesign/devicespecificblocksusedintheFPGAdesignwillbeautogenerated andsynthesized(e.g.ablockofRAMwiredtoanOCDversionmicrocontrollerforuseas externalProgrammemoryspace).Thesesynthesizedmodelswillcontaincompiledinformation fromtheembeddedproject(Hexfile). ThemainFPGAdesignisthensynthesized.AnintermediateVHDLorVerilogfilewillbe generatedforeachschematicsheetinthedesignandatoplevelEDIFnetlistwillbecreated usingtheseandanyadditionalHDLsourcefiles. Fortheparticularphysicaldevicechosen,synthesizedmodelfilesassociatedwithcomponentsin thedesignwillbesearchedforandcopiedtotherelevantoutputfolder.BothSystemandUser presynthesizedmodelsaresupported. ThetoplevelfolderforSystempresynthesizedmodelsisthe\ProgramFiles\Altium Designer6\Library\Ediffolder,whichissubdividedbyVendorandthenfurtherbydevice family. ThetoplevelfolderforuserpresynthesizedmodelsisdefinedintheSynthesispageofthe FPGAPreferencesdialog,accessedundertheTools menu. Thefollowinglistsummarizestheorder(toptobottom=firsttolast)inwhichfoldersaresearched whenlookingforasynthesizedmodelassociatedwithacomponentinthedesign:
FPGAprojectfolder Usermodelstopfolder\Vendorfolder\Familyfolder Usermodelstopfolder\Vendorfolder Usermodelstopfolder Systemmodelstopfolder(Edif)\VendorFolder\Familyfolder Systemmodelstopfolder(Edif)\Vendorfolder Systemmodelstopfolder(Edif).
7.6.3 Build
Figure35.BuildstageoftheprocessflowforXilinxdevices.
Thisstageoftheprocessflowisusedtorunthevendorplaceandroutetools.Thisstagecanberun withtheDevicesviewconfiguredineitherliveornotlivemode.
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Runningthetoolsatthisstagecanverifyifadesignwillindeedfitinsidethechosenphysicaldevice. YoumayalsowishtoruntheVendortoolsifyouwanttoobtainpinassignmentsforimportingback intotherelevantconstraintfile. TheendresultofrunningthisstageisthegenerationofanFPGAprogramming filethatwill ultimatelybeusedtoprogramthephysicaldevicewiththedesign.Thereareessentiallyfivemain stagestothebuildprocess: TranslateDesignusesthetoplevelEDIFnetlistandsynthesizedmodelfiles,obtainedfrom thesynthesisstageoftheprocessflow,tocreateafileinNativeGenericDatabase(NGD)format i.e.vendortoolprojectfile MapDesigntoFPGAmapsthedesigntoFPGAprimitives PlaceandRoutetakesthelowleveldescriptionofthedesign(fromthemappingstage)and worksouthowtoplacetherequiredlogicinsidetheFPGA.Oncearranged,therequired interconnectionsarerouted TimingAnalysisperformsatiminganalysisofthedesign,inaccordancewithanytiming constraintsthathavebeendefined.Iftherearenospecifiedconstraints,defaultenumerationwill beused MakeBitFilegeneratestheprogrammingfilethatisrequiredfordownloadingthedesigntothe physicaldevice. WhentargetingaXilinxdevice,anadditionalstageisavailableMakePROMFile.Thisstageis usedwhenyouwanttogenerateaconfigurationfileforsubsequentdownloadtoaXilinx configurationdeviceonaProductionboard. AftertheBuildstagehascompleted,theResultsSummarydialogwillappear(Figure36).This dialogprovidessummaryinformationwithrespecttoresourceusagewithinthetargetdevice. Informationcanbecopiedandprintedfromthedialog.Thedialogcanbedisabledfromopening, shouldyouwish,astheinformationisreadilyavailableintheOutputpanelorfromthereportfiles producedduringthebuild.
Figure36.Summarizingresourceusageforthechosendevice.
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7.6.4 Program
Thisstageoftheprocessflowisusedto downloadthedesignintothephysical FPGAdeviceonaNanoBoardorproduction board.Thisstageisonlyavailablewhenthe DevicesviewisconfiguredinLivemode.
Figure37.ProgramFPGAstageoftheprocessflow.
Thisstageoftheflowcanonlybeused oncethepreviousthreestageshavebeen runsuccessfullyandaprogrammingfilehas beengenerated.Agreenarrowwillpointto thedevicetobeprogrammedintheHard DevicesChain. Astheprogrammingfileisdownloadedto thedeviceviatheJTAGlink,theprogress willbeshownintheStatusbar.Once successfullydownloaded,thetext underneaththedevicewillchangefrom ResettoProgrammed(Figure38)and anyNexusenableddevicesonthesoft chainwillbedisplayedasRunning(Figure 39).
Figure38.SuccessfulprogrammingofthephysicalFPGAdevice.
Figure39.Softdevicesrunningaftersuccessfulprogramdownload.
7.7
Configuringabuildstage
Shouldyouwishtoconfigureanyofthespecificoptionsassociated witheachofthedifferentsubstagesintheFPGAbuildflow,youcan dosobyclickingontheappropriateconfigurationicon. ConsiderthecasewhereyouwanttogenerateaPROMfilefor subsequentdownloadtoaXilinxconfigurationdeviceonaproduction board.IntheprocessflowassociatedtothetargetedFPGAdevice, expandthebuildsection.ThelastentryinthebuildmenuisMake PROMFile Clickingonthe icon,tothefarrightofthismenuentry,willopen theOptionsforPROMFileGenerationdialog(Figure41).From hereyoucanchoosethenonvolatileconfigurationdevicethatwillbe usedbytheproductionboardtostoretheFPGAconfiguration.
Figure41.AccessingtheoptionsdialogforPROMfilegeneration.
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7.8
HowAltiumDesignerinteractswithbackendvendortools
IfyouarealreadyfamiliarwiththebuildflowsofferedbyAlteraandXilinx,youwillbefamiliarwith oneorbothofthefollowingpanels:
Figure42.Xilinx(left)andAltera(right)vendortoolinterfaces.
AlthoughAltiumDesignerhasitsownHDLsynthesizer,itisreliantonbackendvendortoolsto implementthedesignonaspecificdevice.Thismakessense,asitisthedevicevendorswhohave themostintimateknowledgeoftheirspecificdevicesandwhohavealreadydevelopedwellproven targetingtechnologies. Mostvendorspecifictoolshavebeendevelopedinamodularfashionandcontainanumberof separateexecutableprogramsforeachphaseoftheimplementationprocess.ThevendorGUIsthat arepresentedtotheuserarecocoordinatingprogramsthatsimplypasstheappropriateparameters tobackend,commandlineprograms. WhenitcomestoFPGAtargeting,AltiumDesigneroperatesinasimilarfashioninthatitactsasa coordinatorofbackend,vendorspecificprograms.Parametersthatneedtobepassedfromthe AltiumDesignerfrontendtothevendorspecificbackendprogramsarehandledbyaseriesoftext basedscriptfiles.Userswhoarealreadyfamiliarwiththebackendprocessingtoolsmayfindsome useinaccessingthesescriptfilesshouldtheywishtomodifyortweakinteractionwithbackend processingtools.Thishoweverisconsideredahighlyadvancedtopicandonethatshouldbe handledcautiously.Ensurebackupsaretakenpriortomodification. ThefilescontrollinginteractionwithvendorspecificbackendtoolscanbefoundintheSystem directoryundertheAltiumDesigner6installdirectory.Thenamingconventionusedforthese filesis: Device[Options|Script]_<vendor>[_<tool>|<family>].txt soforexampleDeviceOptions_Xilinx_PAR.txtcontrolsthedefaultoptionsforXilinxsPlace andRoutetool.
7.9
Exercise3RunMyPWMontheNanoBoard
InthisexerciseweshalltakeourpreviouslydevelopedPWMdesignandrunitontheNanoBoard. 1. EnsurethattheNanoBoardiscorrectlyconnectedtothePC,theXC3S15004FG676Cdaughter boardisloaded,andtheNanoBoardisswitchedon. 2. OpentheDevicesViewandensuretheLivecheckboxisticked. 3. ClickonthelabelregionoftheProgramFPGAbuttonintheFPGABuildflow.Thedesignwill beginbuildingandmaytakeamomentortwotocomplete. 4. Ifanybuilderrorsoccur,diagnoseandrectifytheerrorandattemptthebuildprocessagain. 5. Oncedownloaded,verifytheoperationofthedesignbyswitchingdifferentDIPswitchesoffand on.YoushouldnoticeachangeintheLEDillumination.
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8 Embeddedinstruments
8.1 Overview
SofarwehavebuiltourPWMFPGAdesignandrunitontheNanoBoard.Fortunatelythisdesign providedanoutputontheLEDsthatenabledustoimmediatelyverifythatthecircuitwasperforming asweexpected.Buthowdoweverifyotherdesigns?Inthissectionwewillintroducetherangeof embeddedinstrumentsthatcanbeintegratedintoFPGAdesignstofacilitateonchiptestingand debugging.
8.2
OnChipdebugging
AbigconcernofmanyembeddedsystemsdesignerstransitioningtoFPGAbaseddesignisthe issueofdebugginghowdoesoneseeinsideanFPGAcircuittodiagnoseafault?Whattheymay notbeawareofisthattheflexibilityofFPGAdevicesenablestypicaltestandmeasurement instrumentstobewiredinsidethedeviceleadingtofareasierdebuggingthanwhathaspreviously beenpossible. TheAltiumDesignersystemincludesahostofvirtualinstrumentsthatcanbeutilizedtogain visibilityintothehardwareandquicklydiagnoseelusivebugs.Theseinstrumentscanbefoundin theFPGAInstruments.IntLibintegratedlibrary.Thehardwareportionoftheinstrumentis placedandwiredontheschematiclikeothercomponents.Oncethedesignhasbeenbuilt,realtime interactionwitheachinstrumentispossiblefromtheDevicesView.
Figure43.Embeddedinstrumentsdisplayedinthedevicesview.
Thecontrolsfortheindividualembeddedinstrumentscanbeaccessedbydoubleclickingtheir associatediconintheDevicesView.
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8.3
CLKGEN
Figure44.Frequencygenerator,usedtogeneratethespecifiedfrequency
Thefrequencygeneratoroutputsa50%dutycyclesquare U7 wave,ofthespecifiedfrequency.Clickingtheappropriate buttoncanchooseanumberofpredefinedfrequencies,ora TIMEBASE FREQ customfrequencycanbeselectedusingtheOtherFrequency button.Ifthespecifiedfrequencycannotbegeneratedthe FrequencyGenerator closestpossibleisgeneratedandtheerrorshownonthe CLKGEN display.Notethatwhenthefrequencygeneratorisinstantiated intheFPGAitwillnotberunning,youmustclicktheRunbuttontogenerateanoutput.
8.4
CROSSPOINT_SWITCH
Figure45.Crosspointswitch,usedtocontroltheconnectionbetweeninputandoutputsignals
TheCROSSPOINT_SWITCHdeviceisaconfigurablesignal switchinginstrumentwhichprovidesanefficientmeansby whichtoswitchsignalsinadesign. Theinterconnectionbetweeninputandoutputblocksis completelyconfigurable.Initialconnectionscanbedefinedas partofdesigntimeconfiguration,butcanbechangedonthe flyatruntime,fromthedevice'sassociatedinstrumentpanel. Thelatterenablesyoutoswitchsignalswithouthavingtore synthesizeanddownloadtheentiredesigntotheFPGA.
U18 CrosspointSwitch AIN_A[7..0] AOUT_A[7..0] AIN_B[7..0] AOUT_B[7..0] BIN_A[7..0] BIN_B[7..0] CROSSPOINT_SWITCH BOUT_A[7..0] BOUT_B[7..0]
8.5
FRQCNT2
Figure46.Frequencycounter,usedtomeasurefrequencyinthedesign
U6 FREQA FREQB TIMEBASE FrequencyCounter FRQCNT2
Thefrequencycounterisadualinputcounterthatcandisplaythe measuredsignalin3differentmodesasafrequency,period,ornumberof pulses.
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8.6
IOB_x
Figure47.DigitalIOmodule,usedtomonitorandcontrolnodesinthedesign
ThedigitalI/Oisageneralpurposetoolthatcanbeusedfor bothmonitoringandactivatingnodesinthecircuit.Itis availableineither8bitwideor16bitwidevariants,with1to 4channels. EachinputbitpresentsasaLED,andthesetof8or16bits alsopresentsasaHEXvalue.Outputscanbesetorcleared individuallybyclickingtheappropriatebitintheOutputsdisplay.AlternativelytypinginanewHEX valueintheHEXfieldcanaltertheentirebyteorword.IfaHEXvalueisenteredyoumustclickthe buttontooutputit.TheSynchronizebuttoncanbeusedtotransferthecurrentinputvaluetothe outputs.
8.7
DIGITAL_IO
Figure48.ConfigurableDigitalIOmodule,usedtomonitorandcontrolnodesinthedesign
TheconfigurabledigitalI/Oisageneralpurposetoolthatcanbe usedforbothmonitoringandactivatingnodesinthecircuit. Unlikeitslegacycounterparts(IOB_xfamilyofdevices),withthe DIGITAL_IOdeviceyouarenotconstrainedtolimitedsignalsof 8or16bits.Instead,anynumberofsignalsmaybeadded,and anynumberofbitscanbeassignedtoasinglesignal.Youmay alsohavedifferentnumbersofinputandoutputsignals.
ConfigurableDigitalIO InLEDs[7..0] Rot[7..0] SpareOutB[7..0] Zoom[7..0] SpareOutC[7..0] Flags[7..0] SpareOutD[7..0]
EachinputbitcanbepresentedinarangeofdifferentstylesincludingLEDs,numeric,LEDdigits,or asabar,andthesetofbitsalsopresentsasaHEXvalue.Outputstylescanalsovaryandinclude LEDs,numeric,LEDdigits,andaslider.EachoutputcanhaveapredefinedInitialValueandwill alsoincludeaHEXdisplay.Outputscanbesetorclearedindividuallyandthemethodwillvarywith thestyleselected.AlternativelytypinginanewHEXvalueintheHEXfieldcanalterthevalueofthe output.IfaHEXvalueisenteredyoumustclickthe buttontooutputit.TheSynchronizebutton canbeusedtotransferthecurrentinputvaluetotheoutputs.
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8.8
LAX_x
Figure49.Thelogicanalyzerinstrumentatthetop,withtwovariationsoftheconfigurableLAXshownbelowit. TheLAXcomponentonthelefthasbeenconfiguredtoaccept3differentsetsof64signals(signalsets),the oneontherighthasonesignalsetof16bits.TheConfiguredialogisusedtosetthecapturewidth,memory sizeandthesignalsets.
Thelogicanalyzerallowsyoutocapturemultiplesnapshotsofmultiplenodesinyourdesign.Use theLAXtomonitormultiplenetsinthedesignanddisplaytheresultsasadigitalorananalog waveform. TheLAXisaconfigurablecomponent.Configureittosimultaneouslycapture8,16,31or64bits. Thenumberofcapturesnapshotsisdefinedbytheamountofcapturememorythisrangesfrom1K to4Kofinternalstoragememory(usinginternalFPGAmemoryresources).Itcanalsobeconfigured touseexternalmemory.ThisrequiresyoutowireittoFPGAmemoryresourcesortooffchip memory(e.g.DesktopNanoBoardMemory). AfterplacingtheconfigurableLAXfromthelibrary,rightclickonthesymbolandselectConfigure fromthefloatingmenutoopentheConfigure(logicanalyzer)dialog,whereyoucandefinethe Capturewidth,memorysizeandthesignalsets. TheConfigurableLAXincludesaninternalmultiplexer,thisallowsyoutoswitchfromonesignalset toanotheratruntime,displayingthecapturedataofinterest.Youcanalsotriggeroffonesignalset whileobservingtheresultsofanotherset. NotethattheFPGAInstrumentslibraryincludesanumberofLAXcomponents.TheLAX componentistheconfigurableversion,allothersarelegacyversions. 129
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8.8.1 Waveformdisplayfeatures
Figure50.Digitalwaveformcaptureresultsfromthelogicanalyzer
Figure51.Analogwaveformcaptureresultsfromthelogicanalyzer
Thecaptureresultsaredisplayedintheinstrumentpanel.Therearealsotwowaveformdisplay modes.Thefirstisadigitalmode,whereeachcapturebitisdisplayedasaseparatewaveformand thecaptureeventsdefinethetimeline.Notethatthecaptureclockmustbesetinthelogicanalyzer optionsforthetimelinetobecalculatedcorrectly.ClicktheShowDigitalWavesbuttontodisplay thedigitalwaveform. Thesecondwaveformmodeisananalogmode,wherethevalueonallthelogicanalyzerinputsis displayedasavoltage,foreachcaptureevent.Thevoltagerangeisfromzerotothemaximum possiblecountvalue,scaledtoadefaultof3.3V.ClicktheShowAnalogWavesbuttontodisplay theanalogwaveform.
8.8.2 Zoominginandout
InboththeanaloganddigitalwaveformviewersitispossibletozoominandoutbyhittingthePage UporPageDownkeysrespectively
8.8.3 Continuousdisplaymode
Waveformscapturedbythelogicanalyzercanbedisplayedasasinglepassorasacontinuously updateddisplay.Continuousupdatescanbeenabled/disabledfromthelogicanalyzertoolbar.
Figure52.Enablingthecontinuouscapturemode.
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8.9
TerminalConsole
Figure53.Terminalconsoleinstrumentrackfunctionsasadebugconsoleforembeddedapplications.
TheTERMINALdeviceisadebugconsolewhichallowsyoutotypetext directlyinitsassociatedinstrumentpanelandsenditdirectlytothe processorinyourdesign,tobehandledbytheembeddedsoftwarecode runningtherein.Conversely,itallowsthedisplayoftextsentfromthat processor. AlthoughclassedasoneofAltiumDesigner'svirtual instruments,theTERMINALdeviceisreallyahybrid partinstrumentand partWishbonecompliantslaveperipheral.Whereasotherinstrumentsare configuredandoperateddirectlyfromaGUI,theTERMINALdevice requiresinteractionatthecodelevel,toinitializeinternalregistersandto writeto/readfromitsinternalstoragebuffers.
U1 TerminalConsole STB_I CYC_I ACK_O ADR_I[3..0] DAT_O[7..0] DAT_I[7..0] WE_I CLK_I RST_I INT_O[1..0] TERMINAL
8.10
Exercise4AUsingembeddedinstruments
AworkingdesignofaPWMcircuitcompletewithembeddedinstrumentshasbeenpreparedto illustratethefeaturesofFPGAinstruments.Yourinstructorwilltellyouwheretofinditonyourlocal harddrive.

U5 CLK_BRD CLK_BRD CLK_BRD CLK_TICK IA[7..0] O[15..0] IB[7..0] U7 CLK_BRD TIMEBASE FREQ U1 VCC CB8CEB Q[7..0] CLK_TICK CE C CEO TC CLR U3 U2 TEST_BUTTON INV U8 AIN[7..0] AOUT[7..0] A[7..0] B[7..0] COMPM8B GT LT I0 U4 O[7..0] I1 I2 I3 I4 I5 I6 I7 J8S_8B GND CLK_TICK CLK_BRD U9 FREQA FREQB TIMEBASE FrequencyCounter FRQCNT2 LEDS[7..0] U6 TRIGGER J8B2_16B LogicAnalyser LAX_1K16 CLK CLK_CAP CHANNELS[15..0] STATUS
FrequencyGenerator CLKGEN
1Chx8BitDigitalIO IOB_1X8
JTAG_NEXUS_TDI JTAG_NEXUS_TDO JTAG_NEXUS_TCK JTAG_NEXUS_TMS VCC
TDI TDO TCK TMS TRST
J TAG J TAG J TAG J TAG J TAG J TAG
. . .
Figure54.PWMcircuitwithseveralembeddedinstrumentsconnected.
1. OpentheprovidedprojectanddownloadittoyourNanoBoard. 2. Followonyourowncircuitastheinstructordiscussesthevariousembeddedinstruments.
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3. DoubleclicktheNanoBoardiconintheDevicesViewtoopentheinstrumentrackforthe NanoBoardandsetitsclockfrequencyto50MHz.
Figure55.NanoBoardcontroller.
4. Openthefrequencygenerators instrumentpanel.Ifthetimebase indicatedinthewindownexttothe SetTimeBasebuttonisnot50 MHzthenpresstheSetTime Basebuttontoopenadialogbox thatwillenableyoutosetit correctly.TheRequire50/50 Dutycheckboxshouldbe checked. Thefrequencygeneratorshould besetto1MHzasindicatedin Figure.
Figure56.Counteroptionsdialog
Figure57.FrequencygeneratorPanel
5. Openthefrequencycounters instrumentpanel.Selectthe CounterOptionsbuttononthe frequencycountermoduleand makesuretheCounterTimeBase isalsosetto50MHz(thesameas theNanoBoardclockfrequency), asshowninFigure57.PressOK. UsetheModebuttonasnecessary oneachchannelofthefrequency countermoduletotogglethe displaymodebetweenfrequency, periodorcount.Youshouldgeta similardisplaytowhatisdepicted inFigure59.
Figure58.Counteroptionsdialog
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Figure59.Frequencycountercontrolpanel
6. OpentheDigitalIOBsinstrumentpanel.
Figure60.DigitalIOBinstrumentcontrolpanel
7. ModifytheOutputsoftheIOBmoduleandobservechangesintheLEDs. 8. Adjusttheoutputfrequencyofthefrequencygeneratormoduletoalowerfrequencytry1KHz. ObservetheimpactthishasontheLEDs.ModifytheOutputsoftheIOBandobservefurther changesintheLEDs. 9. Adjusttheoutputfrequencyofthefrequencygeneratormodulebackto1MHz. 10. Openthelogicanalysersinstrumentcontrolpanel.
Figure61.Logicanalyserinstrumentcontrolpanel
11. SelectShowPanelonthelogicanalyzer.SetthepanelupasdepictedinFigure62.
Figure62.Logicanalysertriggeringoptions.
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12. SelectOptionsonthelogic analyser.Settheclockcapture frequencyto1MHzthesameas thefrequencygeneratormodule. Adjusttheothercontrolstobethe sameasshowninFigure63. 13. SelectArmandobservethe waveformdisplayedinthewaveform viewer.SelectContinuousCapture fromtheLogicAnalyzermenuand adjusttheIOBoutput.Observethe changeinthePWMmarktospace ratio.
Figure63.Logicanalysersetupoptions.
Figure64.Logicanalyzerwaveformwithbit7oftheIOBset.
Figure65.Logicanalyzerwaveformwithbits6&7oftheIOBset.
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8.11
WherearetheInstruments?
TheimportantdifferentiatorbetweenAltiumDesignersembeddedinstrumentsandothersimulation basedvirtualinstrumentsisthatAltiumDesignersembeddedinstrumentsaretruephysicaldevices thataredownloadedintotheFPGAdeviceaspartofthedesign.Theinformationprovidedtothe designerbytheembeddedinstrumentscanberelieduponasitistakenfromrealphysical measurementstakenonchip. FigureillustratesthispointasitshowstheFPGArealestateusedbytheembeddedinstruments.
Figure66.FloorplanofMyPWM.SchDocafterithasbeenplacedontoanFPGA.
8.12
Enablingembeddedinstruments
TheNanoBoardhardwareincorporatestheentireinfrastructurenecessarytosupportEmbedded InstrumentsandallowthemtocommunicatewiththehostPC.Allvirtualinstrumentscommunicate withthehostPCviaasoftJTAGchainthatconformstotheNexusstandard.ToenableNexuson theNanoBoard,theNEXUS_JTAG_PORTandNEXUS_JTAG_CONNECTORmustbeplacedontothe toplevelschematic.TheserespectivecomponentscanbefoundintheFPGAGeneric.IntLib andFPGANB2DSK01PortPlugin.IntLibIntegratedLibraries.
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NEXUS_JTAG_PORT
JTAG JTAG JTAG JTAG JTAG JTAG
NEXUS_JTAG_CONNECTOR JTAG_NEXUS_TDI JTAG_NEXUS_TDO JTAG_NEXUS_TCK JTAG_NEXUS_TMS VCC
. . .
TDI TDO TCK TMS TRST
Figure67.NEXUSJTAGPortandNEXUSJTAGConnector.
Tobeabletouseembeddedinstrumentsincustomdesigns,itisnecessarytoreserve4devicepins fortheNEXUS_JTAG_CONNECTORandensurethatsufficientdeviceresourcesarepresentto accommodatethevirtualinstrumentsinthedevice.TheJTAGsoftchainandothercommunications chainspresentontheNanoBoardwillbediscussedfurtherinthenextsection.
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9 InteractingwiththeNanoBoard
9.1 Overview
TheNanoBoardispivotaltorapidembeddedsystemsdevelopmentwithAltiumDesigner.Itcontains arangeofperipheralsandexpansioncapabilitiestoallowittoadapttoabroadcrosssectionof embeddedprojects.Inthissectionwewilldiscusstheconceptsnecessaryforadesignertomake effectiveusetheNanoBoardspotential.
9.2
NanoBoardcommunications
TheNanoBoardcontains3primarycommunicationchannels.Acompleteunderstandingofthese channelsisnotnecessarytobeginusingthetoolsuitehoweveritmaybeofinteresttodevelopers keentomakeuseofAltiumDesignersdebuggingcapabilitiesontheirowncustomdesigns. TheprimarypointofusercontroloftheNanoBoardisviatheDevicesView.Thisviewprovidesan easytousevisualizationofthevariouscommunicationschainsactiveontheNanoBoard.
NanoTalk Chain
JTAG Hard Chain
JTAG Soft Chain
Figure68.Devicesviewwithitsvariouscommunicationschannelshighlighted.
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9.2.1 NanoTalkchain
NanoTalkistheproprietarycommunicationsprotocoldevelopedbyAltiumtoenablemultiple NanoBoardstocommunicatewithoneanother.The10pinNanoTalkheaderscanbefoundonboth theleftandrightedgesattheupperendoftheDesktopNanoBoard.Communicationsviathis channelistotallytransparenttotheuser.Thereshouldbenoneedtointeractwiththisstandard.
9.2.2 JTAGHardChain
TheJTAGHardChainisaserialcommunicationschannelthatconnectsphysicaldevicestogether. JTAGdevicescanbeconnectedendonendbyconnectingtheTDOpinofanupstreamdeviceto theTDIpinofadownstreamdevice.ThehardJTAGchainisvisibleinthemiddleportionofthe DevicesView.UsuallythisiswhereanFPGAwillbelocatedhoweverifyoualsohaveother devicesthatareconnectedtotheJTAGchainsuchasaconfigurationdevicethenthesewillbe visiblealso. ThehardJTAGchaincanbeextendedbeyondtheNanoBoardthroughtheUserBoardAandUser BoardBconnectors.Whenusingeitheroftheseconnectors,itisimperativethattheJTAGchainis notbrokeni.e.theTDI/TDOchainmustbeloopedbacktotheNanoBoard.
9.2.3 JTAGSoftChain
TheJTAGSoftChainisaseparateJTAGchannelthatprovidescommunicationwiththeEmbedded InstrumentsthatcanbeincorporatedintoanFPGAdesign.Thischainislabeledasasoftchain sinceitdoesnotconnecttangiblephysicaldevicestogetherbutratherconnectssoftordownloadable instrumentsthatresideinsideahardorphysicalFPGAdevice.
9.3
Technicalbackground
TD DI T I
Parallel P r le a al Data Flow D t Fo a l
JT G TA J AG Cel el C ll
TD DO T O
Figure69.ConceptualViewofJTAGdataflows.
9.3.1 JTAGindepth
TheacronymJTAGstandsforJointTestApplicationGroupandissynonymouswithIEEE1149.1. ThestandarddefinesaTestAccessPort(TAP),boundaryscanarchitectureandcommunications protocolthatallowsautomatedtestequipmenttointeractwithhardwaredevices.Essentiallyit enablesyoutoplaceadeviceintoatestmodeandthencontrolthestateofeachofthedevicespins orrunabuiltinselftestonthatdevice.TheflexibilityoftheJTAGstandardhasalsoleadtoits usageinprogramming(configuring)devicessuchasFPGAsandmicroprocessors. Atminimum,JTAGrequiresthatthefollowingpinsaredefinedonaJTAGdevice: TCK:TestClockInput TMS:TestModeSelect
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TDI:TestDataInput TDO:TestDataOutput TCKcontrolsthedatarateofdatabeingclockedintoandoutofthedevice.ArisingTCKedgeis usedbythedevicetosampleincomingdataonitsTDIpinandbythehosttosampleoutgoingdata onthedevicesTDOpin.
Figure70.UsingJTAGChaintoconnectmultipleJTAGdevicestogetherinadigitaldesign.
Figure70.JTAGTestAccessPort(TAP)StateMachine.
TheTestAccessPort(TAP)Controllerisastatemachinethatcontrolsaccesstotwointernal registerstheInstructionRegister(IR)andtheDataRegister(DR).DatafedintothedeviceviaTDI oroutofthedeviceviaTDOcanonlyeveraccessoneofthesetworegistersatanygiventime.The registerbeingaccessedisdeterminedbywhichstatetheTAPcontrollerisin.Traversalthroughthe TAPcontrollerstatemachineisgovernedbyTMS. 139
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9.3.2 Nexus5001
TheflexibilityofJTAGforhardwaredebuggingpurposeshasflowedoverintothesoftwaredomain. Inthesamewaythattestengineershavesoughtastandardizedmethodfortestingsilicon,software engineershavealsosoughtastandardizedmeansfordebuggingtheirprograms. In1998,theGlobalEmbeddedDebugInterfaceStandard(GEDIS)Consortiumwasformed.Inlate 1999thegroupmovedoperationsintotheIEEEISTOandchangedtheirnametotheNexus5001 ForumandreleasedV1.0ofIEEEISTO1999.InDecember2003,V2.0wasreleased. TheNexus5001standardprovidesastandardizedmechanismfordebugtoolstointeractwithtarget systemsandperformtypicaldebuggingoperationssuchassettingbreakpointsandanalyzing variables,etc.Thereare4classesofNexuscomplianceeachwithdifferinglevelsofsupported functionality.ThelowestlevelusesJTAGasthelowlevelcommunicationsconduit. TheimplementationofNexus5001ontheDesktopNanoBoardhasbeenlabeledastheJTAGSoft Chain.Itisaserialchainjustlikethehardchainhoweverratherthanconnectingphysicaldevices together,itconnectsvirtualdevicestogether.Thesedevicesincludethesetofvirtualinstruments thataresuppliedwithAltiumDesigneranddescribedinthefollowingchapter.Controlofdeviceson theSoftChaincanbeperformedfromtheDevicesViewSoftChainDevicesarelocatedtowards thebottomoftheDevicesViewundertheHardChain. AswiththeJTAGHardChain,theSoftChaincanbetakenofftheNanoBoardviatheUserBoardA andUserBoardBconnectors.Thisprovidesthemeansfortargetsystemstoalsoincludevirtual instrumentsandtobenefitfromtheAltiumDesignerdevelopmentenvironment.SimilarlytotheHard Chain,itisimperativethatacompleteloopbemaintainedbetweentheSoftChainTDIandTDO connections.
9.4
TheNanoBoardcontroller
TheNanoBoardControllercanbeaccessedbydoubleclickingontheNanoBoardiconinthe DevicesView.
Figure71.TheNanoBoardControllerInstrumentRack.
TheClockFrequencyindicatedinthewindowwillbesuppliedtothe CLK_BRDportontheNanoBoard.Accessingthisclockoncustomdesignsis assimpleasplacingtheCLOCK_BOARDcomponentfromtheFPGANB2DSK01Port Plugin.IntLibLibrary.

P182 P182 CLK_BRD
SelectinganonstandardfrequencyispossiblebyclickingtheOtherFrequencybutton.The NanoBoardclocksystememploysaseriallyprogrammableclocksource(partnumberICS30702) thatiscapableofsynthesizinganyclockfrequencybetween6and200MHz.Advancedaccessto theClockControlICregistersisavailablethroughtheClockControlOptionsbutton.Adatasheet forthisdeviceisavailablefromtheICSwebsitehttp://www.icst.com/products/pdf/ics3070102.pdf. AnonlineformusefulforcalculatingsettingsfortheclockcontrolICisalsoavailableat http://www.icst.com/products/ics307inputForm.html. TotherightoftheNanoBoardControllerisasectionwiththeheading FlashRAM.TheFPGABootbuttonaffordsthefacilitytostoreadaughter boardconfigurationfilethatwillgetautomaticallyloadedintothedaughter boardonpowerup.TheEmbeddedbuttonexposesmemorythatcanbe usedbytheuserapplicationtostorenonvolatleuserdata.The EmbeddedMemorydeviceisaccessibleviatheSERIALFMEMORYcomponentintheFPGA NB2DSK01PortPlugin.IntLibLibrary.
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9.5
FPGAI/Oview
TodisplaytheInstrumentrackforadevice,doubleclickonthedeviceintheJTAGHardchain. ClickingontheJTAGViewerPanelbuttonthenbringsuptheJTAGViewerPanel.
Figure72.TheHardDevicesinstrumentrack.
Figure73.TheFPGAI/OInstrumentRackandJTAGViewerPanel.
Thisinterfaceenablesthedevelopertoseeinrealtimetheflowofsignalsacrossthedevicespins. Thiscanbeparticularlyusefulwhenensuringthatsignalsarebeingcorrectlypropagatedtoandfrom thedevice. PlacingatickintheLiveUpdatecheckboxwillcausethedisplaytoupdateinrealtime. Alternatively,leavingtheLiveUpdatecheckboxclearandselectingtheupdateiconwillcause signalinformationtobelatchedtothedisplayandheld. CheckHideUnassignedI/OPinstoremoveclutterfromthedisplay. TheBSDLInformationdropdownlistshouldonlyneedtobeaccessedfordeviceswhichare unknowntoAltiumDesigner.Inthiscase,youwillneedtoprovidethelocationofthevendor suppliedBSDLfileforthedeviceyouareviewing. TheFPGAIOinstrumentrackisavailableforalldevicesontheJTAGHardChainincluding devicesonauserboardthatisconnectedtotheJTAGHardChain. 141
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9.6
Livecrossprobing
ProbedirectivescanbeplacedontheFPGA schematiconanyI/Onetandwillupdateinrealtime aslongastheHardDevicesInstrumentPanelis displayed.UsethePlaceDirectivesProbeto placeacrossprobeononeoftheI/Onets.

Figure74.UsingLiveCrossProbing.
9.7
1. 2. 3. 4. 5.
Exercise4BViewMyPWMontheNanoBoard
ReloadyourcircuitfromExercise3againandrunitontheNanoBoard. OpentheJTAGViewerPanel. ChecktheHideUnassignedI/OPinscheckboxandtheLiveUpdatecheckboxes. ObservethechangeinswitchstatesandLEDsasyoutoggletheNanoBoardDIPswitches. UsethePlaceDirectivesProbeoptiontoplaceaprobepointonthebusconnectedtothe DIPSwitches.ObservetheprobevalueastheDIPSwitchesarechangedontheNanoBoard.
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10 Creatingacorecomponent
10.1 Coreproject
AltiumDesignerprovidestheabilitytoencapsulateanentireFPGAcircuitintoasinglecomponent thatcanbeusedasabuildingblockinotherprojects.Theseselfcontainedblocksarecalledcore componentsandoffertheadvantageofdesignreuseanddesignsecurity.Corecomponentscanbe synthesizedforatargetFPGAandmadeavailabletootherswithoutexposingtheunderlyingIP. AcoreprojectisusedtocreateanFPGAcomponentthatmaybeusedmultipletimeswithinoneor acrossmanyFPGAprojects.Theoutputofacoreprojectbehavesinasimilarfashiontoalibrary componentinthatitbecomesanelementalunitthatisusedasacomponentinlargerdesigns. Acoreprojectisusefulwhenyouwishtomakesomefunctionalityavailabletoabroaduserbasebut youdonotwanttoexposetheIPusedtoimplementthefunctionality.
Figure75.UsingacorecomponentinanFPGAProject.
10.2
CreatingacorecomponentfromanFPGAproject
Itispossibletocreateacorecomponentfromscratchhoweveroftenwewishtocreateacore componentfromanexistingFPGAdesignorproject.Ineithercaseablankcoreprojectmustfirstbe created.IfthecorecomponentistobebasedonanexistingdesignthenuseProjectAdd ExistingtoProjecttoaddtherelevantVHDL,Verilogand/orschematicdocumentstotheproject. Ifthecorecomponentisbeingcreatedfromscratchthenitssourcedocumentswillneedtobe createdinthesamewaythatanFPGAprojectisbuilt.
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10.3
AwordaboutEDIF
EDIFisanacronymforElectronicDesignInterchangeFormat.Itwasoriginallydevelopedasa standardizedformatfortransferringintegratedcircuitdesigninformationbetweenvendortools. AltiumDesignercreatesEDIFfilesaspartofthesynthesisprocessandthesefilesarethenpassed tothevendorbackendtoolsforcompleteFPGAplaceandroute. AlthoughEDIFfilesconformtoastandard,theinformationwithinagivenEDIFfilemaycontain vendorspecificconstructs.EDIFfilescannot,thereforebeconsideredasvendorindependent. ItisalsoworthnotingthatalthoughEDIFfilesdooffersomeformofIPprotection,theyarereadable byhumansandcanbedecipheredwithlittleeffort.TheyshouldnotbereliedupontomaintainIP protection.
10.4
Settingupthecoreproject
OncethecoreprojecthasbeencreateditisimportanttomakeavailableitsEDIFmodelswhenyou eventuallypublishit.MakesuretheIncludemodelsinpublishedarchivecheckboxistickedinthe OptionstaboftheProjectOptionsdialog.
Figure76.Settingoptionsforacorecomponent.
YoumustnowspecifythefolderonyourharddiskthatyouwishtheEDIFmodelstobesavedinto. ThisfolderwillbesearchedalongwiththestandardsystemEDIFfolders(\AltiumDesigner 6\Library\EDIF)whenyousynthesizeanydesign.ItisgoodpracticetokeepEDIFmodelsgenerated fromcoreprojectsinasinglelocationforeasiersearching. Tospecifythelocationoftheuser presynthesizedmodelfolder,openthePreferencesdialog,andnavigatetoFPGA>Synthesis.
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Figure77. Specifyingthelocationofcorecomponentmodels.
10.5
Constrain/configure
TheconceptofconstraintfilesandconfigurationsiscentraltotheflexibilityofAltiumDesigner.They provideamechanismtoallowFPGAcircuitstobedevelopedindependentofthefinalphysical implementation.Ratherthanstoringdeviceandimplementationspecificdatasuchaspinallocations andelectricalpropertiesinthesourceVHDLorschematicdocuments,thisinformationisstoredin separatefilescalledConstraintfiles.ThisdecouplingofthelogicaldefinitionofanFPGAdesign fromitsphysicalimplementationallowsforquickandeasyretargetingofasingledesigntomultiple devicesandPCBlayouts. ThereareanumberofclassesofconfigurationinformationpertinenttodifferentaspectsofanFPGA project:
10.5.1 Deviceandboardconsiderations:
ThespecificFPGAdevicemustbeidentifiedandportsdefinedinthetoplevelFPGAdesignmustbe mappedtospecificpinnumbers.
10.5.2 Deviceresourceconsiderations:
Insomedesignsitmaybeadvantageoustomakeuseofvendorspecificresourcesthatareunique toagivenFPGAdevice.Someexamplesarehardwaremultiplicationunits,clockmultipliersand memoryresources.
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10.5.3 Projectordesignconsiderations:
Thiswouldincluderequirementswhichareassociatedwiththelogicofthedesign,aswellas constraintsonitstiming.Forexample,specifyingthataparticularlogicalportmustbeallocatedto globalclocknet,andmustbeabletorunatacertainspeed. Aconfigurationisasetofoneormoreconstraintfilesthatmustbeusedtotargetadesignfora specificoutput.Themigrationofadesignfromprototype,refinementandproductionwilloften involveseveralPCBiterationsandpossiblyevendifferentdevices.Inthiscase,aseparate configurationwouldbeusedtobringtogetherconstraintfileinformationforeachdesigniteration. Eachnewconfiguration(anditsassociatedconstraintfile(s)isstoredwiththeprojectandcanbe recalledatanytime. Tosummarize: Constraintfilesstoreimplementationspecificinformationsuchasdevicepinallocationsand electricalproperties. AConfigurationisagroupingofoneormoreconstraintfilesanddescribeshowtheFPGA projectshouldbebuilt.
10.6
Creatinganewconstraintfile
Whentargetingadesignforauserboard,itisoftennecessarytomanuallycreateatleastone constraintfile.Thisconstraintfilewouldincludeataminimumthedevicethatisbeingtargetedand mayincludeanynumberofadditionalconstraintsappropriateforthetargetPCB.Ascoresmay oftenbesynthesizedforanumberofpossibletargets,itisusefultodiscusstheprocessofmanually constrainingandconfiguringadesigninthecontextofcreatingcoreprojects. Beforeaconfigurationcanbebuilt,aconstraintfilemustexist.Constraintfileshavetheextension .Constraint.ConstraintfilesforusewiththeDesktopNanoBoardcanbefoundinthe\Program Files\AltiumDesigner6\Library\Fpga\directory.Ingeneralitisadvisabletotakeacopy ofthesefilesandstoreitinyourprojectdirectorybeforeaddingittotheproject.Thiswaytheproject iskeptselfcontainedandanyeditsyoumayinadvertentlymakewillnotaffectthesupplied constraintfile. Toaddyourown,newconstraintfile,rightclickontheprojectnameintheProjectspaneland selectAddNewToProjectConstraintFile. Anewblankconstraintfilewillappear.TospecifythetargetdeviceselectDesignAdd/Modify ConstraintPartandtheBrowsePhysicalDevicesdialogwillopen.
Figure78.TheBrowsePhysicalDevicesdialog,whereyouselectthetargetFPGA.
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Figure79.Basicconstraintfile.
Selectthevendor,family,deviceand temperature/speedgradesasdesiredandclick OK. Alinesimilartotheoneabovewillbe automaticallyinsertedintotheconstraintfile: Savetheconstraintfile.Typicallyitwouldbe namedtoreflectitsrole forexampleifthe targetdevicewasaXilinxSpartan3FPGA mountedonyourprojectPCByoumightcallit MyProject_Spartan3_1500.Constraint. Youwillnoticetheconstraintfilehasbeen addedtotheprojectunderthesettingstab.
Figure80.ProjectwithconstraintFile.
10.7
Creatingaconfiguration
Aspreviouslymentioned,configurationsgroupanumberofconstraintfilestogethertocreateasetof instructionsfortheFPGAbuildprocess.Todefineaconfiguration: RightclickontheprojectnameintheProjectspanelandselectConfigurationManager
Figure81.Specifyingaconfigurationusingtheconfigurationmanager.
Ifyouhavejustrecentlycreatedanewconstraintsfile,youwillseeitlistedundertheConstraint Filename.Existingconstraintfilesthatcurrentlyarentintheprojectcanbeaddedbyselecting theAddbuttonnexttotheConstraintFilestext. Todefineanewconfiguration,selecttheAddbuttonnexttotheConfigurationstext.Adialog willappearrequestingyoutoprovideanameforthenewconfiguration.Thenamecanbe arbitrarybutitishelpfulifitprovidessomeindicationastowhattheconfigurationis for.
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Havingdefinedthenewconfiguration,youmaynowassignconstraintfilestoitbytickingtheir associatedcheckbox.HerewehaveassignedtheconstraintfileMyConstraint_Spartan3_1500 totheTarget_XC3S1500configuration. ClickOKtosavetheconfiguration.
Figure82.Specifyingaconfigurationusingtheconfigurationmanager.
Althoughtheabovesimplisticexampleonlyhadoneconstraintfileandoneconfiguration,thepower ofconfigurationsreallybecomesapparentasthedesignmatures.Belowweseehowadesignhas beentargetedtomultipleplatforms:
Figure83.Exampleofaprojectwithmultipleconfigurationsdefined.
Configurationscanbeupdatedormodifiedasdesiredatanytimethroughouttheprojects developmentbyreturningtotheConfigurationManagerdialog.
10.8
Synthesize
Nowthatwehavedefinedaconfiguration wearereadytosynthesizethecoreforthe target. WiththetoplevelFPGAdocumentopen selectDesignSynthesize.Ifwehad definedmorethanoneconfigurationand wishedtosynthesizeallconfigurationsat oncewecouldselectDesign SynthesizeAllConfigurations. Ifyouhavenotalreadynominatedthe toplevelentity/configurationinthe SynthesistaboftheOptionsforCore Figure84.SpecifyinganFPGAprojectstopleveldocument. Project,theChooseTopleveldialogwill appear.EnterthecoreprojectnameorselectfromthedropdownlistandclickOKtocontinue. TheprojectwillbesynthesizedresultinginthegenerationofVHDLfilesfortheschematic,EDIF filesfortheschematicwiringandparts,andasynthesislogfile.Thesewillallbelocatedunder theGeneratedfolderintheprojectpanel. YouwillobservetheconfigurationnameinbracketsbesidetheGeneratedFolder.Hadwe synthesizedmorethanoneconfigurationthenaseparateGeneratedfolderwouldhaveappeared foreachofthedefinedconfigurations.
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Confirmthatthesynthesisprocesscompleted successfullybyobservingthesynthesislogfile. Alinetowardsthebottomofthereportshould indicatewhetheranyerrorswereencountered.
10.9
Publish
Nowwecanpublishthecoreproject.Thiswillzip together(archive)alltheEDIFfilesinthecore projectsProjectOutputsfolderandthencopythis totheuserEDIFmodelsfolderthatwasspecified earlier. SelectDesignPublish.Iftheerrormessage cannotfindworkingfolderappears,make sureyouhavesetuptheUsepresynthesized Figure85.Filesgeneratedaftersynthesizingthedesign modelfolderoptionintheFPGAPreferences dialog. ChecktheMessagespaneltoensurethedesignhasbeensuccessfullypublished. Savethecoreprojectfile.
10.10 Creatingacoreschematicsymbol
Thecoreprojecthasbeensuccessfullysynthesizedandpublished.Itwouldbepossibleatthispoint forotherpersonneltomakeuseofyourcorethroughaVHDLinstantiationprocess.Thiscanbea messyaffair.Afarsimpleroptionwouldbeforthemtouseaschematicsymbolthatislinkedtoyour coreandassociatedEDIFfiles.Todothis,weneedtocreateourownschematicsymbolfromthe corecomponent. WiththetoplevelFPGAdocumentopenselectDesignGenerateSymbol.
Figure86.Creatingacorecomponentsymbol.
ClickYeswhenyouareaskedifyouwanttocreateanewschematiclibrary.Apopupwillappear, whereyoucanspecifytheappearanceofthenewlygeneratedsymbol.Anewschematiclibrary (Schlib1.SchLib)willbeautomaticallycreatedandopenedtodisplaythegeneratedsymbol.By defaultthecomponentnamewilltakeonthesamenameasthecoreprojectname.
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Figure87.Specifyingcorecomponentoptions.
Fromwithinthelibraryeditor,selectthecomponentintheLibrarypanelandselecttheEdit button.TheLibraryComponentPropertiesdialogwillbedisplayed.Notethatseveral parametershavebeenaddedtoindicatewhichchildmodelsarerequiredtoberetrievedfromthe publishedEDIFzipfiles.
Figure88.Specifyingthepropertiesofthenewlycreatedcorecomponentsymbol.
ClickingontheEditPinsbuttonwillenablefurthermodificationofthepropertiesandappearance oftheschematicsymbol. Fromtheschematiclibraryeditor,adjustthesymbolpropertiesasappropriateandsavethe component.Savethelibrarybeforeexiting.
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Figure89.Editingthecorecomponentpins.
10.11 Usingacorecomponent
Whenacorecomponentissynthesizedandpublished,theEDIFmodelisarchivedintothelocation specifiedintheFPGAPreferencesdialog.Anyprojectthatsubsequentlyusesthecorecomponent mustensurethattheEDIFarchivecanbefoundwithinthesearchpath.Thesearchsequencefor EDIFmodelsis: $project_dir $user_edif\$vendor\$family $user_edif\$vendor $user_edif $system_edif\$vendor\$family $system_edif\$vendor $system_edif Notethatthesearchlocationsincludestheprojectdirectorywhichmakesitusefulifyouneedto transferthedesigntoanotherPCthatdoesnothavetheuserEDIFmodelslocationdefined. 151
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10.12 Exercise5CreateacorecomponentfromMyPWM
1. CreateanewcoreprojectandcallitMyPWMCore.PrjCor.Notethatthefilenamemustnothave spacesinit. 2. SettheIncludemodelsinpublishedarchivecheckboxintheProjectOptionsdialog. 3. InthePreferencesdialog,gotoFPGASynthesis,andselectanoutputpathforEDIFfiles. Thispathshouldnotincludeanyspaces. 4. AttachtheexistingMyPWM.SchDocthatyoucreatedaspartofexercise3. 5. CreateaprojectlevelconstraintfileandcallitMyPWMPrj.Constraint.Addthefollowingtothis constraintfile:
Record=Constraint|TargetKind=Port|TargetId=CLK_BRD|FPGA_CLOCK_PIN=True Record=Constraint|TargetKind=Port|TargetId=CLK_BRD|FPGA_CLOCK=True Record=Constraint|TargetKind=Port|TargetId=CLK_BRD|FPGA_CLOCK_FREQUENCY=50Mhz Figure90.UpdatestobemadetoMyPWMPrj.Constraintfile.
6. CreateaconstraintfileeachforanAlteraCycloneIIdeviceaswellasaXilinxSpartan3device. 7. Createaconfigurationthatlinkseachoftheindividualdeviceconstraintfileswiththeproject constraintfile. 8. Synthesizeallconfigurationsandpublishthedesign.ChecktheUserPresynthesizedmodel Folder(assetinStep3)usingwindowsexplorerandviewthedirectoriesthatarecreatedand theircontents. 9. CreateacoreschematicsymbolandsaveittothelibraryMyCoreLib.SchLib 10. CreateanewFPGAprojectandschematicthatmakesuseofyourPWMcoreandtestitonthe NanoBoard.
CLK_BRD
ON
U1 CLK_BRD LEDS[7..0] LEDS[7..0]
SW[7..0]
1 2 3 4 5 6 7 8
SW[7..0] TEST_BUTTON
TEST_BUTTON
MyPWMCore
Figure90.TestprojectusedtotestthefunctionofMyPWMCore.
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11 FPGAdesignsimulation
AltiumDesignersupportsbehavioralsimulationofVHDLdesigns.Thisisparticularlyusefulwhen verifyingthefunctionaloperationofdigitalcircuitspriortoimplementingtheminsideanFPGA.
11.1
Creatingatestbench
Beforesimulationcanbegin,aVHDLTestbenchfilemustbecreatedtodrivethesimulation session.Conceptually,theTestbenchstraddlestheDesignUnderTest(DUT)anddrivestheDUTs inputswhilstobservingitsoutputs. VHDLTestbench
DUT Inputs
DesignUnderTest(DUT)
DUT Outputs
Figure91.ConceptualviewofhowaVHDLtestbenchinteractswiththeDesignUnderTest(DUT).
AltiumDesignerprovidesaconvenientmethodforbuildingaVHDLTestbenchbasedontheinputs andoutputsofthenominatedDUT.Ashelltestbenchfilecanbeautomaticallycreatedbythe system. Openaschematicdocumentandselect ToolsConvertCreateVHDLTestbench fromthemenu. OpenaVHDLdocumentandselectDesignCreateVHDLTestbench. AnewVHDLdocumentwillbecreatedwiththeextension.VHDTSTandwillbeaddedtotheproject. WithintheTestbenchfilewillbeacommentinsertstimulushere.ByplacingVHDLcodeatthis pointyoucancontroltheoperationofthesimulationsession.Ataminimum,theTestbenchmustset alloftheDUTsinputstoaknownstate.IftheDUTrequiresaclockthenthattoomustbeprovided bytheTestbench.MostsimulationerrorsoccurasaresultoftheTestbenchfailingtoproperly initializetheinputsoftheDUT.
11.2
AssigningtheTestbenchDocument
OnceyouhavecreatedtheTestbenchfilebutbeforeasimulationcanbegin,AltiumDesignerneeds tobeformallytoldwhichVHDLdocumentintheprojectwillbeusedtodrivethesimulation.Select ProjectOptionsbyrightclickingontheFPGAprojectintheProjectspanelorusethemenuto selectProjectProjectOptionsSelecttheSimulationtabfromwithintheProjectOptionsdialog andselecttheappropriate TestbenchDocument fromthedropdownlist.
Figure9218.Specifyingthetestbenchdocument
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11.3
Initiatingasimulationsession
Asimulationsessioncanbeinitiatedby selectingSimulatorSimulatefromthe menuorbyclickingthesimulationbutton intheVHDLToolstoolbarwhilstaVHDL documentisactiveinthemainwindow.
11.4
Projectcompileorder
Whenyoufirstrunasimulationfromatestbench,AltiumDesignermayneedtoestablishthe compilationorderoftheVHDLdocuments.Whilstperformingthisprocess,youmayseeanerror appearintheMessagespanelwiththemessage:UnboundinstanceDUTofcomponentDonot beconcernedasthisisnormalwhenyoufirstrunasimulation.
Figure93.Messagespanel.
Afterabriefmoment,adialogmayappear promptingyoutospecifythetoplevel documentforsimulation(Figure94). Thecompilationorderoftheprojectcanbe changedatalatertimeifnecessaryby selectingProjectProjectOrder orbyright clickingontheFPGAprojectintheProjects panelandselectingProjectOrder.

Figure94.Choosingthetopleveldocument.
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11.5
Settingupthesimulation display
TheSimulationSignalsdialog(Figure95)is automaticallypresentedatthebeginningofa simulationoritcanbeaccessedviaSimulator Signals. TheWatchNameisthenameofthesignaldeclared insidetheblockofVHDLcode. SignalsmustbeEnabledinordertobeapartofthe simulation.Furthermore,iftheyneedtobe displayedaspartofthesimulationoutputthen ShowWavemustalsobeselected. TheWaveformviewer(Figure95)providesa visualizationofthestatusofeachofthedisplayed signals. Theicon nexttothebusnameindicatesabus signal.Clickingonthisiconwillexpandthebus intoitsindividualsignalsforcloserinspection. Thetimecursor(indicatedbythepurplevertical bar)canbedraggedalongthetimeaxisviathe mouse.Thecurrentpositionofthecursoris providedinthetimebaracrossthetopofthe display. Zoominginoroutisachievedbypressingthe PageUporPageDownkeysrespectively. Thedisplayformatoftheindividualsignalscan bealteredviathemenuitemToolsFormat andRadix. .
Figure9519.Specifyingsignalstodisplayinthe simulation.
Figure96.Thewaveformviewer
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11.6
Runninganddebuggingasimulation
Runningasimulationisreasonablystraightforwardwithallthe stepping/runningfunctionsthatyoumightwishtousebeing availablefromtheSimulatormenuortheVHDLToolstoolbar. RunForeverwillrunthesimulationindefinitelyuntilStopis pressed.ThiscommandisusedtorunaVHDLsimulationuntil therearenochangesoccurringinthesignalsenabledinthe simulation. UsetheRun(foratimestep)commandtorunthecurrent simulationforauserspecifiedperiodoftime(timestep). Runfor (thelasttimestep)willrunthesimulatorforthesame periodoftimeasspecifiedinthelastRuncommand. RuntoTimewillrunthesimulatortoanabsolutetime. Selectingatimepriortowherethesimulationhasalready simulatedtowillcausethesimulatortodonothing. RuntoCursorisusefulwhendebuggingVHDLsourceand willcausethesimulatortorununtilthedefinedcursorlocation isencounteredinasourceVHDLdocument.Thesimulatorwill simulateeverythinguptotheselectedline.Makesurethatthe Showexecutionpointoptionisenabled,intheDebugging OptionsregionoftheFPGASimulationDebuggerpageof thePreferencesdialog(Figure97). CustomStep(Runsimulationtothenextdebugpoint):This commandisusedtorunthecurrentsimulation,uptothenext executablelineofcodeinthesourceVHDLdocuments.The nextexecutablecodepointcanbeanywhereinthecodeand thereforethecommandcanbeconsideredtobestepping Figure97.Thesimulatormenu throughthecodeinparallel,ratherthanthesequentiallybased stepintoandstepovercommands. StepTime:Thiscommandisusedtorunthecurrentsimulation,executingcodeinthesource VHDLdocumentsuntiltimeincrementsi.e.alldeltatimeeventspriortothenexttimeincrement willbeexecuted. DeltaStep:Thiscommandisusedtorunthecurrentsimulationforasinglecycle,whichcanbe calledaDeltastep.ADeltastepcanbesosmallthatnochangeinrealtimeisseen. StepIntoenablestheusertosinglestepthroughtheexecutablelinesofcodeinthesource VHDLdocuments.Ifanyprocedures/functionsareencountered,steppingwillcontinueintothe calledprocedureorfunction. StepOverissimilartoStepIntoexceptthatifanyprocedures/functionsareencountered, steppingwillexecutetheentireprocedure/functionasasingleexecutablelineandwillnotstep intoit. Stopwillpausethesimulatoratitscurrentsimulationpoint.Apausedsimulationcancontinueto berunwithanyoftheabovecommands. Resetwillabortthecurrentsimulation,clearanywaveformsandresetthetimebackto0. Endterminatestheentiresimulationsession.Endedsimulationscannotberestartedotherthan byinitiatinganothersimulationsession.
156
FPGADesign
Figure98.Thesimulationdebuggeroptionsinthepreferencesdialog.
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FPGADesign
11.7
Exercise6CreateatestbenchandsimulateMyPWM
1. OpentheprojectyoucreatedinExercise2andmakeMyPWM.VHDtheactivedocument. 2. SelectDesignCreateVHDLTestbenchfromthemenu. Updatethetestbenchtobethe sameasthecodelistedinFigure99.
Figure99.TestbenchcodefortestingMyPWM
3. Updatethetestbenchdocument,toplevelentity/configurationandtoplevelarchitecture fieldsinthesimulationtaboftheProjectProjectOptionsdialog. 4. Compilethetestbenchdocumentandrectifyanyerrors. 5. RunthesimulationbyselectingSimulatorSimulate. 6. Runthesimulatorfor2us. 7. ObservethewaveformsforLEDS[0]andLEDS[1].Isitwhatyouexpect?Trychangingthe PWMperiodbychangingthevalueofSWinthetestbench.
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12 Review
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FPGADesignBasics

8.6 8.7 8.8 8.9 8.10 8.11 8.12 9

CoreTopics FPGA Project Creation FPGA Schematic Extensions

FPGABuild Process FPGAdesign builtand loadedonto NanoBoard

OutputisasingleFPGA Sourcecodeforaprogramthatwillexecute onasinglesoftcore

AnFPGAprojectshouldbeusedwhenthetargetisasingleFPGA.TheoutputofanFPGAproject willbeaconfigurationbitfilethatcanbeusedtoprogramanFPGA. ThesimplestwaytocreateaprojectisfromtheFilemenu(FileNewProject).

Hierarchicalnetandbusconnectivitybetweendocumentsobeysthestandardhierarchicalproject connectionbehavior,whereportsonthesubdocumentconnecttosheetentriesofthesamenamein thesheetsymbolthatrepresentsthatdocument,asshownbelow. 15

Typicallytherearealargenumber ofrelatednetsinadigitaldesign. Busescanplayanimportantrole inmanagingthesenets,andhelp presentthedesigninamore readableform.

4.5.3 Matchingbusesofdifferentwidthsusingthe JBtypebusjoiner

TheJBtypebusjoinerallowsyoutomatchnetsinbusesofdifferent mergeandsplitbuses widths.Itdoesthisvia2componentparameters,IndexAandIndexBthat mapfromonebusthroughtotheotherbus.TheseindicesmustbedefinedwhenyouuseaJB joiner.

ReadtheflowofnetsthroughaJBtypebusjoinerbymatchingfromthenetsintheattachedbus,to thefirstindexonthebusjoiner,tothesecondindexinthebusjoiner,tothenetsdefinedinthe secondbusnetlabel. LeftBusIndexAIndexBRightBus Therulesformatchingnetsateachofthepointsareasfollows:

IndexA9 IndexB9 ROMADDR9,thruto ADDR0 IndexA0 IndexB0 ROMADDR0

IndexA15 IndexB31 PORTB31,thruto IndexA0 IndexB0 PORTB16

IndexA15 IndexB31 PORTB31,thruto INPUTS15 IndexA0 IndexB16 PORTB16

IndexA15 IndexB31 PORTB0,thruto IndexA0 IndexB16 PORTB15

HardwareresourcesontheDesktopNanoBoardcanbeaccessedviatheuseofcomponentsfrom the\ProgramFiles\AltiumDesigner6\Library\Fpga\FPGANB2DSK01Port Plugin.IntLiblibrary.

ManyofthehardwareresourcespresentontheNanoBoardcomewithperipheralmodulesthatcan beincludedintheFPGAdesigntoeaseinterfacingtotheexternalport. Peripheralscanbeplacedfromthe\ProgramFiles\AltiumDesigner 6\Library\Fpga\FPGAPeripherals.IntLiblibrary.

InthisexercisewewillcreateourfirstFPGAdesign.Inordertocompletethistaskyouwillneedto usethefollowingcomponentsfromtheirrespectivelibraries: Component

FPGANB2DSK01PortPlugin.IntLib FPGANB2DSK01PortPlugin.IntLib FPGAGeneric.IntLib

DIPSWITCH LED CB8CEB

U3 A[7..0] B[7..0] COMPM8B

OpenanewFPGAProject.SaveitasMyPWM.PrjFpg AddanewschematictoyourprojectandsaveitasMyPWM.SchDoc PlaceandwirethecomponentstocreatethePulseWidthModulator UsingcomponentsfromthetwolibrariesFPGAGeneric.IntLibandFPGANanoBoard PortPlugin.IntLib,placeandwiretheschematicshowninFigure17.

U1 CB8CEB VCC CLK_BRD U2 TEST_BUTTON INV

Q[7..0] CE C CEO TC CLR U3 A[7..0] B[7..0] COMPM8B GT LT I0 I1 I2 I3 I4 I5 I6 I7 U4 O[7..0] LEDS[7..0]

ConstraintfilesforusewiththeNanoBoarddaughter/peripheralboardmodulescanbefoundinthe \ProgramFiles\AltiumDesigner6\Library\Fpgadirectory.Toprotectthesesystem filesfrominadvertentmodification,itisadvisabletomakethisdirectoryreadonly.

ThegroupingofmultipleconstraintsintoasingleconfigurationismanagedviatheConfiguration ManageraccessiblebyrightclickingtheFPGAprojectintheProjectspanelandselecting ConfigurationManagerfromthemenu.

ThiswillautomaticallyconfiguretheFPGAProjecttoincludetheconstraintfilesrequiredtotargetthe hardwareontheDesktopNanoboardandwilllaunchtheConfigurationManagerdialogforthe currentFPGAproject.

Constraintfileadditions/modificationscanbemadebymanuallyeditingtheconstraintfileorby usingtheDesignAdd/ModifyConstraint menu.

ThisconstraintwillensurethattheVendorFPGAtoolsroutetheCLK_BRDporttoaspecialized clockpinonthetargetdevice. Alternatively,theFPGA_PINNUM constraintcanbespecifiedtolocktheport toaspecificpinonthetargetdevice.

SelectingOKfromthedialogboxinFigure25willaddtheconstraintFPGA_PINNUM=P185tothe CLK_BRDportconstraint. AcompletelistofthesupportedconstraintsandtheirsyntaxcanbefoundinthedocumentTR0130 ConstraintFileReference.PDFlocatedundertheKnowledgeCenterorfromtheAltiumwebsite.

ClickOKtoclosethisdialogandtheHardJTAGChainshouldnowappearinthemain window.YoumaynoticethatanewSettingsfolderhasbeenaddedtotheproject.Inthis folderyouwillfindaConstraintFilesfolderwithallofthenewlyaddedconstraintfiles. Severalofthefileswillhaveashortcut symbol.

BuildinganFPGAprojectrequiresprocessingthroughanumberofstages.Navigationthroughthe buildprocessisaccomplishedviathefourstepscircledinFigure31.Thefunctionofeachstagewill beexplainedshortly.

Blue Orange Magenta Green

Clickingonthearrowiconwillforcethecurrentstageandallpriorstagestorunregardlessof whethertheyhaveruntocompletionpreviously.Selectingthisiconwillforceatotallycleanbuild evenifthedesignhasbeenpartiallybuilt.

Selectingthelabelregionwillrunthecurrentstageandanypreviousdependantstagesthatarenot uptodate.Thisisthequickestwaytobuildadesignasitonlybuildsthoseportionsofthedesign thatactuallyrequireit.

Selectingthedownarrowwillexposeadropdownlistofthevarioussubstagesforthecurrentbuild stage.ThestatusofthevarioussubstagesisindicatedbythecolorofthestatusLED.Wherea substagehasfailed,theassociatedreportfilecanbeexaminedtohelpdeterminethecauseofthe failure.

U6 FREQA FREQB TIMEBASE FrequencyCounter FRQCNT2

Thefrequencycounterisadualinputcounterthatcandisplaythe measuredsignalin3differentmodesasafrequency,period,ornumberof pulses.

ConfigurableDigitalIO InLEDs[7..0] Rot[7..0] SpareOutB[7..0] Zoom[7..0] SpareOutC[7..0] Flags[7..0] SpareOutD[7..0]

Figure49.Thelogicanalyzerinstrumentatthetop,withtwovariationsoftheconfigurableLAXshownbelowit. TheLAXcomponentonthelefthasbeenconfiguredtoaccept3differentsetsof64signals(signalsets),the oneontherighthasonesignalsetof16bits.TheConfiguredialogisusedtosetthecapturewidth,memory sizeandthesignalsets.

AworkingdesignofaPWMcircuitcompletewithembeddedinstrumentshasbeenpreparedto illustratethefeaturesofFPGAinstruments.Yourinstructorwilltellyouwheretofinditonyourlocal harddrive.

JTAG_NEXUS_TDI JTAG_NEXUS_TDO JTAG_NEXUS_TCK JTAG_NEXUS_TMS VCC

TDI TDO TCK TMS TRST

J TAG J TAG J TAG J TAG J TAG J TAG

NEXUS_JTAG_CONNECTOR JTAG_NEXUS_TDI JTAG_NEXUS_TDO JTAG_NEXUS_TCK JTAG_NEXUS_TMS VCC

TDI TDO TCK TMS TRST

JTAG Hard Chain

JTAG Soft Chain

Parallel P r le a al Data Flow D t Fo a l

TDI:TestDataInput TDO:TestDataOutput TCKcontrolsthedatarateofdatabeingclockedintoandoutofthedevice.ArisingTCKedgeis usedbythedevicetosampleincomingdataonitsTDIpinandbythehosttosampleoutgoingdata onthedevicesTDOpin.

TheClockFrequencyindicatedinthewindowwillbesuppliedtothe CLK_BRDportontheNanoBoard.Accessingthisclockoncustomdesignsis assimpleasplacingtheCLOCK_BOARDcomponentfromtheFPGANB2DSK01Port Plugin.IntLibLibrary.

ProbedirectivescanbeplacedontheFPGA schematiconanyI/Onetandwillupdateinrealtime aslongastheHardDevicesInstrumentPanelis displayed.UsethePlaceDirectivesProbeto placeacrossprobeononeoftheI/Onets.

OncethecoreprojecthasbeencreateditisimportanttomakeavailableitsEDIFmodelswhenyou eventuallypublishit.MakesuretheIncludemodelsinpublishedarchivecheckboxistickedinthe OptionstaboftheProjectOptionsdialog.

Aspreviouslymentioned,configurationsgroupanumberofconstraintfilestogethertocreateasetof instructionsfortheFPGAbuildprocess.Todefineaconfiguration: RightclickontheprojectnameintheProjectspanelandselectConfigurationManager

Havingdefinedthenewconfiguration,youmaynowassignconstraintfilestoitbytickingtheir associatedcheckbox.HerewehaveassignedtheconstraintfileMyConstraint_Spartan3_1500 totheTarget_XC3S1500configuration. ClickOKtosavetheconfiguration.

Althoughtheabovesimplisticexampleonlyhadoneconstraintfileandoneconfiguration,thepower ofconfigurationsreallybecomesapparentasthedesignmatures.Belowweseehowadesignhas beentargetedtomultipleplatforms:

Confirmthatthesynthesisprocesscompleted successfullybyobservingthesynthesislogfile. Alinetowardsthebottomofthereportshould indicatewhetheranyerrorswereencountered.

Fromwithinthelibraryeditor,selectthecomponentintheLibrarypanelandselecttheEdit button.TheLibraryComponentPropertiesdialogwillbedisplayed.Notethatseveral parametershavebeenaddedtoindicatewhichchildmodelsarerequiredtoberetrievedfromthe publishedEDIFzipfiles.

ClickingontheEditPinsbuttonwillenablefurthermodificationofthepropertiesandappearance oftheschematicsymbol. Fromtheschematiclibraryeditor,adjustthesymbolpropertiesasappropriateandsavethe component.Savethelibrarybeforeexiting.

U1 CLK_BRD LEDS[7..0] LEDS[7..0]

Beforesimulationcanbegin,aVHDLTestbenchfilemustbecreatedtodrivethesimulation session.Conceptually,theTestbenchstraddlestheDesignUnderTest(DUT)anddrivestheDUTs inputswhilstobservingitsoutputs. VHDLTestbench

Asimulationsessioncanbeinitiatedby selectingSimulatorSimulatefromthe menuorbyclickingthesimulationbutton intheVHDLToolstoolbarwhilstaVHDL documentisactiveinthemainwindow.

Whenyoufirstrunasimulationfromatestbench,AltiumDesignermayneedtoestablishthe compilationorderoftheVHDLdocuments.Whilstperformingthisprocess,youmayseeanerror appearintheMessagespanelwiththemessage:UnboundinstanceDUTofcomponentDonot beconcernedasthisisnormalwhenyoufirstrunasimulation.