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12, DECEMBER 2003

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A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC

Byung-Moo Min, Senior Member, IEEE, Peter Kim, Member, IEEE, Frederick W. Bowman, III, David M. Boisvert, Member, IEEE, and Arlo J. Aude, Member, IEEE

AbstractA 10-bit 80-MS/s analog-to-digital converter (ADC) with an area- and power-efficient architecture is described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is realized using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal polarity inverting (FSPI) technique addresses the drawback of the conventional amplifier sharing technique. A wide-swing wide-bandwidth telescopic amplifier and an early comparison technique with a constant delay circuit have been developed to further reduce power consumption. The ADC is implemented in a 0.18- m dual-gate-oxidation CMOS process technology, achieves 72.8-dBc spurious free dynamic range, 57.92-dBc signal-to-noise ratio, 9.29 effective number of bits (ENOB) for a 99-MHz input at full sampling rate, and consumes 69 mW from a 3-V supply. The ADC occupies 1.85 mm2 . Index TermsAnalog-to-digital conversion, early comparison scheme with constant delay circuit, low-power pipelined analog-to-digital conversion, opamp sharing technique.

I. INTRODUCTION IGH-SPEED medium-resolution analog-to-digital converters (ADCs) are important in a wide variety of commercial applications including data communications and image signal processing. In such applications, the reduction of power consumption associated with high-speed sampling and quantization is one key design issue in enhancing portability and battery operation. In general, pipelined ADCs have proven to be very efficient architectures for meeting the low power dissipation and high input bandwidth requirements of these applications. In a pipelined ADC, the sample-and-hold circuit and amplifier is used by the first stage to sample the high frequency input and also by the subsequent stages to sample the residue from the previous stage. This feature allows each stage of the pipeline to begin processing a new sample as soon as its residue is sampled by the following stage, and also allows all stages to operate concurrently, giving a throughput of one output sample per clock cycle. Thus, pipelined ADCs can operate at high sampling rates with high dynamic performance. In this paper, a 10-bit 80-MS/s ADC combines a number of design approaches to achieve very low power consumption

and high performance with a pipelined architecture. These techniques include sharing an amplifier between two successive pipeline stages to obtain an area- and power-efficient architecture. Using a high-bandwidth low-power telescopic amplifier, which exploits a wide-swing gain-boosting circuit and the high transconductance and relatively low gate capacitance of 0.18- m channel length devices in a dual-gate-oxidation (DGO) CMOS process technology. An early comparison scheme with high-precision current-controlled delay circuit shows much less sensitivity to the variation of power supply, process, and temperature. Each of these techniques are presented in terms of their motivation, principle of operation, and related design considerations. This paper is organized as follows. Section II reviews the pipelined ADC architecture, Section III describes the limits of the conventional amplifier sharing technique, while addressing how it can be improved, Section IV describes the design of the ADC including further power reduction techniques at the circuit design levels such as a low-power high-bandwidth telescopic amplifier, an early comparison scheme with constant delay circuit, and a low-offset dynamic comparator, and Section V presents the experimental results and conclusion.

II. ARCHITECTURE REVIEW OF PIPELINED A/D CONVERSION A typical pipeline architecture uses a number of similar pipelined stages as shown in Fig. 1. All of these pipelined stages are similar in structure, consisting of a sample-and-hold amplifier (SHA), a digital-to-analog converter (DAC), and ADC. Each stage performs a coarse quantization, a DAC function on the quantization result, subtraction, and amplification of the remainder. Fig. 1 illustrates that these functions are implemented by a switched-capacitor (SC) circuit, with a bits per stage and an interstage gain of . resolution of The input signal is sampled on a set of capacitors of and simultaneously quantized into a per-stage resolution of bits through the ADC function. The DAC function is performed by charging/discharging a set of capacitors with a . Depending on the resolved reference voltage source bits, one of the capacitors is moved as a feedback capacitor of or the amplifier, while the others are connected to the source to perform the subtraction and amplification for the residue signal, which is passed to the next stage for more bits from all stages are combined fine conversion. Then,

Manuscript received April 11, 2003; revised July 14, 2003. B.-M. Min, P. Kim, and D. M. Boisvert are with National Semiconductor, Salem, NH 03079 USA (e-mail: byung-moo.min@nsc.com). A. J. Aude is with National Semiconductor, Norcross, GA 30071 USA. Digital Object Identifier 10.1109/JSSC.2003.819166

0018-9200/03$17.00 2003 IEEE

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Fig. 1.

Typical pipeline architecture implemented with an SC circuit.

to produce a full digital representation of the applied analog input. In an SC circuit with the single-pole operational amplifier (opamp) such as a common-source MOS amplifier, the closed-loop bandwidth (BW) is given by (1) is the transconductance of the opamp, is the where output load capacitance, and is the feedback factor. The feedback factor of the th stage SC circuit shown in Fig. 1 is given by (2) is the input capacitance of the opamp. The total where output load capacitance of the th stage is given by (3) is the total input capacitance of the comparator. where Based on these equations, decreasing the per-stage resolution is important if the speed of the SC circuit is a key design constraint. A smaller resolution gives a larger feedback factor and a lower load capacitance. Thus, the 1.5-bits/stage architecture has two benefits. The first is to maximize the bandwidth of the SC circuit, which limits the overall conversion rate. With a resolution of 1.5 bits/stage, the closed-loop gain of 2 allows for a low load capacitance and a large feedback factor, and as a result, a large interstage amplifier bandwidth can be achieved compared with architectures employing larger per-stage resolution. The second benefit is that a resolution of 1.5 bits/stage allows for a large correction range for comparator offsets in the flash ADC, where only two comparators are required for 1.5 bits/stage. Thus, comparator offsets up to can be tolerated without degradation of the overall linearity or signal-to-noise ratio (SNR) [1]. Compared with a conventional 1.5-bits/stage architecture, a multibit-per-stage architecture such as a 2.5-bits/stage ADC only needs half the number of opamps to implement a 10-bit ADC, but the drawback is that the feedback factor is reduced by about 50%, which requires a wider bandwidth opamp. Since the is proportional to the square root of the transconductance bias current of the amplifier, in order to maintain the feedback factor, the amplifier needs four times more bias current for the

same size transistor. Also, each stage needs both more accurate and a higher number of comparators (six comparators with digital error correction in the case of 2.5 bits/stage). Alternatively, the time-interleaving technique can be used to reduce the opamps bandwidth requirements at the cost of an increased number of channels. For example, by using two channels, the required operating frequency of the multiplying digital-to-analog converter (MDAC) is reduced to one half of that required in the conventional architecture, and the number of opamps is multiplied by two. The increased number of opamps can be reduced by sharing opamp across the two channels, using the well-known double sampling concept. However, these timeinterleaving methods need a very complex calibration scheme to correct offset mismatch, gain mismatch, and sample-time errors between time-interleaving channels in order to achieve 10-bit performance [2]. Instead of sharing an opamp across two channels, the amplifier sharing technique shares an opamp between two consecutive stages in the pipeline. This technique needs only half the number of opamps, while having the same bandwidth requirement and feedback factor as the conventional 1.5 bits/stage. Therefore, this amplifier sharing technique can be implemented with half the power consumption, but the drawback to this approach is that each opamp is always in the active mode. Hence, in this architecture, there is no time to reset the nonzero voltage due to the finite dc gain as well as the offset voltage of the opamps. Therefore, if the rest of the problem could be solved, the opamp sharing technique would be very competitive in achieving low-power consumption [3], [4]. Table I summarizes the comparison of these architectures for a low-power 10-bit 80-MS/s pipelined ADC. In this pipelined implementation, a 1.5-bits/stage architecture with an amplifier sharing technique has been chosen to achieve high-speed and low-power performance. III. AMPLIFIER SHARING TECHNIQUE Significant power reduction can be achieved by sharing an amplifier between successive stages in a pipelined ADC [3]. Amplifier sharing is motivated by the fact that in an SC architecture, the amplifier is used for only half of a clock cycle, which is during the amplification/integration phase. For example, in

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TABLE I COMPARISON OF LOW-POWER ARCHITECTURES FOR 10-bit 80-MS/s PIPELINED ADC

Fig. 2. Motivation of opamp sharing technique.

Fig. 2, gain stage is in the sampling mode. So, the opamp is in is the idle state or offset sampling mode, but the gain stage in the MDAC mode during the same clock phase, and the opamp is active in a closed feedback loop. Therefore, this opamp can be shared between these two consecutive pipeline stages by adding two more switch sets, which enables the opamp to commutate between these two SC networks. However, the amplifier sharing technique has two drawbacks [3]. First, the additional switches that are used to implement this technique introduce series resistance, which in combination with the amplifiers input capacitance affects the settling behavior of the stage. For higher conversion speeds, the switch resistance can be reduced by using larger switches at the expense of a potential increase in offset voltage due to charge injection and clock feedthrough. Second, the nonzero input voltage of the amplifier is never reset. Thus, every input sample is affected by the finite-gain error component from the previous sample. Also, ) noise and the opamps inerror voltages, including flicker ( trinsic offset voltage, cannot be cancelled because the amplifier is always in the active mode. In order to solve this problem, we propose a feedback signal polarity inverting (FSPI) technique between two sharing phases, as shown in Fig. 3. The sum of the combined errors mentioned above result in an at the output of the opamp that is added to the error signal residue signal as an output-referred offset voltage of the opamp. Therefore, in the 1.5-bit/stage architecture, the first and second and , are residue signals of the th sample, given by (4)

Fig. 3.

Opamp sharing (FSPI) technique.

(5) The output-referred offset voltages are composed of low frequency components compared with the ADC clock frequency, and thus, we can assume that it has similar value between two phases. Assuming

(6) but if the polarity of the first residue signal is inverted during the next phase, the error voltage of the first residue will be subtracted from that of the second residue, as follows:

(7) Therefore, with the proposed FSPI technique, the error voltage of the given opamp sharing stage can be reduced to one third of the conventional error voltage as shown by (6) and (7). Fig. 3

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Fig. 4.

Block diagram of the ADC.

shows how to implement this technique. During phase 1, the first residue signal of the opamp is sampled on the capacitors, and sample the negative output signal and where and sample the positive output signal of opamp A1. During and go into the positive feedphase 2, the capacitors and go into back path of the opamp A1 and capacitors the negative feedback path. In other words, during phase 1 or the first MDAC process, the output residue signal of opamp A1 is inversely sampled to capacitors of the next stage. Then, during the next phase, the negative residue signal goes to positive feedback path and the positive residue signal goes to negative feedback path. Thus, the polarity of the first stages output-referred offset voltage has been changed and subtracted from that of the second stage. The residue signal of second stage is sampled to through to further resolve the digital code. the capacitor IV. FURTHER POWER-REDUCTION TECHNIQUES Fig. 4 shows the overall SC pipelined ADC architecture. The wide-band low-noise SHA is capable of IF sampling up to sampling 200 MHz with low distortion by using constant switches, which are designed to observe device reliability considerations and use a bootstrapping circuit similar to previous work [5]. Also, the SHA allows for a wide input common-mode and feedback range by using a separate sampling capacitor . The opamp of the SHA forces the sampled signal capacitor to transfer to during the holding phase. charge on This SHA is followed by four 1.5-bit amplifier sharing blocks and a final 2-bit flash ADC. Each block consists of two consecutive stages sharing one amplifier and one clock-timing generator. Each sharing stage resolves four bits of digital output. The four bits from each the four sharing stages and the two bits from the flash are converted into a 10-bit code through the digital error correction logic block, which eliminates redundancy to compensate for the comparator offset errors [6]. With a large tolerance of 1.5 bits/stage, the comparator of each blocks ADC function uses a dynamic latch type to reduce power consumption. The capacitor sizes in the pipeline stages are minimized to reduce power consumption while balancing the thermal noise and matching requirements. In

Fig. 5. Scaling of pipeline stages.

order to achieve a maximum differential nonlinearity (DNL) with a given capacitor size, the ADC adopts the commutated feedback capacitor switching (CFCS) technique, which assigns the feedback capacitor depending on the resolved digital output at the decision point of code to reduce the error term of the comparator [4]. Also, in order to further reduce the power consumption, the scaling technique for the opamps and the capacitors is applied as shown in Fig. 5 [7]. The thermal noise margin of the SHA is the most important, so the sampling capacitance size of the SHA is chosen to give one bit more margin (65 dBc) to get more than 59-dBc SNR. Except for the SHA, the overall scaling characteristics is more speed limited than thermal-noise limited. In other words, all of the other capacitors are chosen to give a better feedback factor with a given opamp input gate capacitance. The scaling factor is about 0.7 between stages. Including the bias current for the input signal sampling common ground circuit, the total opamp power consumption is about 32 mW with a 3.0-V power supply. The SHA block consumes about 34% of that power. The ADC includes an on-chip precision bandgap reference voltage generator and buffer amplifiers to generate positive and . The clock generation of the ADC is implemented negative with five local clock generators in order to avoid any loss of clock period due to skews related to the layout. Each local clock generator is driven by a single master clock to coincide between stages, and the number of logic gates from the clock pin to the

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sampling switch clock is minimized to reduce clock skew and jitter. The master clock generator is located near the last stage in order to give a slight timing margin between pipeline stages, and so the last stage is driven first. In the following sections, circuit design techniques for further power minimization are described. A. Low-Power High-Bandwidth Opamp Using a single-stage telescopic amplifier can further enhance the above power advantage. In general, a telescopic amplifier offers excellent bandwidth with less power consumption at the cost of reduced signal swing range compared with other types of opamps. In this implementation, the conventional telescopic amplifier, shown in Fig. 6, has an improved dynamic range as differential well as bandwidth. First, in order to get a dynamic range with high dc gain on a 2.7-V supply, this opamp exploits a wide-swing gain-boosting technique for a pMOS cascode circuit. With this technique, instead of amplifying the voltage signal, the cascode current signal is amplified and converted into a voltage signal through a transimpedance amplifier. Then, the converted cascode voltage signal is applied to the gate of the pMOS cascode transistor. Thus, the static drainsource voltage of the pMOS current bias transistor can compared be reduced into the effective gatesource voltage of the conventional gain-boosting circuit. In with dynamic range as differential mode, it increases about for the output signal swing range. But the two times of drawback of the pMOS wide-swing gain-boosting circuit is that it slows down the settling times for large-signal transients compared with the simple cascode circuit. This is due to two reasons. First, the cascode current signal is processed through the pMOS transistor, which has a low transconductance. Also, the output of the gain-boosting circuit can slew to very different voltages from the required settling point, and take a while to return to the necessary voltages. In order to make this slow settling component fast enough, the unity-gain frequency of the added gain boosting circuit should be higher than the 3-dB bandwidth of the circuit, which is the closed-loop bandwidth of an SC circuit as shown in (1), and must be lower than the second-pole frequency of the main amplifier for reasons concerning stability [8]. Second, in order to enhance the closed-loop bandwidth, the input differential pairs use 0.18- m channel length devices which have about 3 times smaller gate capacitance than 3-V devices based on the same transconductance. For example, if two opamps are designed, one using 0.18- m devices and the other using 0.4- m devices, and if it is assumed that both opamps have similar bandwidths, then the resulting input capacitance of the 0.18- m opamp is three times smaller than that of the 0.4- m opamp. In the 1.5-bits/stage system, the becomes 1. Thus, feedback factor is given by (2), where the feedback factor of the 0.18- m opamp is about 1.4 times larger than that of the 0.4- m opamp. Based on (1), since the closed-loop bandwidth is proportional to the feedback factor, the proposed opamp can get higher bandwidths with a given bias current. Fig. 6 shows the proposed amplifier architecture. The nMOS inputs and the tail current source use 0.18- m channel length devices, which have lower threshold voltages

Fig. 6. Low-power high-bandwidth opamp.

and higher transconductances, but the pMOS transistors and all the other nMOS transistors use 0.4- m channel length devices in order to allow the maximum operating supply ranges up to 3.6 V. Simulations show that the proposed amplifier achieves about 80 phase margin, greater than 90-dB dc gain, and more than 1-GHz gain bandwidth for the range of 2.73.6-V supply, while output signal swing. The amplifier uses maintaining a an SC common-mode feedback circuit, which is implemented with one set of output holding capacitors and two sets of resetting capacitors. These resetting capacitors operate on both nonoverlap clock phases, like the ping-pong architecture enabling the opamp to maintain the output common-mode level with the amplifier sharing architecture. Also, the amplifier uses separate input and output common-mode levels. With a low input common-mode level, smaller transistors for the input sampling and the additional switches for the amplifier sharing technique can be used, which results in less charge injection on the virtual ground node of the opamp. B. Early Comparison Scheme With Constant Delay Circuit To allow for more settling time with reduced power consumption, the nonoverlap time between the two clock phases P1 and P2 is minimized together with a bottom-plate sampling technique to reduce charge injection. Due to this reduced nonoverlap time, this ADC uses an early comparison scheme in which the latch clock is enabled immediately after the amplifiers slew limited operation. Any comparison error due to insufficient settling or slew limiting can be recovered by the digital error correction just like a comparator offset voltage. However, even with the digital error correction, the comparator enable time should be placed precisely in order to give enough settling time from kickback noise of the comparator as well as to give enough opamp slew time, especially at high clock frequency. For this purpose, instead of a simple delay circuit using a CMOS inverter string, a bandgap current-controlled delay circuit is used to generate the comparator latch clock. Simulation results show

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Fig. 7. Constant delay clock generation.

Fig. 8.

Early comparison with constant delay clock.

the bandgap current controlled delay circuit is about ten times less sensitive to the variation of supply voltage, process, and temperature than the conventional delay circuit. Fig. 7 shows the delay clock generation scheme for the early comparison. The whole system is controlled from a precision source, and the bias current of the delay circuit is proportionally generated together with that of the opamp by the ratio of the current mirrors. This bias current is applied to the modified CMOS inverter string, which has a pMOS and an nMOS current bias transistor on each power supply rail. Thus, the comparator latch time can be always enabled right after the opamp slew time even with a clock-frequency-dependent power control system. For example, if the bias current of the opamp and the delay circuit is reduced at lower clock frequency, both the opamp slew time and the clock delay time are increased together to keep the comparator latch time right after the opamp slewing. Fig. 8 shows a simulation graph of the output of SHA block and the delayed clock, which illustrates the early comparison timing. Also, for the amplifier sharing, each clock phase has its own latch clock. C. Low-Offset Dynamic Comparator The 1.5-bits/stage architecture allows a large error correction range for the comparator offsets in the flash ADC of up . With a dynamic range in differential mode, to this redundant range is hundreds of millivolts, which allows the use of dynamic latch-type comparators without any preamplifier to cancel the offset voltage [1]. In order to reduce power consumption, a dynamic comparator as shown in Fig. 9 is used in this ADC.

The operating principle of the conventional comparator shown in Fig. 9(a) is as follows. When the latch clock goes high, and are turned on, and the gates of the transistors and are still at , where they are initially in the are saturation region. Then, assuming all transistors perfectly matched, the unequally sized cross-coupled differen and determine which of the outputs tial pairs and goes to or . After the latching of the outputs, the current paths are cut off, and the outputs are sustained to the falling edge of the latch clock. The drawback of this conventional comparator is that the input-referred and offset voltage is very sensitive to the matching of as well as that of the input differential pair transistors. The transistors are in the deep linear reason is because the and are in the saturation region at the region, whereas regeneration moment. Therefore, the transconductance of and is much higher than that of , which makes and one of the dominant factors in the matching of determining the outputs. Also, due to the low gain of the input pair transistors, the input-referred offset voltage is sensitive to and to the common-mode the device mismatching of mismatching between the input and reference signals. Therefore, in order to make a robust dynamic comparator insensitive to device and common-mode mismatches, all transistors should be in the saturation region at the rising edge of latch clock. For this purpose, the proposed comparator shown in Fig. 9(b) has and . When the latch clock included transistors are in the saturation mode, goes to high, all transistors and are in the linear region. Therefore, the whereas and becomes much less important, and mismatch of the input-referred offset voltage is mainly determined by the of input transistors deviation of the threshold voltage . In-house measurement results show about ten times better offset characteristics compared with the conventional scheme. Similar to the conventional dynamic comparator, the trip point of the proposed comparator is given by the ratio of for the 1.5-bit the input device widths and is set to conversion stage. V. EXPERIMENTAL RESULTS The ADC has been fabricated in a 0.18- m two-poly five-metal DGO CMOS process. The die photograph is shown in Fig. 10. The upper side shows the bandgap reference voltage generator and the reference buffer opamps, the center side has the SHA and the four opamp sharing stages, and the bottom shows the digital error correction logic block. The total active area excluding the PAD and ESD cells is about 1.85 mm , and the core area excluding the bandgap and buffer amplifiers is about 1 mm . The measured nonlinearity of the ADC is shown in Fig. 11. The integral nonlinearity (INL) is less than 0.5 LSB, and the DNL is less than 0.25 LSB. The slope of the INL at both edges is due to the limited dynamic range of the telescopic opamp. For the linearity test, a 500-kHz 0-dB full-scale sine wave with 80-MHz clock frequency was used. The measured output fast Fourier transform (FFT) spectrum with a 99-MHz input frequency at 80 MS/s is shown in Fig. 12. The measured SNR is about 58 dBc, the spurious free dynamic

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(a) Fig. 9. Dynamic comparator. (a) Conventional. (b) Proposed.

(b)

Fig. 10.

Die photograph. Fig. 12. Measured FFT spectrum.

Fig. 11.

Measured nonlinearity. Fig. 13. Dynamic performance versus input frequency.

range (SFDR) is about 73 dBc, the total harmonic distortion (THD) is about 68 dBc, and the effective number of bits (ENOB) is about 9.3. The total ADC power consumption on a 3-V supply is about 69 mW excluding the output drivers, which is about 0.85 pJ/conversion as an energy figure-of-merit unit. For this measurement, a clock crystal with 1-ps rms jitter characteristics has been used as a CMOS clock source. The measured dynamic performance versus input frequency is

shown in Fig. 13. The low input frequency shows more than 9.5 ENOB, and Nyquist rate input shows more than 9.4 ENOB. The overall dynamic performance is just a little degraded as the signal frequency is increased. The measured dynamic performance versus duty cycle with a Nyquist input frequency at 80 MS/s is shown in Fig. 14. The 30% duty cycle still

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using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal polarity inverting technique addresses the drawback of the conventional amplifier sharing technique. A wide-swing high-bandwidth telescopic amplifier, an early comparison scheme with a constant delay circuit, and a low-offset dynamic comparator have been developed to further reduce power consumption. The ADC, which occupies 1.85 mm and only consumes 69 mW at 80 MS/s, has been implemented in a 0.18- m DGO CMOS process technology. ACKNOWLEDGMENT
Fig. 14. Dynamic performance versus duty cycle.

This paper is dedicated to the memory of Frederick W. Bowman III for his passionate and novel layout works. The authors would like to thank S. Rao for the testing, E. Masse and R. Leboeuf for the PCB works, S. Mair for the product engineering of this ADC, and P. Holloway, P. Tucci, and L. Lewicki for their support. REFERENCES
[1] T. Cho and P. Gray, A 10 b, 20 Msample/s, 35 mW pipeline A/D converter, IEEE J. Solid-State Circuits, vol. 30, pp. 166172, Mar. 1995. [2] S. Jamal, D. Fu, N. Chang, P. Hurst, and S. Lewis, A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration, IEEE J. Solid-State Circuits, vol. 37, pp. 16181627, Dec. 2002. [3] K. Nagaraj, H. Fetterman, J. Anidjar, S. Lewis, and R. Renninger, A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers, IEEE J. Solid State Circuits, vol. 32, pp. 312320, Mar. 1997. [4] P. C. Yu and H. S. Lee, 2.5-V, 12-b, 5-Msamples/s pipelined CMOS ADC, IEEE J. Solid-State Circuits, vol. 31, pp. 18541861, Dec. 1996. [5] A. Abo and P. Gray, A 1.5 V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter, IEEE J. Solid-State Circuits, vol. 34, pp. 599605, May 1999. [6] S. Lewis, H. Fetterman, G. Gross, R. Ramachandran, and T. Viswanathan, A 10-b 20-Msample/s analog-to-digital converter, IEEE J. Solid-State Circuits, vol. 27, pp. 351358, Mar. 1992. [7] D. W. Cline and P. R. Gray, A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 m CMOS, IEEE J. SolidState Circuits, vol. 31, pp. 294303, Mar. 1996. [8] K. Bult and G. Geelen, A fast-settling CMOS opamp for SC circuits with 90-dB DC gain, IEEE J. Solid-State Circuits, vol. 25, pp. 13791384, Dec. 1990.

Fig. 15. Offset voltage of ADC.

shows more than 9.4 ENOB. A 50% duty cycle shows about 9.5 ENOB. A 70% duty cycle shows just above 9.0 ENOB, and starts to degrade. The reasons that 70% is worse than 30% is because the comparator enable time is placed just above the 70% duty cycle. As a result, the kickback noise starts to affect the settling behavior. The second reason is that the opamp sharing stage has less feedback factor due to the parasitic capacitance of the switches, so it requires a little longer settling time than the conventional SC circuit of the SHA block. The third reason is due to nonlinear settling behavior in the sampling capacitor of SHA due to the shorter clock phase. This 30%70% duty cycle is compatible with about a 135-MS/s conversion speed on each pipeline stage. The histogram of the measured offset voltage of the ADC is shown in Fig. 15. The total sample size is about 170, the measured average is about 1 mV, 1 sigma is about 5 mV, and the maximum offset is less than 1% FS. The measured offset voltage proves the effect of the proposed FSPI technique. VI. CONCLUSION A 10-bit 80-MS/s ADC with an area- and power-efficient architecture has been described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is realized

Byung-Moo Min (S96A00SM00) received the B.S. and M.S. degrees in electrical engineering and the Ph.D. degree in electronic engineering from Korea University, Seoul, Korea, in 1983, 1985, and 1997, respectively. From 1985 to 1999, he was a Senior Researcher with LG Semiconductor Inc., Seoul, where he was involved in the development of memory products, audio CODEC, LCD driver integrated circuits, and analog-to-digital converters. In 2000, he held a Postdoctoral position with the Electrical and Computer Engineering Department, Oregon State University, Corvallis, where he was involved in low-power switched-capacitor circuit design. Since January 2001, he has been with National Semiconductor, Salem, NH, as a Design Manager. He is currently responsible for the design of high-speed, high-resolution, and low-power CMOS analog-to-digital converters. He has about six referred publications and six patents in the area of analog circuits and analog-to-digital converters. Dr. Min has received several distinguished research awards, including a graduate fellowship to attend Korea University from LG Semiconductor Inc.

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Peter Kim (M03) was born in Inchon, Korea, in 1978. He received the B.S. and M.E. degrees in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 2000 and 2001, respectively. He did his Masters thesis through partnership with Analog Devices on high-voltage low-power 6- and 8-bit DACs for liquid crystal display driver applications. Since 2001, he has been a Design Engineer with National Semiconductors East Coast Laboratories, Salem, NH.

David M. Boisvert (M97) received the B.S.E.E. degree from the University of Massachusetts, Lowell, in 1984 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1986 and 1990, respectively. His doctoral research focused on the physics and technology of high-speed low-on-resistance power transistors. Before completing the Ph.D. degree, he worked with the Eastman Kodak Research Laboratories, Rochester, NY, where he focused on the development of advanced image sensors. In 1990, he returned to the Eastman Kodak Company where he developed analog front-ends for imaging applications. In 1994, he joined East Coast Laboratories, Salem, NH, a startup company focusing on low-power CMOS analog signal processing and analog-to-digital conversion which was acquired by National Semiconductor in 1996. He is currently a Design Director for National Semiconductor, Salem, focusing on analog front-ends and analog-to-digital converters for imaging and digital communication applications. He holds several patents in the areas of image sensor design, analog signal processing and analog-to-digital conversion, and has several patents pending. Dr. Boisvert has received several awards, including an undergraduate fellowship to attend the University of Massachusetts from the Massachusetts Board of Higher Education, and a graduate fellowship to attend Stanford University from the Eastman Kodak Company.

Frederick W. Bowman, III attended the University of Maine and studied computer science. He began his career as a Layout Designer with Analog Devices Inc., Wilmington, MA. He worked there for over 18 years, specializing in mixed-signal analog design. In October 1999, he joined National Semiconductor Corporation Data Conversion Systems, Salem, NH. He was admired both for the quality of his work and his technical expertise, which his coworkers and designers frequently drew on. He was also recognized many times at the corporate level, including receiving the ART Award in 2001 for best engineering practice in developing the ADC08200. He worked at National Semiconductor until he passed away suddenly on May 5, 2003. He will be greatly missed not only for his abilities, but for his friendliness, humor, and good nature.

Arlo J. Aude (M00) was born in Green Bay, WI, on February 11, 1973. He received the B.S. degree in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1995, with a specialization in analog design. In the same year, he also received certificates in social and industrial psychology. From 1992 to 1995, he interned at VansEvers Company, Tampa, FL, where he was involved in the research and design of vacuum tube audio amplifiers. He joined the Data Conversion group of Harris Semiconductor, Melbourne, FL, in 1996, where he was involved in the design and testing of high-speed analog-to-digital and digital-toanalog converters. In 1999, he joined the Wired Communications Group of National Semiconductor, where he is currently involved in the design of CMOS analog building blocks for use in high-speed communications systems. He currently holds five patents. Mr. Aude is a member of Psi Upsilon.