LIBRARY ieee;

USE ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;

ENTITY nco IS
-- Declarations
port ( clk : in std_logic;
reset : in std_logic;
din : in signed(11 downto 0);
dout : out signed(7 downto 0)
);
END nco ;
-- hds interface_end
ARCHITECTURE behavior OF nco IS
type vectype is array (0 to 256) of signed(7 downto 0);
-- ROM cosrom
constant cosrom : vectype := (
0 => "01111111",
1 => "01111111",
2 => "01111111",
3 => "01111111",
4 => "01111111",
5 => "01111111",
6 => "01111111",
7 => "01111111",
8 => "01111111",
9 => "01111111",
10 => "01111111",
11 => "01111111",
12 => "01111111",
13 => "01111111",
14 => "01111111",
15 => "01111111",
16 => "01111111",
17 => "01111111",
18 => "01111111",
19 => "01111111",
20 => "01111111",
21 => "01111111",
22 => "01111111",
23 => "01111111",
24 => "01111111",
25 => "01111110",
26 => "01111110",
27 => "01111110",
28 => "01111110",
29 => "01111110",
30 => "01111110",
31 => "01111110",
32 => "01111110",
33 => "01111101",
34 => "01111101",
35 => "01111101",
36 => "01111101",
37 => "01111101",
38 => "01111101",
39 => "01111100",

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"01111100",
"01111100",
"01111100",
"01111100",
"01111011",
"01111011",
"01111011",
"01111011",
"01111010",
"01111010",
"01111010",
"01111010",
"01111010",
"01111001",
"01111001",
"01111001",
"01111001",
"01111000",
"01111000",
"01111000",
"01110111",
"01110111",
"01110111",
"01110111",
"01110110",
"01110110",
"01110110",
"01110101",
"01110101",
"01110101",
"01110100",
"01110100",
"01110100",
"01110011",
"01110011",
"01110011",
"01110010",
"01110010",
"01110010",
"01110001",
"01110001",
"01110001",
"01110000",
"01110000",
"01101111",
"01101111",
"01101111",
"01101110",
"01101110",
"01101101",
"01101101",
"01101101",
"01101100",
"01101100",
"01101011",
"01101011",
"01101010",
"01101010",
"01101010",
"01101001",

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"01101001",
"01101000",
"01101000",
"01100111",
"01100111",
"01100110",
"01100110",
"01100101",
"01100101",
"01100100",
"01100100",
"01100011",
"01100011",
"01100010",
"01100010",
"01100001",
"01100001",
"01100000",
"01100000",
"01011111",
"01011111",
"01011110",
"01011110",
"01011101",
"01011101",
"01011100",
"01011100",
"01011011",
"01011011",
"01011010",
"01011001",
"01011001",
"01011000",
"01011000",
"01010111",
"01010111",
"01010110",
"01010101",
"01010101",
"01010100",
"01010100",
"01010011",
"01010010",
"01010010",
"01010001",
"01010001",
"01010000",
"01001111",
"01001111",
"01001110",
"01001110",
"01001101",
"01001100",
"01001100",
"01001011",
"01001010",
"01001010",
"01001001",
"01001000",
"01001000",

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"01000111",
"01000111",
"01000110",
"01000101",
"01000101",
"01000100",
"01000011",
"01000011",
"01000010",
"01000001",
"01000001",
"01000000",
"00111111",
"00111110",
"00111110",
"00111101",
"00111100",
"00111100",
"00111011",
"00111010",
"00111010",
"00111001",
"00111000",
"00111000",
"00110111",
"00110110",
"00110101",
"00110101",
"00110100",
"00110011",
"00110011",
"00110010",
"00110001",
"00110000",
"00110000",
"00101111",
"00101110",
"00101101",
"00101101",
"00101100",
"00101011",
"00101010",
"00101010",
"00101001",
"00101000",
"00100111",
"00100111",
"00100110",
"00100101",
"00100100",
"00100100",
"00100011",
"00100010",
"00100001",
"00100001",
"00100000",
"00011111",
"00011110",
"00011110",
"00011101",

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"00011100",
"00011011",
"00011011",
"00011010",
"00011001",
"00011000",
"00011000",
"00010111",
"00010110",
"00010101",
"00010100",
"00010100",
"00010011",
"00010010",
"00010001",
"00010001",
"00010000",
"00001111",
"00001110",
"00001101",
"00001101",
"00001100",
"00001011",
"00001010",
"00001010",
"00001001",
"00001000",
"00000111",
"00000110",
"00000110",
"00000101",
"00000100",
"00000011",
"00000010",
"00000010",
"00000001",
"00000000");

signal dtemp : unsigned(17 downto 0);

signal din_buf : signed(17 downto 0);
signal dtemp1 : integer;
constant offset : unsigned(17 downto 0) := "000100000000000000";
begin
process(CLK, RESET)
begin
if (RESET='1') then
dout <= (others => '0');
din_buf <= (others => '0');
dtemp <= (others => '0');
dtemp1 <= 0;
elsif rising_edge(CLK) then
din_buf <= din(11)&din(11)&din(11)&din(11)&din(11)&din(11)&di n;
dtemp <= dtemp + unsigned(din_buf) + offset;
dtemp1 <= to_integer(dtemp(17 downto 8));
if (dtemp1 >= 0) and (dtemp1 < 257) then
dout <= cosrom(dtemp1);
elsif (dtemp1 >= 257) and (dtemp1 < 513) then
dout <= -cosrom(512-dtemp1);

elsif (dtemp1 >= 513) and (dtemp1 < 769) then

dout <= -cosrom(dtemp1-512);
else
dout <= cosrom(1024-dtemp1);
end if;
end if;
end process;
END behavior;
[2] Numerical Controlled Oscillator (NCO)
Figure 3 explains NCO.
Figure 3. Numerical Controlled Oscillator (NCO)
In our target system, let's assume that system clock frequency is 16MHz = 16,000
,000MHz and center NCO operating frequency is 1MHz = 1,000,000MHz. Then as shown
in the figure 3, there are 16 sampling points in 1 cycle of 1MHz sinusoidal wav
e.
The NCO generates exactly 1 cycle of sinusoidal wave when input value = 0. Then
the offset value is 1/16. Every clock cycle, the D flipflop accumulates the offs
et value. Then, in 16 cycles, accumulated value will increase by 1.0. The accumu
lator output is multiplied by 2pai, then cosine value is extracted from the cos
ROM.
When the input value is more than 0, the accumulation speed gets higher. Then in
less than 16 cycles, the accumulator increases by 1.0. This corresponds to high
er frequency than 1.0MHz is generated. Vice versa, when the input value is less
than 0, lower frequency than 1.0MHz is generated. Consequently, the NCO operatin
g frequency will be controlled by the input value with center frequency of 1.0MH
z.