100 Watts Audio Digital Amplifier

100 WATTS AUDIO DIGITAL AMPLIFIER
SITI HAJAR BINTI HAZIZI
UNIVERSITI TEKNOLOGI MALAYSIA
PSZ 19:16 (Pind. 1/97)
UNIVERSITI TEKNOLOGI MALAYSIA
BORANG PENGESAHAN STATUS TESIS

JUDUL:
100 WATTS AUDIO DIGITAL AMPLIFIER SESI PENGAJIAN: 2007/2008
Saya
SITI HAJAR BINTI HAZIZI (HURUF BESAR)
mengaku membenarkan tesis (PSM / Sarjana / Doktor Falsafah)* ini disimpan di Perpustakaan Universiti Teknologi Malaysia dengan syarat-syarat kegunaan seperti berikut: 1. 2. 3. 4. Tesis adalah hakmilik Universiti Teknologi Malaysia. Perpustakaan Universiti Teknologi Malaysia dibenarkan membuat salinan untuk tujuan pengajian sahaja. Perpustakaan dibenarkan membuat salinan tesis ini sebagai bahan pertukaran antara institusi pengajian tinggi. **Sila tandakan ( ) SULIT TERHAD TIDAK TERHAD Disahkan oleh (Mengandungi maklumat yang berdarjah keselamatan atau kepentingan Malaysia seperti yang termaktub di dalam AKTA RAHSIA RASMI 1972) (Mengandungi maklumat TERHAD yang telah ditentukan oleh organisasi/badan di mana penyelidikan dijalankan)
(TANDATANGAN PENULIS) Alamat Tetap: NO 15, JALAN JAYA 1/7, TAMAN PAGOH JAYA,PANCHOR 84500 MUAR JOHOR D.T Tarikh: 5th DECEMBER 2007
(TANDATANGAN PENYELIA) PUAN ISMAWATI BT. ABDUL GHANI Nama Penyelia
Tarikh :
5th DCEMBER 2007
CATATAN: * Potong yang tidak berkenaan. **Jika tesis ini SULIT atau TERHAD, sila lampirkan surat daripada pihak berkuasa/organisasi berkenaan dengan menyatakan sekali sebab dan tempoh tesis ini perlu dikelaskan sebagai SULIT atau TERHAD. Tesis dimaksudkan sebagai tesis bagi Ijazah Doktor Falsafah dan Sarjana secara penyelidikan, atau disertai bagi pengajian secara kerja kursus dan penyelidikan atau Laporan Projek Sarjana Muda (PSM)..
I hereby declare that I have read this thesis and in my opinion this thesis is sufficient in terms of scope and quality for the award of the degree of Bachelor of Electrical (Electronics) Engineering
Signature Name of Supervisor Date .
: : :
.. PUAN ISMAWATI BINTI ABDUL GHANI 5th DECEMBER 2007
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100 WATTS AUDIO DIGITAL AMPLIFIER
SITI HAJAR BINTI HAZIZI
A thesis submitted in fulfillment of the requirements for the award of the degree of Bachelor in Electrical (Electronic) Engineering
Faculty of Electrical Engineering University Technology Malaysia
DIS 2007
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I declare that this thesis entitled 100 Watts Audio Digital Amplifier is my own original writing except the quotation and summaries that cited clearly in the references.
Signature Name Date
: ___________________________________ : SITI HAJAR BINTI HAZIZI : 5th DECEMBER 2007
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To my beloved father, Hazizi bin Arshad, who has given me enormous guidelines throughout my life. To my beloved mother, Norsiah binti Ibrahim, who has given me a lot of strength and support in completing this project. Also to my sisters, Siti Nuraishah and Siti Nabilah and my brother, Ismail, who, are always there to share my ups and downs of life.
ACKNOWLEDGEMENT
In preparing this thesis, I was in contact with many people. They have contributed towards my understanding and thoughts. In particular, I wish to express my sincere appreciation to my main thesis supervisor, Puan Ismawati Abdul Ghani, for the encouragement, guidance and critics. I would also like to take this opportunity to express my deepest grateful appreciation to my family members who have continuously giving me unlimited moral and spiritual encouragement and financial support throughout all my academic endeavors. I am also indebted to the staff of the Faculty of Electrical Engineering for their assistance in completing my project. My fellow undergraduate students should also be recognized for their support. My sincere appreciation also extends to all my colleagues and others who have provided assistance at various occasions. Their views and tips are useful indeed. Unfortunately, it is not possible to list all of them in this limited space but the most helpful persons in this project would be Mohd Effendy Idris, Mr. Takumi Suga, Nurhija Mahalin and Mohd Azli Mohamed.
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ABSTRACT
There are many classes of audio amplifiers. There are Class A, B, C, D and others classes have different characteristic. The purpose of this project is to develop an amplifier that will amplify weak signals and to remove unwanted signals within the audio frequency range. Class D audio amplifier is suitable to this project. The frequency range for an audio amplifier is between 20 Hz and 20 kHz. The main goals are to achieve 90% of efficiency with 100 watts as the output power.
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ABSTRAK
Seperti yang diketahui, terdapat pelbagai jenis penguat yang dikategorikan mengikut kelas. Antaranya ialah penguat Kelas A, B, C, D dan lain-lain. Kesemua jenis penguat ini mempunyai cirri yang berlainan. Tujuan projek ini dijalankan adalah untuk menghasilkan penguat yang akan menguatkan isyarat-isyarat yang lemah dan membuang isyarat-isyarat yang tidak diperlukan dalam julat frekuensi audio. Penguat kelas D adalah penguat yang sesuai digunakan di dalam projek ini. Had frekuensi bagi projek ini ialah 20 Hz hingga 20 kHz. Sasaran projek ialah untuk mendapatkan keluaran 100 watt.
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] TABLE OF CONTENTS
CHAPTER
TITLE
PAGE iii vi v vi vii viii xi xii xiv 1 1 5 5 6 7 5 8 9 10 11
DECLARATION DEDICATION ACKNOWLEDGEMENT ABSTRACT ABSTRAK TABLE OF CONTENTS LIST OF FIGURES LIST OF SYMBOLS AND ABBREVIATIONS LIST OF APPENDICES
INTRODUCTION 1.1 1.2 1.3 1.4 Introduction Objective Scope of Work Problem Statement
PROJECT OVERVIEW 2.1 Chip TDA8920BJ 2.1.1 Description 2.1.2 Mode Selection 2.1.3 Protection 2.2 Pulse Width Modulation
ix
2.3 2.4
Low Pass Filter Theoretical analysis of class D operation
13 15
METHODOLOGY 3.1 Research Methodology 3.2 Circuit and Hardware Design
17 17 18
RESULTS 4.1 4.2 4.4 4.5 4.6 Current Limiting Mode Selector Filter Output power estimation Output Power
20 20 21 22 23 26 27 28
4.3 Pulse Width Modulation frequency
4.7 Signal to Noise ratio
5 6
DISCUSSION CONCLUSION REFERENCES APPENDIX APPENDIX A GANTT CHART PSM 1 GANTT CHART PSM 2 APPENDIX B TDA8920BJ DATASHEET
30 31 32 33 33 33 34 35
LIST OF FIGURES
TABLE NO 1.1 1.2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.1 3.2 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11
TITLE Class D amplifier compares analog audio to triangle wave to create pulse modulation Class D Topology Block Diagram of the project. Mode select drive input circuit Mode select transfer characteristic Input Sine Wave vs. PWM Output Two-Level vs. Three-Level PWM PWM Comparator Amplitude Response of Butterworth Low Pass Filter Gain responses of Chebyshev Low Pass Filter Loop Filter Methodology for the Project Block diagram current limiting Mode switching in normal way Mode switching directly from standby-operating Oscillator Typical low pass filter Bode Plot for 1 Ohm load Bode Plot for 2 Ohm load Bode Plot for 4 Ohm load Bode Plot for 8 Ohm load Input vs. Output Waveform
PAGE 4 4 5 9 10 11 12 13 14 14 16 17 18 20 21 21 22 24 24 25 25 26 27 26
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LIST OF SYMBOLS AND ABBREVIATION
A C CMRR DC dB f F hZ k m M n R V L RMS Vpp SNR OSC
Gain Capacitor Common Mode Reject Ratio Direct Current Decibel Frequency Farad Herz kilo mili mega nano Resistor Voltage Ohm micro Inductor Root Mean Square value Voltage peak to peak Signal to Noise Ratio Oscillator
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LIST OF APPENDICES
APPENDIX A B
TITLE GANTT Chart PSM 1 and PSM 2 TDA8920BJ DATASHEET
PAGE 33 35
CHAPTER 1
INTRODUCTION
1.1 Introduction The term amplifier is very generic. In general, the purpose of an amplifier is to take an input signal and make it stronger (or in more technically correct terms, increase its amplitude). Amplifiers find application in all kinds of electronic devices designed to perform any number of functions. There are many different types of amplifiers, each with a specific purpose in mind. This project will focus on audio power amplifiers. Audio power amplifiers are those amplifiers which are designed to drive loudspeakers. Generally audio frequencies are between 20 Hz to 20 kHz. The preceding stages are low power audio amplifiers which perform tasks like preamplification, equalization, tone control, mixing / effects or audio sources like record players, CD players, Cassette players and so on. As we know, in the early audio amplifiers were based on vacuum tubes (also known as valves). Most modern audio amplifiers are based on solid state devices like transistors, FETs, and MOSFETs but there are still aficionados who prefer tube based amplifiers, as they have a warmer sound due to more linear V / I characteristic. Audio amplifiers based on transistors became practical with the appearance of cheap transistors in the late 1960s.
2 Audio power amplifiers are classified primally by the design of the output stage. Classification is based on the amount of time the output devices operate during each cycle of signal swing. The following is brief description of some of the more common amplifier classes.
Class A: Class A amplifiers have very low distortion (lowest distortion occurs when the volume is low) however they are very inefficient and are rarely used for high power designs. The distortion is low because the transistors in the amplifier are biased such that they are half "on" when the amplifier is idling (this is the point at which the semiconductor devices are most linear in behavior). As a result of being half on at idle, a lot of power is dissipated in the devices even when the amp has no music playing! Class A amps are often used for "signal" level circuits (where power requirements are small) because they maintain low distortion. High end Class A audio amplifiers are sometimes used by the most discriminating audiophiles. Distortion for class A amplifiers increases as the signal approaches clipping; as the signal is reaching the limits of voltage swing for the circuit. Some class A amplifiers have speakers connected via capacitive coupling.
Class B: Class B amplifiers are used in low cost designs or designs where sound quality is not that important. Class B amplifiers are significantly more efficient than class A amplifiers, however they suffer from bad distortion when the signal level is low (the distortion in this region of operation is called "crossover distortion"). Class B is used most often where economy of design is needed. Before the advent of IC amplifiers, class B amplifiers were common in clock radio circuits, pocket transistor radios, or other applications where quality of sound is not that critical. For example, a siren driver is one application of a Class B amplifier. Siren drivers are amplifiers that are basically driven into clipping (to produce a square wave type signal). In such a drive situation there would be little need to care about crossover distortion (the design can be less expensive due to reduced parts count).
Class AB: Class AB is probably the most common amplifier class currently used in home stereo and similar amplifiers. Class AB amplifiers combine the good points of class A and B amps. They have the improved efficiency of class B amplifiers and distortion performance that is a lot closer to that of a class A amplifier. With such amplifiers, distortion is worst when the signal is low and generally lowest when the signal is just reaching the point of clipping. Class AB amplifiers (like class B) use pairs of transistors, both of them being biased slightly ON so that the crossover distortion (associated with Class B amplifiers) is largely eliminated.
Class C: Class C amps are never used for audio circuits. They are commonly used in radio frequency (RF) circuits. Class C amplifiers operate the output transistor in a state that results in tremendous distortion (it would be totally unsuitable for audio reproduction). However, the RF circuits where Class C amplifiers are used employ filtering so that the final signal is completely acceptable. Class C amplifiers are quite efficient. However, for this project, I will use the class D audio amplifier because it can
work as digital audio amplifier. Below is the description of class D audio amplifier.
Class D: The concept of a Class D amplifier has been around for a long time (~ 50 years or so), however only fairly recently have they become more commonly used in consumer applications. Due to improvements in the speed, power capacity and efficiency of modern semiconductor devices, applications using Class D amplifiers have become affordable for the common person. Class D amplifiers use a completely different method of amplification as compared to Class A, B and AB. Whereas the aforementioned classes of amplifier operate the semiconductor devices in the linear mode, Class D amplifiers operate the output semiconductor devices as switches (ON or OFF). In a Class D amplifier, the input signal is compared with a high frequency triangle wave, resulting in the generation of a Pulse Width Modulation (PWM) type signal. This signal is then applied to a special filter that removes all the unwanted high frequency by-products of the PWM stage. The output of the filter drives the speaker. Class D amplifiers are most often
4 found in car audio subwoofer amplifiers. The major advantage of Class D amplifiers is that they have the potential for very good efficiency (due to the fact that the semiconductor devices are ON or OFF in the power stage, resulting in low power dissipation in the device as compared to linear amplifier classes). One notable disadvantage of Class D amplifiers: they are fairly complicated and special care is required in their design. Due to the high frequencies that are present in the audio signal (as a result of the PWM stage), Class D amplifiers used for car stereo applications are often limited to subwoofer frequencies, however designs are improving all the time. It will not be too long before a full band class D amplifier becomes commonplace and less costly. Class D amplifiers find use in many other applications besides audio. Class D amplifiers will probably eventually revolutionize audio power amplifiers: when they are perfected, their efficiency will allow outputs of 1000+ watts without the need for a cooling fan! They will also be small and lightweight compared to the class AB designs that are most common today.
Figure 1.1: Class D amplifier compares analog audio to triangle wave to create pulse modulation
Figure 1.2: Class D Topology
1.2 Objective The objective of this project is to design a digital audio amplifier that will amplify from a low signals and filter out frequencies outside the loudspeaker with 100watts as the output. The design will then be simulated using MULTISIM software and the final circuit will be implemented into hardware.
1.3 Scope of Work Figure 1.1 signifies the limitation of studies and the scope of work for the project. It will start with the audio input until the output at the speaker.
Figure 1.1 Block Diagram of the project.
1.4 Problem Statement Nowadays, Class D designs are rivals to most class AB amplifiers. Class D has more respectable total harmonic distortion (THD) performance that is very competitive with class AB. Other than that, the efficiency of other classes is not high. So, with class D design, it can improve until 95% of efficiency. Improves efficiency translates into lower system cost, lower operating temperatures, lower power supply voltages, and lower power consumption.
CHAPTER 2
PROJECT OVERVIEW
2.1 Chip TDA8920BJ
The TDA8920 is a high efficiency class-D audio power amplifier. It can be used in a mono Bridge-Tied Load (BTL) or in a stereo Singled-Ended (SE) configuration. The device operates over a wide supply voltage range from 15 V up to 30 V and consumes a very low quiescent current. Figure 2.1 is the block diagram of the chip with pin numbering.
Figure 2.1: Block Diagram
The audio input signal is converted to a digital Pulse Width Modulation (PWM) signal via an analog input stage and PWM modulator. To enable output power transistors to be driven, this digital PWM signal is applied to a control and handshake block and driver circuit for both the high side and low side. In this way a level shift is performed from the low power digital PWM signal (at logic levels) to a high power PWM signal which switches between the main supply lines. A 2nd order low-pass filter converts the PWM signal to an analog audio signal across the loudspeaker.
2.1.1 Description
This TDA8920BJ have a high efficiency. It can be reach until 90%. To make sure this IC operate successfully, the operating voltage are from 15V to 30V and use differential audio inputs. As define before, this IC is usable as a mono amplifier in Bridge-Tied Load (BTL) or as a Stereo Single-Ended (SE) amplifier. The advantages of this IC are has very low distortion, very low quiescent current, short circuit proof across the load and has good ripple rejection. It has fixed gain of 30dB and high output power. For the protection, it is already have electrostatic discharge protection on all pins and also thermally protected.
2.1.2 Mode Selection
The amplifier can be switched in three operating modes with the mode select input: o Standby mode, with a very low supply current (practically zero) o Mute mode; the amplifiers are operational but the audio signal at the output is suppressed o Operating mode (amplifier fully operational) with output signal.
For suppressing plop noise the amplifier will remain automatically for approximately 500 ms in the mute mode before switching to operating mode. During this time the coupling capacitors at the input are fully charged. An example of a switching circuit for driving the mode select input is illustrated in Fig.2.2.
Figure 2.2: Mode select drive input circuit
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Figure 2.3 signifies the mode select transfer characteristic with different mode. Where Vth is threshold voltage and Vms is mode selector voltage (5.5V).
Figure 2.3: Mode select transfer characteristic
Where, Vms (hys1) = (Vth1+) (Vth1-) Vms (hys2) = (Vth2+) (Vth2-) (1.1) (1.2)
2.1.3 Protection Protections are included to avoid the device being damaged at over-temperature Tj > 150 C, if happen the power stage will shut down immediately. The power stage will start switching again if the temperature drops to approximately 130 C, thus there is a hysteresis of approximately 20 C. When short-circuit of the loudspeaker terminals, the power dissipation is limited. A maximum current limiter which limits the maximum output current to 8 A, or to the value set by RLIM. During limiting the current is measured and when the current is higher than 8 A, the amplifier is switched off within 3 ms and every 20 ms the IC tries to restart. The dissipation will be low because of this low duty cycle.
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2.2 Pulse Width Modulation
PWM is what makes a Class-D amplifier digital, or at least quasi-digital. Instead of an amplifier using a sine wave throughout its amplification process, it uses a series of square waves in which the duty cycles vary according to the input signal. As an input signal approaches its upper limits, the duration of the pulses increase. The average of all the varying width pulses is equivalent to the original input.
The Class-D amplifier utilizes an H-bridge to convert the PWM square-wave to an acoustic wave that ultimately drives the speakers at the output stage. Figure 2.4 depicts a PWM signal.
Figure2.4: Input Sine Wave vs. PWM Output The red line in Figure 2.4 is the input sine wave that was needed to generate the PWM signal. Notice when the sinusoidal waveform reaches its peaks, the pulse width remains wider versus when the sinusoidal waveform approaches zero volts, the pulse widths get smaller. Class-D amplifiers typically use two-level rather than three-level PWM to control the switching of the H-bridge circuit. Two-level PWM contains two possible output levels, high and low. Three-level PWM contains three possible output levels, positive, negative, and zero. Figure 2.5 illustrates the difference between the two PWM methods.
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Figure 2.5: Two-Level vs. Three-Level PWM
Three-level PWM is more beneficial because it increases the efficiency of the H-bridge circuit. To prove this, we must look at the input when it is zero volts. The two-levels duty cycle will be 50% because the MOSFETs will be switching on and off equally. The three-levels duty cycle will be zero because there is no need to draw current through the load. This conserves energy by minimizing MOSFET switching, increasing the efficiency.
In todays standard Class-D amplifier, the PWM signal is created by a comparator. The comparators job is simply to compare the audio signal to a reference signal, typically a triangle wave. When the audio signals amplitude is larger than the reference signals amplitude the resulting PWM signal is high. The longer the audio signals amplitude remains larger than the reference signals amplitude, the longer the PWM will remain high. In the case when the audio signal changes polarity, the terminals on the comparator circuit become switched. The analog input goes to the inverting terminal and the reference signal goes to the noninverting terminal.
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Figure 2.6: PWM Comparator
To achieve a proper PWM signal that will represent an analog input, the reference signal amplitude must be larger than the maximum input amplitude. Another important factor of the reference signal is the operating frequency or clock speed of that waveform. The operating frequency must be faster than the audio signal to assure an accurate sampling rate. [1] The faster the clock speed of the reference signal, the closer the output will represent the input. The advantage of an extremely high clock speed, 1MHz and up is full audible bandwidth capabilities of the amplifier, 20 to 20 kHz. As of 2003, the Xtant 1.1i was the only Class D amplifier on the market with this capability. [2]
2.3 Low Pass Filter
There are three main filter optimizations in active filters, which are Butterworth, Bessel and Chebyshev. The Butterworth low pass filters provide maximum pass band flatness as shown in Figure 2.7. Therefore, a Butterworth low pass is often used as anti-aliasing filter in data converter applications where precise signal levels are required across the entire pass band.
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Figure 2.7 Amplitude Response of Butterworth Low Pass Filter
From Figure 2.8, it can be seen that Chebyshev low pass filters provide an even better roll off above fc. However, the pass band gain is not monotone, but contains ripples of constant magnitude instead. For a given filter order, the higher the pass band ripples, the higher the filters roll off. Chebyshev filters are often used in filter banks, where the frequency content of a signal is of more importance than a constant amplification.
Figure 2.8: Gain responses of Chebyshev Low Pass Filter
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The Bessel low pass filters have a linear phase response over a wide frequency range, which results in a constant group delay in that frequency range. Bessel low pass filters, therefore, provide an optimum square wave transmission behavior. However, the pass band gain of a Bessel is not as flat as that of the Butterworth, and the transition from pass band to stop band is by far not as sharp as that of a Chebyshev low pass filter.
2.4 Theoretical analysis of class D operation
Generally, it is well-known that using feedback around an amplifier, it is possible to trade off raw amplification ability against different other properties. Such as bandwidth, high input impedance, or reduction of distortion. Think of a one-bit analog-to-digital quantizer, for example realized as a simple comparator. It is self-evident that the result will be very poor if you try to sample a signal with it - it can only detect the zero-crossings in the input signal, and nothing else. But in some sense, the one-bit quantizer is something that does let an input signal through, although severly distorted. This is something that can be exploited, using feedback. Place this distorting element in a feedback loop. Also, introduce a loop filter according to the Figure 2.9. The quantizer is modeled as a source of distortion, or noise. That is, a noise signal Q(s) is added to the output of the loop filter. (X(s) and Y(s) denote the Laplace-transform of the corresponding continuous variables x(t) and y(t) respectively. H(s) is the transfer function of the loop filter, and is the feedback factor (usually < 1))
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Figure 2.9: Loop Filter
The output signal Y(s) can be expressed as: Y(s) = Q(s) + H(s) (X(s) - Y(s)) If this is solved for Y(s), then Y(s) = H(s) 1+H(s) X(s) + 1 1+H(s) Q(s) (2.4) (2.3)
Now you can see the benefit of the feedback loop. Suppose to begin with that H(s)=a, where a is a (high) constant amplification factor > 106. Then the first term in the expression above can be simplified to X(s) / , and the second term can be simplified to Q(s) / a. This shows that the desired signal X(s) is amplified by a factor 1/, while the undesired quantization noise is amplified by 1/a, which in effect is a powerful suppression of the noise if a is large. If an integrator is used as the loop filter (i.e. a low-pass filter with H(s)=a/s), then the second term in the expression for Y(s) above will take on a high-pass characteristic. The total noise power (summed over all frequencies) is thereby actually increased, but it can be shown that the noise power is decreased in the lower part of the frequency spectrum. This is what is referred to as noise shaping.
CHAPTER 3
METHODOLOGY
3.1 Research Methodology The simplified methodology is shown in the diagram below:
Literature Review
Design & Simulate Circuit
Compare Results for Calculation & Simulation
Success?
Y
Implement Design into Hardware
Figure 3.1: Methodology for the Project
18 Literature review was done by reading books, journals and websites that instruct on how to design a Class D audio amplifier. An amplifier that can produce the output power of 100 watts and a low pass filter that will filter out the unwanted signals in the range of 20Hz-20 kHz was designed. After some revision, for this project I choose to design the circuit using TDA8920J. This IC is quiet difficult to get, so the supplier suggest that I use TDA8920J because it has same characteristic with TDA8920J. For this project, the circuit cannot be simulated in MULTISIM. So, the design was implemented into hardware.
3.2 Circuit and Hardware Design The circuit was designed based on the specifications and the characteristic of the IC. It is often enough overlooked as to how the actual testing of a system will be done. For this reason, it will be show on the most basic level how the amplifier will be tested in terms of power and efficiency. Please note the following figure.
Figure 3.2: Block diagram
By measuring both the voltage and current at the power supply, the input power of the amplifier can be determined using the following formula: (3.1)
PIN = I * V
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By finding the RMS voltage out of the amplifier, the output power of the amplifier can be determined using the following formula: POUT = V 2/ R (3.2)
From the actual power of the amplifier, the efficiency can be calculated. The theoretical efficiency has already been determined in the MOSFET section of this paper. If the measured output is divided by the input power, this will yield the efficiency of the amplifier. (3.3)
Efficiency = OutputPower / InputPower
If a 1 load was used for testing in laboratory, the testing equipment would have to be capable of handling 42 Amps of current. Such equipment is expensive, and might not be readily available.
CHAPTER 4
RESULTS
4.1 Current Limiting From Figure 4.1, with an external resistor RLIM connected between pin LIM (7) and VSS (-25V for the circuit) the maximum output current of the amplifiers can be set. If pin LIM is short-circuited to VSS, then the maximum output current is limited to 8 A. The relationship between maximum output current and resistor value is given by: Io(max) = 70.103 / 10.103 + RLIM So, RLIM = (70.103 / 8) 10.103 = 42.03 k (4.2) (4.1)
Figure 4.1: current limiting
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4.2 Mode Selector
Figure 4.2: Mode switching in normal way Figure 4.2 show when switching from standby to mute, there is a delay of 100 ms before the output starts switching. The audio signal is available after Vmode has been set to operating, but not earlier than 150 ms after switching to mute. For popnoise free start-up it is recommended that the time constant applied to the MODE pin is at least 350 ms for the transition between mute and operating. When switching directly from standby to operating, there is a first delay of 100 ms before the outputs starts switching. The audio signal is available after a second delay of 50ms. For pop-noise free start-up it is recommended that the time constant applied to the MODE pin is at least 500 ms for the transition between standby and operating. This is shown in Figure 4.3.
Figure 4.3: Mode switching directly from standby-operating
22 4.3 Pulse Width Modulation frequency For TDA8920J, the output signal of the amplifier is a PWM signal with a sample frequency of 500 kHz. But for TDA8920BJ, the sample frequency is 317 kHz. This switching frequency is fixed by an external resistor ROSC connected between pin OSC (1) and Vss. An optimal setting carrier frequency is between 300 kHz and 350 kHz. The oscillator frequency can be calculated using: TDA8920J Fosc = 5 x 109 / Rosc = 5 x 109 / 10k = 500 kHz TDA8920BJ Fosc = 9.51 x 109 / Rosc = 9.51 x 109 / 30k = 317 kHz (4.4) (4.3)
Figure 4.4: oscillator
23 4.4 Filter For this project, I do not get the output or frequencies response through the hardware. But I have done some simulating based on the characteristic of the design. In this project we used the low pass filter. So, to ensure the goal of 95% efficiency, it was decided to use a passive filter. A passive filter is able to achieve higher efficiency because it theoretically gives back all the energy that it absorbs. To determine the values, the following formulas were used. [3]
(4.5)
(4.6)
From these equations, the capacitor value was calculated to be 1.4 F and the inductor value was calculated to be 45 H. These were based on a 4 load in a typical low-pass filter configuration as seen below in Figure 4.5. A 4 load was chosen because it matches the typical speaker impedance. This means that if 2 speakers are connected in series yielding an 8 load, the amplifier will be capable of playing up to 40 kHz rather than the cut-off frequency of 20 kHz. Conversely, a 2 load will only be able to play up to 10 kHz, and a 1load will only be able to play up to 5 kHz. We chose this configuration because when trying to achieve high quality sound, the lower impedances generally lose their quality. This means that a 2 or 1 load should be reserved for subwoofer applications where the cut-off frequency is not as much of an issue. A typical subwoofer is reserved for very low frequencies less than 500 Hz.
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Figure 4.5: typical low pass filter The low pass filter was modified to be more similar to the IC. So the values for inductor and capacitor were changed. This may look like the typical low-pass filter, but notice that based on the filter described above, the load output is half, the input voltage is half, the inductor value is half, and the capacitor value is doubled.
Figure 4.6: Bode Plot for 1 Ohm load
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Figure 4.9: Bode Plot for 8 Ohm load The simulations show where the cut-off frequency will be for each speaker load configuration. The calculations were very close to the simulated results with the margin of error increasing as the impedance decreased. Notice that the last figure of the 8 load shows a frequency of approximately 20 kHz. This is due to the fact that there is a slight rise in the filter response before the cut-off. The rise is approximately 3db, and that is what is shown.
4.5 Output power estimation Maximum current (internally limited to 8 A): Io(peak) = VP (1tmin fosc) /( RL + 0.4) From the equation 4.7, we can get the load impedance, RL. RL = [ 30 x (1-150n x 317k) ] 8 0.4 = 3.17 (4.7)
Po(1%) = [(RL / RL+0.4)VP(1-tminfosc) 2RL]
(4.8)
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So, the value from e.q(1) will use in equation (2). Then we will get Po(1%) = 101.54 W Variables: RL = load impedance Fosc = oscillator frequency Tmin = minimum pulse width (typical 150 ns) VP = single-sided supply voltage (so, if supply is 30 V symmetrical, then VP =30V) Po(1%) = output power just at clipping Po(10%) = output power at THD = 10 % Po(10%) = 1.24 Po(1%).
4.6 Output Power Due to the fact that this project was about creating an audio amplifier, it was thought necessary to show that the project constructed actually had the ability to amplify a signal. The actual output can be seen in Figure 4.10 below.
Figure 4.10: Input vs. Output
28
From the picture shown that an input sine wave at 5 Volts per division on the scope and an output sine wave at 25 Volts per division. What is cannot that the test input signal was a 300 kHz sine wave with amplitude of 1.4 Volts. The output waveform was measured to have amplitude of 40 Volts. To determine the gain of this amplifier, it can simply divide the output power by the input power as shown. Gain = output / input = 40 / 1.4 = 28.57
4.7 Signal to Noise ratio When looking at industry standards, one specification given on almost every amplifier is a signal-to-noise ratio (SNR). This specification indicates how much noise is created in the amplifier relative to the signal you are trying to pass through it. If the noise power is small enough compared to the output power, then it will not audible to the human ear at the output. The SNR more simply is the ratio of signal power to noise power. Below is the formula. SNR = Psignal / Pnoise (4.9)
In order to compute the SNR, an FFT of the output must first be examined. For this amplifier a 300 kHz sinusoidal input with amplitude of 1.4 Volts was used. Examined the output, as seen in Figure 4.11.
29
Figure 4.11 The data was imported into Microsoft Excel, where we were able to use the data to compute the power of both the signal and noise. To do this, we had to first separate the signal power from the noise power, have to be separated. That was done by observing the large magnitudes that occurred around 300 kHz where the spike was apparent.
CHAPTER 5
DISCUSSION
1.1 Discussion
Now that the project is done but not completed well, I recognize that there are some things that could have been done differently. There are areas for improvement in all stages of the design. This section will focus on ideas that could be implemented into the amplifier to improve upon the existing design.
Actually for this project I did not get the correct output as expected in the objective. So, here I want to give some recommendation to the next design to improve the results.
Firstly, the circuit must be modified to a simple design. Where, it is more easy to understand and detect where the error area. In my experience, when we using components that already design by some company, it have some difficulty to find the error or what the problems inside them.
Other than that, the result must be affected when soldering. The temperatures that apply to the IC are more than the limited thermal.
31
CHAPTER 6
CONCLUSION
After all of the process to done this project, it can conclude that it is not easy to built the digital audio amplifier without any knowledge on circuit diagram and literature review. A lot of mistake can happen along the work to end this project. This project did not achieve the objective at all. The output of the design for the amplifier is not successful because there are some problems on the hardware after it was soldered. It may caused by the temperature during soldering or some of the components was burnt.
Other than that, the IC that I used in this design had some problems that may effect the outputs. The gain of the design and the bandwidth of the low pass filter were successfully simulated. The gain is 28.75dB.
32
REFERRENCE
Boylestad, L. Nashelsky. Electronic Devices and Circuit Theory. New Jersey: Prentice Hall, 1992 An Introduction to Digital Audio, John Watkinson, Focal Press. Audio Technology Systems: Principles, Applications, and Troubleshooting, Derek Cameron, A Prentice Hall Company. The IEEE journal Design with Operational Amplifier and Analog Integrated Circuits, Second Edition, Sergio Franco, WCB McGraw Hill. Philips Semiconductor Website Mr. Takumi Suga (engineer) Pohlmann, K.C. Principles of Digital Audio, 3rd ed. New York: McGraw-Hill, 1995.
1 http://www.cpemma.co.uk/pwm.html 2 www.xtant.com/html/products/xtant1.li.cfm 3 Class D Audio Amplifier, WPI MQP,2003 4 http://www.extron.com
APPENDIX A
GANTT CHART PSM 1
APPENDIX A
GANTT CHART PSM 2
34
TDA8920B
2 100 W class-D power amplier
Rev. 01 1 October 2004 Preliminary data sheet
1. General description
The TDA8920B is a high efciency class-D audio power amplier with very low dissipation. The typical output power is 2 100 W. The device is available in the HSOP24 power package and in the DBS23P through-hole power package. The amplier operates over a wide supply voltage range from 12.5 V to 30 V and consumes a very low quiescent current.
2. Features
s s s s s s s s s s s s s Zero dead time switching Advanced current protection: output current limiting Smooth start-up: no pop-noise due to DC offset High efciency Operating supply voltage from 12.5 V to 30 V Low quiescent current Usable as a stereo Single-Ended (SE) amplier or as a mono amplier in Bridge-Tied Load (BTL) Fixed gain of 30 dB in Single-Ended (SE) and 36 dB in Bridge-Tied Load (BTL) High output power High supply voltage ripple rejection Internal switching frequency can be overruled by an external clock Full short-circuit proof across load and to supply lines Thermally protected.
3. Applications
s s s s s Television sets Home-sound sets Multimedia systems All mains fed audio systems Car audio (boosters).
Philips Semiconductors
TDA8920B
4. Quick reference data

Table 1: Quick reference data Conditions Min 12.5 no load; no lter; no RC-snubber network connected RL = 3 ; THD = 10 %; VP = 27 V RL = 4 ; THD = 10 %; VP = 27 V Mono bridge-tied load conguration Po output power RL = 6 ; THD = 10 %; VP = 27 V 210 W Typ 27 50 Max 30 65 Unit V mA Symbol Parameter General; VP = 27 V VP Iq(tot) supply voltage total quiescent supply current output power
Stereo single-ended conguration Po 110 86 W W
5. Ordering information
Table 2: Ordering information Package Name TDA8920BTH TDA8920BJ HSOP24 DBS23P Description plastic, heatsink small outline package; 24 leads; low stand-off height plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) Version SOT566-3 SOT411-1 Type number
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Preliminary data sheet
Rev. 01 1 October 2004
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6. Block diagram
VDDA2 3 (20) VDDA1 10 (4) VDDP2 23 (16) VDDP1 14 (8) 15 (9)
STABI PROT 18 (12) 13 (7) RELEASE1
BOOT1
IN1M IN1P
9 (3) 8 (2) INPUT STAGE PWM MODULATOR
CONTROL AND ENABLE1 HANDSHAKE
SWITCH1
DRIVER HIGH 16 (10) DRIVER LOW VSSP1 OUT1
SGND1 OSC MODE
11 (5) 7 (1) 6 (23)
mute STABI
OSCILLATOR MODE
MANAGER
TEMPERATURE SENSOR CURRENT PROTECTION VOLTAGE PROTECTION
TDA8920BTH (TDA8920BJ)
VDDP2 22 (15) BOOT2
SGND2
2 (19) mute ENABLE2 CONTROL SWITCH2 AND HANDSHAKE RELEASE2 DRIVER HIGH 21 (14) DRIVER LOW 17 (11) VSSP1 20 (13) VSSP2 OUT2
IN2P IN2M
5 (22) 4 (21) INPUT STAGE PWM MODULATOR
1 (18) VSSA2
12 (6) VSSA1
24 (17) VSSD
19 (-) n.c.
coa023
Pin numbers in parenthesis refer to the TDA8920BJ.
Fig 1. Block diagram.
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7. Pinning information
7.1 Pinning
OSC IN1P IN1M VDDA1 SGND1 VSSD 24 VDDP2 23 BOOT2 22 OUT2 21 VSSP2 20 n.c. 19 STABI 18 VSSP1 17 OUT1 16 BOOT1 15 VDDP1 14 PROT 13
001aab217
1 2 3 4 5 6 7 8 9
1 2 3 4 5
VSSA2 SGND2 VDDA2 IN2M IN2P MODE OSC IN1P IN1M
VSSA1 PROT VDDP1 BOOT1
OUT1 10 VSSP1 11 STABI 12 VSSP2 13 OUT2 14 BOOT2 15 VDDP2 16 VSSD 17 VSSA2 18 SGND2 19 VDDA2 20 IN2M 21 IN2P 22 MODE 23
001aab218
TDA8920BTH
6 7 8 9
TDA8920BJ
10 VDDA1 11 SGND1 12 VSSA1
Fig 2. Pin conguration TDA8920BTH.
Fig 3. Pin conguration TDA8920BJ.
7.2 Pin description

Table 3: Pin description Description TDA8920BJ 18 19 20 21 22 23 1 2 3 4 negative analog supply voltage for channel 2 signal ground for channel 2 positive analog supply voltage for channel 2 negative audio input for channel 2 positive audio input for channel 2 mode selection input: Standby, Mute or Operating mode oscillator frequency adjustment or tracking input positive audio input for channel 1 negative audio input for channel 1 positive analog supply voltage for channel 1 TDA8920BTH VSSA2 SGND2 VDDA2 IN2M IN2P MODE OSC IN1P IN1M VDDA1 1 2 3 4 5 6 7 8 9 10 Symbol Pin
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Pin description continued Description TDA8920BJ 5 6 7 8 9 10 11 12 13 14 15 16 17 signal ground for channel 1 negative analog supply voltage for channel 1 decoupling capacitor for protection (OCP) positive power supply voltage for channel 1 bootstrap capacitor for channel 1 PWM output from channel 1 negative power supply voltage for channel 1 decoupling of internal stabilizer for logic supply not connected negative power supply voltage for channel 2 PWM output from channel 2 bootstrap capacitor for channel 2 positive power supply voltage for channel 2 negative digital supply voltage TDA8920BTH
Table 3:
Symbol Pin SGND1 VSSA1 PROT VDDP1 BOOT1 OUT1 VSSP1 STABI n.c. VSSP2 OUT2 BOOT2 VDDP2 VSSD 11 12 13 14 15 16 17 18 19 20 21 22 23 24
8. Functional description
8.1 General
The TDA8920B is a two channel audio power amplier using class-D technology. The audio input signal is converted into a digital Pulse Width Modulated (PWM) signal via an analog input stage and PWM modulator. To enable the output power transistors to be driven, this digital PWM signal is applied to a control and handshake block and driver circuits for both the high side and low side. In this way a level shift is performed from the low power digital PWM signal (at logic levels) to a high power PWM signal which switches between the main supply lines. A 2nd-order low-pass lter converts the PWM signal to an analog audio signal across the loudspeakers. The TDA8920B one-chip class-D amplier contains high power D-MOS switches, drivers, timing and handshaking between the power switches and some control logic. For protection a temperature sensor and a maximum current detector are built-in. The two audio channels of the TDA8920B contain two PWMs, two analog feedback loops and two differential input stages. It also contains circuits common to both channels such as the oscillator, all reference sources, the mode functionality and a digital timing manager. The TDA8920B contains two independent amplier channels with high output power, high efciency, low distortion and a low quiescent current. The amplier channels can be connected in the following congurations:
Mono Bridge-Tied Load (BTL) amplier Stereo Single-Ended (SE) ampliers.

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The amplier system can be switched in three operating modes with pin MODE:
Standby mode; with a very low supply current Mute mode; the ampliers are operational; but the audio signal at the output is
suppressed by disabling the VI-converter input stages
Operating mode; the ampliers are fully operational with output signal.
To ensure pop-noise free start-up the DC output offset voltage is applied gradually to the output between Mute mode and Operating mode. The bias current setting of the VI converters is related to the voltage on the MODE pin; in Mute mode the bias current setting of the VI converters is zero (VI converters disabled) and in Operating mode the bias current is at maximum. The time constant required to apply the DC output offset voltage gradually between mute and operating can be generated via an RC-network on the MODE pin. An example of a switching circuit for driving pin MODE is illustrated in Figure 4. If the capacitor C is left out of the application the voltage on the MODE pin will be applied with a much smaller time-constant, which might result in audible pop-noises during start-up (depending on DC output offset voltage and used loudspeaker). In order to fully charge the coupling capacitors at the inputs, the amplier will remain automatically in the Mute mode before switching to the Operating mode. A complete overview of the start-up timing is given in Figure 5.
+5 V standby/ mute R MODE pin R C mute/on SGND

001aab172
Fig 4. Example of mode selection circuit.
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audio output
modulated PWM Vmode 50 % duty cycle operating
> 4.2 V
2.2 V < Vmode < 3 V
mute
0 V (SGND)
standby 100 ms 50 ms > 350 ms time
audio output
modulated PWM Vmode 50 % duty cycle operating
> 4.2 V
2.2 V < Vmode < 3 V
mute
0 V (SGND)
standby 100 ms 50 ms
coa024
> 350 ms
time
When switching from standby to mute, there is a delay of 100 ms before the output starts switching. The audio signal is available after Vmode has been set to operating, but not earlier than 150 ms after switching to mute. For pop-noise free start-up it is recommended that the time constant applied to the MODE pin is at least 350 ms for the transition between mute and operating. When switching directly from standby to operating, there is a rst delay of 100 ms before the outputs starts switching. The audio signal is available after a second delay of 50 ms. For pop-noise free start-up it is recommended that the time constant applied to the MODE pin is at least 500 ms for the transition between standby and operating.
Fig 5. Timing on mode selection input.
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8.2 Pulse width modulation frequency

The output signal of the amplier is a PWM signal with a carrier frequency of approximately 317 kHz. Using a 2nd-order LC demodulation lter in the application results in an analog audio signal across the loudspeaker. This switching frequency is xed by an external resistor ROSC connected between pin OSC and VSSA. An optimal setting for the carrier frequency is between 300 kHz and 350 kHz. Using an external resistor of 30 k on the OSC pin, the carrier frequency is set to 317 kHz. If two or more class-D ampliers are used in the same audio application, it is advisable to have all devices operating at the same switching frequency by using an external clock circuit.
8.3 Protections
The following protections are included in TDA8920B:
OverTemperature Protection (OTP) OverCurrent Protection (OCP) Window Protection (WP) Supply voltage protections: UnderVoltage Protection (UVP) OverVoltage Protection (OVP) UnBalance Protection (UBP).
The reaction of the device on the different fault conditions differs per protection:
8.3.1 OverTemperature Protection (OTP)

If the junction temperature Tj > 150 C, then the power stage will shut-down immediately. The power stage will start switching again if the temperature drops to approximately 130 C, thus there is a hysteresis of approximately 20 C.
8.3.2 OverCurrent Protection (OCP)

When the loudspeaker terminals are short-circuited or if one of the demodulated outputs of the amplier is short-circuited to one of the supply lines, this will be detected by the OverCurrent Protection (OCP). If the output current exceeds the maximum output current of 8 A, this current will be limited by the amplier to 8 A while the amplier outputs remain switching (the amplier is NOT shut-down completely). The amplier can distinguish between an impedance drop of the loudspeaker and low-ohmic short across the load. In the TDA8920B this impedance threshold (Zth) depends on the supply voltage used. When a short is made across the load causing the impedance to drop below the threshold level (< Zth) then the amplier is switched off completely and after a time of 100 ms it will try to restart again. If the short circuit condition is still present after this time this cycle will be repeated. The average dissipation will be low because of this low duty cycle.
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In case of an impedance drop (e.g. due to dynamic behavior of the loudspeaker) the same protection will be activated; the maximum output current is again limited to 8 A, but the amplier will NOT switch-off completely (thus preventing audio holes from occurring). Result will be a clipping output signal without any artefacts. See also Section 13.6 for more information on this maximum output current limiting feature.
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8.3.3 Window Protection (WP)

During the start-up sequence, when pin MODE is switched from standby to mute, the conditions at the output terminals of the power stage are checked. In the event of a short-circuit at one of the output terminals to VDD or VSS the start-up procedure is interrupted and the system waits for open-circuit outputs. Because the test is done before enabling the power stages, no large currents will ow in the event of a short-circuit. This system is called Window Protection (WP) and protects for short-circuits at both sides of the output lter to both supply lines. When there is a short-circuit from the power PWM output of the power stage to one of the supply lines (before the demodulation lter) it will also be detected by the start-up safety test. Practical use of this test feature can be found in detection of short-circuits on the printed-circuit board. Remark: This test is operational during (every) start-up sequence at a transition between Standby and Mute mode. However when the amplier is completely shut-down due to activation of the OverCurrent Protection (OCP) because a short to one of the supply lines is made, then during restart (after 100 ms) the window protection will be activated. As a result the amplier will not start-up until the short to the supply lines is removed.
8.3.4 Supply voltage protections

If the supply voltage drops below 12.5 V, the UnderVoltage Protection (UVP) circuit is activated and the system will shut-down correctly. If the internal clock is used, this switch-off will be silent and without pop noise. When the supply voltage rises above the threshold level, the system is restarted again after 100 ms. If the supply voltage exceeds 33 V the OverVoltage Protection (OVP) circuit is activated and the power stages will shut-down. It is re-enabled as soon as the supply voltage drops below the threshold level. So in this case no timer of 100 ms is started. An additional UnBalance Protection (UBP) circuit compares the positive analog (VDDA) and the negative analog (VSSA) supply voltages and is triggered if the voltage difference between them exceeds a certain level. This level depends on the sum of both supply voltages. An expression for the unbalanced threshold level is as follows: Vth(ub) 0.15 (VDDA + VSSA). When the supply voltage difference drops below the threshold level, the system is restarted again after 100 ms. Example: With a symmetrical supply of 30 V, the protection circuit will be triggered if the unbalance exceeds approximately 9 V; see also Section 13.7. In Table 4 an overview is given of all protections and the effect on the output signal.
Table 4: OTP OCP WP UVP OVP UBP
[1]
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Overview protections TDA8920B Complete shut-down Y N [2] Y [3] Y Y Y Restart directly Y [1] Y [2] Y N Y N Restart every 100 ms N [1] N [2] N Y N Y
Protection name
Hysteresis of 20 degrees will inuence restart timing depending on heatsink size.

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[2] [3]
Only complete shut-down of amplier if short-circuit impedance is below threshold of 1 . In all other cases current limiting: resulting in clipping output signal. Fault condition detected during (every) transition between standby-to-mute and during restart after activation of OCP (short to one of the supply lines).
8.4 Differential audio inputs

For a high common mode rejection ratio and a maximum of exibility in the application, the audio inputs are fully differential. By connecting the inputs anti-parallel the phase of one of the channels can be inverted, so that a load can be connected between the two output lters. In this case the system operates as a mono BTL amplier and with the same loudspeaker impedance an approximately four times higher output power can be obtained. The input conguration for a mono BTL application is illustrated in Figure 6. In the stereo single-ended conguration it is also recommended to connect the two differential inputs in anti-phase. This has advantages for the current handling of the power supply at low signal frequencies.
IN1P IN1M Vin IN2P IN2M
OUT1
SGND
OUT2
power stage
mbl466
Fig 6. Input conguration for mono BTL application.
9. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VP IORM Tstg Tamb Tj
[1]
Parameter supply voltage repetitive peak current in output pin storage temperature ambient temperature junction temperature
Conditions maximum output current limiting

[1]
Min 8 55 40 -
Max 30 +150 +85 150
Unit V A C C C
Current limiting concept. See also Section 13.6.
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10. Thermal characteristics

Table 6: Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient TDA8920BTH TDA8920BJ Rth(j-c) thermal resistance from junction to case TDA8920BTH TDA8920BJ
[1] See also Section 13.5.
Conditions
[1]
Typ 35 35
[1]
Unit K/W K/W K/W K/W
in free air in free air
1.3 1.3
11. Static characteristics

Table 7: Static characteristics VP = 27 V; fosc = 317 kHz; Tamb = 25 C; unless otherwise specied. Symbol Supply VP Iq(tot) Istb VI II Vstb Vmute Von VI VOO(SE)(mute) VOO(SE)(on) VOO(BTL)(on) Vo(stab) supply voltage total quiescent supply current standby supply current input voltage input current input voltage for Standby mode input voltage for Mute mode input voltage for Operating mode DC input voltage mute SE output offset voltage operating SE output offset voltage operating BTL output offset voltage stabilizer output voltage mute and operating; with respect to VSSP1
[4] [2] [1]
Parameter
Conditions
Min
Typ
Max 30 65 500 6 300 0.8 3.0 6 15 150 21 210 15
Unit V mA A V A V V V V mV mV mV mV V
12.5 27 0 0 2.2 4.2 11 50 150 100 0 12.5
no load, no lter; no snubber network connected
Mode select input; pin MODE VI = 5.5 V

[2] [3] [2] [3] [2] [3]
Audio inputs; pins IN1M, IN1P, IN2P and IN2M

[2]
Amplier outputs; pins OUT1 and OUT2
VOO(BTL)(mute) mute BTL output offset voltage

[4]
Stabilizer output; pin STABI
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Table 7: Static characteristics continued VP = 27 V; fosc = 317 kHz; Tamb = 25 C; unless otherwise specied. Symbol Tprot Thys
[1] [2] [3] [4]
Parameter temperature protection activation hysteresis on temperature protection
Conditions
Min -
Typ 150 20
Max -
Unit C C
Temperature protection
The circuit is DC adjusted at VP = 12.5 V to 30 V. With respect to SGND (0 V). The transition between Standby and Mute mode contain hysteresis, while the slope of the transition between Mute and Operating mode is determined by the time-constant on the MODE pin; see Figure 7. DC output offset voltage is applied to the output during the transition between Mute and Operating mode in a gradual way. The slope of the dV/dt caused by any DC output offset is determined by the time-constant on the MODE pin.
slope is directly related to time-constant on the MODE pin

VO (V) Voo (on) STBY MUTE ON
Voo (mute)
0.8
2.2
3.0
5.5 4.2 VMODE (V)

coa021
Fig 7. Behavior of mode selection pin MODE.
12. Dynamic characteristics

12.1 Switching characteristics
Table 8: Switching characteristics VDD = 27 V; Tamb = 25 C; unless otherwise specied. Symbol fosc fosc(int) VOSC VOSC(trip) ftrack Parameter typical internal oscillator frequency internal oscillator frequency range high-level voltage on pin OSC trip level for tracking on pin OSC frequency range for tracking Conditions ROSC = 30.0 k Min 290 210 SGND + 4.5 210 Typ 317 SGND + 5 SGND + 2.5 Max 344 600 SGND + 6 600 Unit kHz kHz V V kHz Internal oscillator
External oscillator or frequency tracking
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12.2 Stereo and dual SE application

Table 9: Stereo and dual SE application characteristics VP = 27 V; RL = 4 ; fi = 1 kHz; fosc = 317 kHz; RsL < 0.1 [1]; Tamb = 25 C; unless otherwise specied. Symbol Po Parameter output power Conditions RL = 3 ; VP = 27 V THD = 0.5 % THD = 10 % RL = 4 ; VP = 27 V THD = 0.5 % THD = 10 % RL = 6 ; VP = 27 V THD = 0.5 % THD = 10 % RL = 8 ; VP = 27 V THD = 0.5 % THD = 10 % THD total harmonic distortion Po = 1 W fi = 1 kHz fi = 6 kHz Gv(cl) SVRR closed loop voltage gain supply voltage ripple rejection operating fi = 100 Hz fi = 1 kHz mute; fi = 100 Hz standby; fi = 100 Hz Zi Vn(o) input impedance noise output voltage operating Rs = 0 mute cs Gv Vo(mute) CMRR
[1] [2] [3] [4] [5] [6] [7] [8]
[5] [6] [7] [4] [4] [4] [3] [2] [2] [2] [2]
Min 29 40 45 [8]
Typ 87 110 69 86 48 60 36 45 0.02 0.03 30 55 50 55 80 68 210 160 70 100 75
Max 0.05 31 1 -
Unit W W W W W W W W % % dB dB dB dB dB k V V dB dB V dB
channel separation channel unbalance output signal in mute common mode rejection ratio Vi(CM) = 1 V (RMS)
RsL is the series resistance of inductor of low-pass LC lter in the application. Output power is measured indirectly; based on RDSon measurement. See also Section 13.3. Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, using AES17 20 kHz brickwall lter. Maximum limit is guaranteed but may not be 100 % tested. Vripple = Vripple(max) = 2 V (p-p); Rs = 0 . B = 22 Hz to 20 kHz, using AES17 20 kHz brickwall lter. B = 22 Hz to 22 kHz, using AES17 20 kHz brickwall lter; independent of Rs. Po = 1 W; Rs = 0 ; fi = 1 kHz. Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.
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12.3 Mono BTL application

Table 10: Mono BTL application characteristics VP = 27 V; RL = 8 ; fi = 1 kHz; fosc = 317 kHz; RsL < 0.1 Symbol Po Parameter output power
[1];
Tamb = 25 C; unless otherwise specied.

Min
[2]
Conditions RL = 6 ; VP = 27 V THD = 0.5 % THD = 10 % RL = 8 ; VP = 27 V THD = 0.5 % THD = 10 %

[2]
Typ 174 210 138 173 0.02 0.03 36 80 80 80 80 34 300 220 200 75
Max 0.05 37 -
Unit W W W W % % dB dB dB dB dB k V V V dB
[3]
THD
total harmonic distortion
Po = 1 W fi = 1 kHz fi = 6 kHz
35
[4]
Gv(cl) SVRR
closed loop voltage gain supply voltage ripple rejection operating fi = 100 Hz fi = 1 kHz mute; fi = 100 Hz standby; fi = 100 Hz
[4] [4]
70 22
Zi Vn(o)
input impedance noise output voltage operating Rs = 0 mute

[5] [6] [7]
Vo(mute) CMRR
[1] [2] [3] [4] [5] [6] [7]
output signal in mute common mode rejection ratio Vi(CM) = 1 V (RMS)
RsL is the series resistance of inductor of low-pass LC lter in the application. Output power is measured indirectly; based on RDSon measurement. See also Section 13.3. Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, using an AES17 20 kHz brickwall lter. Maximum limit is guaranteed but may not be 100 % tested. Vripple = Vripple(max) = 2 V (p-p); Rs = 0 . B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall lter. B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall lter; independent of Rs. Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.
13. Application information

13.1 BTL application
When using the power amplier in a mono BTL application the inputs of both channels must be connected in parallel and the phase of one of the inputs must be inverted (see Figure 6). In principle the loudspeaker can be connected between the outputs of the two single-ended demodulation lters.
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13.2 MODE pin

For pop-noise free start-up an RC time-constant must be applied on the MODE pin. The bias-current setting of the VI-converter input is directly related to the voltage on the MODE pin. In turn the bias-current setting of the VI converters is directly related to the DC output offset voltage. Thus a slow dV/dt on the MODE pin results in a slow dV/dt for the DC output offset voltage, resulting in pop-noise free start-up. A time-constant of 500 ms is sufcient to guarantee pop-noise free start-up (see also Figure 4, 5 and 7).
13.3 Output power estimation

The achievable output powers in several applications (SE and BTL) can be estimated using the following expressions: SE:
2 RL ------------------- V P ( 1 t min f osc ) R L + 0.4 = ---------------------------------------------------------------------------------------2 RL
P o ( 1% )
(1)
Maximum current (internally limited to 8 A): V P ( 1 t min f osc ) I o ( peak ) = ----------------------------------------------------R L + 0.4 BTL:
2 RL ------------------- 2V P ( 1 t min f osc ) R L + 0.8 = -------------------------------------------------------------------------------------------2 RL
(2)
P o ( 1% )
(3)
Maximum current (internally limited to 8 A): 2V p ( 1 t min f osc ) I o ( peak ) = -------------------------------------------------------R L + 0.8 Variables: RL = load impedance fosc = oscillator frequency tmin = minimum pulse width (typical 150 ns) VP = single-sided supply voltage (so, if supply is 30 V symmetrical, then VP = 30 V) Po(1%) = output power just at clipping Po(10%) = output power at THD = 10 % Po(10%) = 1.24 Po(1%). (4)
13.4 External clock

When using an external clock the following accuracy of the duty cycle of the external clock has to be taken into account: 47.5 % < < 52.5 %.
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If two or more class-D ampliers are used in the same audio application, it is strongly recommended that all devices run at the same switching frequency. This can be realized by connecting all OSC pins together and feed them from an external central oscillator. Using an external oscillator it is necessary to force pin OSC to a DC-level above SGND for switching from the internal to an external oscillator. In this case the internal oscillator is disabled and the PWM will be switched on the external frequency. The frequency range of the external oscillator must be in the range as specied in the switching characteristics; see Section 12.1. In an application circuit:
Internal oscillator: ROSC connected between pin OSC and VSSA External oscillator: connect the oscillator signal between pins OSC and SGND; delete
ROSC and COSC.
13.5 Heatsink requirements

In some applications it may be necessary to connect an external heatsink to the TDA8920B. Limiting factor is the 150 C maximum junction temperature Tj(max) which cannot be exceeded. The expression below shows the relationship between the maximum allowable power dissipation and the total thermal resistance from junction to ambient: T j ( max ) T amb R th ( j a ) = ----------------------------------P diss (5)
Pdiss is determined by the efciency () of the TDA8920B. The efciency measured in the TDA8920B as a function of output power is given in Figure 21.The power dissipation can be derived as function of output power (see Figure 20). The derating curves (given for several values of the Rth(j-a)) are illustrated in Figure 8. A maximum junction temperature Tj = 150 C is taken into account. From Figure 8 the maximum allowable power dissipation for a given heatsink size can be derived or the required heatsink size can be determined at a required dissipation level.
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30 Pdiss (W)
mbl469
(1)
20
(2)
10
(3) (4) (5)
0 0 20 40 60 80 100 Tamb (C)
(1) Rth(j-a) = 5 K/W. (2) Rth(j-a) = 10 K/W. (3) Rth(j-a) = 15 K/W. (4) Rth(j-a) = 20 K/W. (5) Rth(j-a) = 35 K/W.
Fig 8. Derating curves for power dissipation as a function of maximum ambient temperature.
13.6 Output current limiting

To guarantee the robustness of the class-D amplier the maximum output current which can be delivered by the output stage is limited. An advanced OverCurrent Protection (OCP) is included for each output power switch. When the current owing through any of the power switches exceeds the dened internal threshold of 8 A (e.g. in case of a short-circuit to the supply lines or a short-circuit across the load) the maximum output current of the amplier will be regulated to 8 A. The TDA8920B amplier can distinguish between a low-ohmic short circuit condition and other overcurrent conditions like dynamic impedance drops of the used loudspeakers. The impedance threshold (Zth) depends on the supply voltage used. Depending on the impedance of the short circuit the amplier will react as follows: 1. Short-circuit impedance > Zth: the maximum output current of the amplier is regulated to 8 A, but the amplier will not shut-down its PWM outputs. Effectively this results in a clipping output signal across the load (behavior is very similar to voltage clipping). 2. Short-circuit impedance < Zth: the amplier will limit the maximum output current to 8 A and at the same time the capacitor on the PROT pin is discharged. When the voltage across this capacitor drops below an internal threshold voltage the amplier will shut-down completely and an internal timer will be started.
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A typical value for the capacitor on the PROT pin is 220 pF. After a xed time of 100 ms the amplier is switched on again. If the requested output current is still too high the amplier will switch-off again. Thus the amplier will try to switch to the Operating mode every 100 ms. The average dissipation will be low in this situation because of this low duty cycle. If the overcurrent condition is removed the amplier will remain in Operating mode once restarted. In this way the TDA8920B amplier is fully robust against short circuit conditions while at the same time so-called audio holes as a result of loudspeaker impedance drops are eliminated.
13.7 Pumping effects

In a typical stereo half-bridge (Single-Ended (SE)) application the TDA8920B class-D amplier is supplied by a symmetrical voltage (e.g VDD = +27 V and VSS = 27 V). When the amplier is used in a SE conguration, a so-called pumping effect can occur. During one switching interval, energy is taken from one supply (e.g. VDD), while a part of that energy is delivered back to the other supply line (e.g. VSS) and visa versa. When the voltage supply source cannot sink energy, the voltage across the output capacitors of that voltage supply source will increase: the supply voltage is pumped to higher levels. The voltage increase caused by the pumping effect depends on:
Speaker impedance Supply voltage Audio signal frequency Value of decoupling capacitors on supply lines Source and sink currents of other channels.
The pumping effect should not cause a malfunction of either the audio amplier and/or the voltage supply source. For instance, this malfunction can be caused by triggering of the undervoltage or overvoltage protection or unbalance protection of the amplier. Best remedy for pumping effects is to use the TDA8920B in a mono full-bridge application or in case of stereo half-bridge application adapt the power supply (e.g. increase supply decoupling capacitors).
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13.8 Application schematic

Notes to the application schematic:
A solid ground plane around the switching amplier is necessary to prevent emission. 100 nF capacitors must be placed as close as possible to the power supply pins of the
TDA8920BTH.
The internal heat spreader of the TDA8920BTH is internally connected to VSS. The external heatsink must be connected to the ground plane. Use a thermal conductive electrically non-conductive Sil-Pad between the backside
of the TDA8920BTH and a small external heatsink.
The differential inputs enable the best system level audio performance with
unbalanced signal sources. In case of hum due to oating inputs, connect the shielding or source ground to the amplier ground. Jumpers J1 and J2 are open on set level and are closed on the stand-alone demo board.
Minimum total required capacity per power supply line is 3300 F.
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xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
Preliminary data sheet Rev. 01 1 October 2004
Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13356
R2
VDDP VDDA VDDP

R1 5.6 k R3 5.6 k
L1 BEAD CON1 +25 V VDD 1 GND 2 3 25 V VSS

C1 100 nF C2 47 F/35 V
10
C3 470 F/35 V
DZ1 5V6 S1 VSSP ON/OFF VSSA S2
R4 5.6 k C4
C7 100 nF
C5 47 F/35 V
C6 470 F/35 V
100 F/10 V
OPERATE/MUTE VDDP
C8
L2 BEAD
R5 10
VSSA
VSSP
VDDA
VSSA
C9 100 nF
R6 30 k C14 100 nF
47 F/ 63 V C15 100 nF C16 100 nF
FB GND
C12 100 nF
C13 100 nF
FB GND MODE
VDDP
C10 220 pF
VSSP
C11 220 pF
SINGLE ENDED OUTPUT FILTER VALUES LS1/LS2 L3/L4 C22/C31 2 4 6 8 10 H 22 H 33 H 47 H 1 F 680 nF 470 nF 330 nF
VDDA1
VDDP1
VSSA1
IN1
C17 1 nF
VSSP1
OSC
R8 5.6 k R10
C18 470 nF C20 470 nF C19 220 pF
IN1P 10 8
12
14
17 16 OUT1
C21 15 nF
R7 10
L3
R9 22 C22 C24 100 nF
OUT1P LS1 OUT1M
IN1M SGND1
9 11 U1
C23 1 nF C25 1 nF
5.6 k
15
BOOT1
FB GND SGND2
R11 5.6 k C26 470 nF C29 470 nF C28 220 pF
TDA8920BTH
2 5 21 OUT2
R13 10
IN2P
22
BOOT2 C27
15 nF
FB GND L4
OUT2M LS2
R14 22
IN2
C30 1 nF
R12 5.6 k
IN2M
4 3 VDDA2 1 VSSA2 13 PROT 19 n.c. 24 VSSD 18 STABI 23 VDDP2 20 VSSP2
OUT2P
C31 C40 220 pF C41 220 pF
FB GND
C34 100 nF
C35 100 nF
FB GND
C33 220 pF C36 100 nF
C37 100 nF
C38 100 nF
C39 100 nF
FB GND
C32 100 nF
TDA8920B
001aab224
VDDA
VSSA
VSSA
VSSP
VDDP
VSSP
VDDP
VSSP
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Fig 9. TDA8920BTH application schematic.
TDA8920B
13.9 Curves measured in reference design

102 (THD + N)/S (%) 10
001aab225
102 (THD + N)/S (%) 10
001aab226
1
(1)
1
(1)
101
(2)
101
(2)
102
(3)
102
(3)
103 102
101
10
102 103 Po (W)
103 102
101
10 Po (W)
102
Vp = 27 V; 2 3 SE conguration. (1) f = 6 kHz. (2) 1 kHz. (3) 100 Hz.
Vp = 27 V; 2 4 SE conguration. (1) f = 6 kHz. (2) 1 kHz. (3) 100 Hz.
Fig 10. (THD + N)/S as a function of output power; SE conguration with 2 3 load.
102 (THD + N)/S (%) 10
001aab227
Fig 11. (THD + N)/S as a function of output power; SE conguration with 2 4 load.
102 (THD + N)/S (%) 10
001aab228
101
(1) (2)
101
(1) (2)
102
(3)
102
(3)
103 102
101
10
102 103 Po (W)
103 102
101
10
102 103 Po (W)
Vp = 27 V; 1 6 BTL conguration. (1) f = 6 kHz. (2) 1 kHz. (3) 100 Hz.
Vp = 27 V; 1 8 BTL conguration. (1) f = 6 kHz. (2) 1 kHz. (3) 100 Hz.
Fig 12. (THD + N)/S as a function of output power; BTL conguration with 1 6 load.
Fig 13. (THD + N)/S as a function of output power; BTL conguration with 1 8 load.
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102 (THD + N)/S (%) 10
001aab229
102 (THD + N)/S (%) 10
001aab230
101
(1)
101
(1)
102
(2)
102
(2)
103 10
102
103
104 f (Hz)
105
103 10
102
103
104 f (Hz)
105
Vp = 27 V; 2 3 SE conguration. (1) Pout = 1 W. (2) Pout = 10 W.
Fig 14. (THD + N)/S as a function of frequency; SE conguration with 2 3 load.

102 (THD + N)/S (%) 10
001aab231
Fig 15. (THD + N)/S as a function of frequency; SE conguration with 2 4 load.

102 (THD + N)/S (%) 10
001aab232
101
(1)
101
(1)
102
(2)
102
(2)
103 10
102
103
104 f (Hz)
105
103 10
102
103
104 f (Hz)
105
Vp = 27 V; 1 6 BTL conguration. (1) Pout = 1 W. (2) Pout = 10 W.
Vp = 27 V; 1 8 BTL conguration. (1) Pout = 1 W. (2) Pout = 10 W.
Fig 16. (THD + N)/S as a function of frequency; BTL conguration with 1 6 load.
Fig 17. (THD + N)/S as a function of frequency; BTL conguration with 1 8 load.
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0 cs (dB) 20
001aab233
0 cs (dB) 20
001aab234
40
40
60
(1)
60
(1)
80
(2)
80
(2)
100 10
102
103
104 f (Hz)
105
100 10
102
103
104 f (Hz)
105
Fig 18. Channel separation as a function of frequency; SE conguration with 2 3 load.

32 Pdiss (W) 24
(1)
Fig 19. Channel separation as a function of frequency; SE conguration with 2 4 load.

100 (%) 80
(2) (4)
001aab235
(3)
001aab236
(1) (3)
60 16
(4) (2)
40
8 20
0 102
101
10
102 103 Po (W)
0 0 80 160 Po (W) 240
Vp = 27 V; f = 1 kHz. (1) 2 3 SE conguration. (2) 2 4 SE conguration. (3) 1 6 BTL conguration. (4) 1 8 BTL conguration.
Vp = 27 V; f = 1 kHz. (1) 2 3 SE conguration. (2) 2 4 SE conguration. (3) 1 6 BTL conguration. (4) 1 8 BTL conguration.
Fig 20. Power dissipation as a function of total output power.
Fig 21. Efciency as a function of total output power.
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200 Po (W) 160

(1)
001aab237
240
(1)
001aab238
Po (W)
(2)
(2)
160 120
(3) (4)
(3)
80
(4)
80
40
0 10 15 20 25 30 VS (V) 35
0 10 15 20 25 30 VS (V) 35
f = 1 kHz. (1) 1 6 BTL conguration. (2) 1 8 BTL conguration. (3) 2 3 SE conguration. (4) 2 4 SE conguration.
f = 1 kHz. (1) 1 6 BTL conguration. (2) 1 8 BTL conguration. (3) 2 3 SE conguration. (4) 2 4 SE conguration.
Fig 22. Output power as a function of supply voltage; THD + N = 0.5 %.

45 G (dB) 40
001aab239
Fig 23. Output power as a function of supply voltage; THD + N = 10 %.

45 G (dB) 40
(1)
001aab240
35
(1) (2)
35
(2)
30
(3) (4)
30
(3) (4)
25
25
20 10
102
103
104 f (Hz)
105
20 10
102
103
104 f (Hz)
105
Vi = 100 mV; Rs = 5.6 k; Ci = 330 pF; Vp = 27 V. (1) 1 8 BTL conguration. (2) 1 6 BTL conguration. (3) 2 4 BTL conguration. (4) 2 3 BTL conguration.
Vi = 100 mV; Rs = 0 ; Ci = 330 pF; Vp = 27 V. (1) 1 8 BTL conguration. (2) 1 6 BTL conguration. (3) 2 4 BTL conguration. (4) 2 3 BTL conguration.
Fig 24. Gain as a function of frequency; RS = 5.6 k and Ci = 330 pF.
Fig 25. Gain as a function of frequency; RS = 0 and Ci = 330 pF.
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TDA8920B
0 SVRR (dB) 20
001aab241
Vo (V)
10 1
001aab242
101 40
(1)
102 103
(2)
60
104 80 105 106 0 2 4 Vmode (V) 6
100 10
102
103
104 f (Hz)
105
Vp = 27 V; Vripple = 2 V (p-p). (1) both supply lines rippled. (2) one supply line rippled.
Vi = 100 mV; f = 1 kHz.
Fig 26. .SVRR as a function of frequency.

120 S/N (dB)
(1)
Fig 27. .Output voltage as a function of mode voltage.

001aab243
80
(2)
40
0 102
101
10
102 103 Po (W)
Vp = 27 V; Rs = 5.6 k; 20 kHz AES17 lter. (1) 2 3 SE conguration and 1 6 BTL conguration. (2) 2 4 SE conguration and 1 8 BTL conguration.
Fig 28. S/N ratio as a function of output power.
14. Test information

14.1 Quality information
The General Quality Specication for Integrated Circuits, SNW-FQ-611 is applicable.
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TDA8920B
15. Package outline

HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3
E D x
A X
c y E2 HE v M A
D1 D2 1 pin 1 index Q A2 E1 A4 Lp detail X 24 Z e bp 13 w M (A3) A 12
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. 3.5 3.5 3.2 A3 0.35 A4(1) bp c D(2) D1 D2 1.1 0.9 E(2) 11.1 10.9 E1 6.2 5.8 E2 2.9 2.5 e 1 HE 14.5 13.9 Lp 1.1 0.8 Q 1.7 1.5 v w x y Z 2.7 2.2 8 0
+0.08 0.53 0.32 16.0 13.0 0.04 0.40 0.23 15.8 12.6
0.25 0.25 0.03 0.07
Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT566-3 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 03-02-18 03-07-23
Fig 29. HSOP24 package outline.

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TDA8920B
DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm)
SOT411-1
non-concave x D Dh
Eh
view B: mounting base side A2
A5 A4
B j
E2 E
E1
L2 L1 L3
L 1 Z e e1 w M 23
Q m
c e2
v M
bp
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT A 2 mm A4 A5 bp c D (1) d D h E (1) e e1 e2 Eh E1 E2 j L L1 L2 L3 m Q v w x
Z (1)
12.2 4.6 1.15 1.65 0.75 0.55 30.4 28.0 12 2.54 1.27 5.08 11.8 4.3 0.85 1.35 0.60 0.35 29.9 27.5
6 10.15 6.2 1.85 3.6 9.85 5.8 1.65 2.8
14 10.7 2.4 1.43 2.1 4.3 0.6 0.25 0.03 45 13 9.9 1.6 0.78 1.8
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT411-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 98-02-20 02-04-24
Fig 30. DBS23P package outline.

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TDA8920B
16. Soldering
16.1 Introduction
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for ne pitch SMDs. In these situations reow soldering is recommended. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing.
16.2 Through-hole mount packages

16.2.1 Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specied maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
16.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds.
16.3 Surface mount packages

16.3.1 Reow soldering
Reow soldering requires solder paste (a suspension of ne solder particles, ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
below 225 C (SnPb process) or below 245 C (Pb-free process)

for all BGA, HTSSON..T and SSOP..T packages
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TDA8920B
for packages with a thickness 2.5 mm for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
16.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specically developed. If wave soldering is used the following conditions must be observed for optimal results:
Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be xed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated ux will eliminate the need for removal of corrosive residues in most applications.
16.3.3 Manual soldering

Fix the component by rst soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the at part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
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16.4 Package related soldering information

Table 11: Mounting Through-hole mount Through-hole-surface mount Surface mount Suitability of IC packages for wave, reow and dipping soldering methods Package [1] CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP [4] BGA, HTSSON..T [5], LBGA, LFBGA, SQFP, SSOP..T [5], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [7], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [10], WQCCN..L [10]
[1] [2]
Soldering method Wave suitable suitable [3] not suitable not suitable Reow [2] not suitable suitable Dipping suitable
not suitable [6]
suitable
suitable not not recommended [7] [8] recommended [9]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales ofce. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. Hot bar soldering or manual soldering is suitable for PMFP packages. These transparent plastic packages are extremely sensitive to reow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is denitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is denitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[3] [4] [5]
[6]
[7] [8] [9]
[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on ex foil. However, the image sensor package can be mounted by the client on a ex foil by using a hot bar soldering process. The appropriate soldering prole can be provided on request.
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17. Revision history

Table 12: Revision history Release date 20041001 Data sheet status Preliminary data sheet Change notice Order number 9397 750 13356 Supersedes Document ID TDA8920B_1
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18. Data sheet status

Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualication Denition This data sheet contains data from the objective specication for product development. Philips Semiconductors reserves the right to change the specication in any manner without notice. This data sheet contains data from the preliminary specication. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specication without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specication. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notication (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
19. Denitions
Short-form specication The data in a short-form specication is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values denition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specication is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specied use without further testing or modication.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production), relevant changes will be communicated via a Customer Product/Process Change Notication (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specied.
21. Trademarks
Sil-Pad is a registered trademark of The Bergquist Company.
20. Disclaimers
Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
22. Contact information

For additional information, please visit: http://www.semiconductors.philips.com For sales ofce addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13356
33 of 34
TDA8920B
23. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.4 9 10 11 12 12.1 12.2 12.3 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 14 14.1 15 16 16.1 16.2 16.2.1 16.2.2 16.3 16.3.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pulse width modulation frequency . . . . . . . . . . 8 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OverTemperature Protection (OTP) . . . . . . . . . 8 OverCurrent Protection (OCP) . . . . . . . . . . . . . 8 Window Protection (WP). . . . . . . . . . . . . . . . . 10 Supply voltage protections . . . . . . . . . . . . . . . 10 Differential audio inputs . . . . . . . . . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal characteristics. . . . . . . . . . . . . . . . . . 12 Static characteristics. . . . . . . . . . . . . . . . . . . . 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Switching characteristics . . . . . . . . . . . . . . . . 13 Stereo and dual SE application . . . . . . . . . . . 14 Mono BTL application . . . . . . . . . . . . . . . . . . . 15 Application information. . . . . . . . . . . . . . . . . . 15 BTL application . . . . . . . . . . . . . . . . . . . . . . . . 15 MODE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output power estimation. . . . . . . . . . . . . . . . . 16 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16 Heatsink requirements . . . . . . . . . . . . . . . . . . 17 Output current limiting. . . . . . . . . . . . . . . . . . . 18 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 19 Application schematic . . . . . . . . . . . . . . . . . . . 20 Curves measured in reference design . . . . . . 22 Test information . . . . . . . . . . . . . . . . . . . . . . . . 26 Quality information . . . . . . . . . . . . . . . . . . . . . 26 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 27 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Through-hole mount packages . . . . . . . . . . . . 29 Soldering by dipping or by solder wave . . . . . 29 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 29 Surface mount packages . . . . . . . . . . . . . . . . 29 Reow soldering . . . . . . . . . . . . . . . . . . . . . . . 29 16.3.2 16.3.3 16.4 17 18 19 20 21 22 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 30 30 31 32 33 33 33 33 33
Koninklijke Philips Electronics N.V. 2004

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 1 October 2004 Document order number: 9397 750 13356
Published in The Netherlands

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100 WATTS AUDIO DIGITAL AMPLIFIER

SITI HAJAR BINTI HAZIZI

UNIVERSITI TEKNOLOGI MALAYSIA

PSZ 19:16 (Pind. 1/97)

UNIVERSITI TEKNOLOGI MALAYSIA

BORANG PENGESAHAN STATUS TESIS

100 WATTS AUDIO DIGITAL AMPLIFIER SESI PENGAJIAN: 2007/2008

SITI HAJAR BINTI HAZIZI (HURUF BESAR)

(TANDATANGAN PENYELIA) PUAN ISMAWATI BT. ABDUL GHANI Nama Penyelia

5th DCEMBER 2007

Signature Name of Supervisor Date .

.. PUAN ISMAWATI BINTI ABDUL GHANI 5th DECEMBER 2007

100 WATTS AUDIO DIGITAL AMPLIFIER

SITI HAJAR BINTI HAZIZI

Faculty of Electrical Engineering University Technology Malaysia

Signature Name Date

: ___________________________________ : SITI HAJAR BINTI HAZIZI : 5th DECEMBER 2007

PAGE iii vi v vi vii viii xi xii xiv 1 1 5 5 6 7 5 8 9 10 11

Low Pass Filter Theoretical analysis of class D operation

METHODOLOGY 3.1 Research Methodology 3.2 Circuit and Hardware Design

4.3 Pulse Width Modulation frequency

4.7 Signal to Noise ratio

LIST OF SYMBOLS AND ABBREVIATION

A C CMRR DC dB f F hZ k m M n R V L RMS Vpp SNR OSC

TITLE GANTT Chart PSM 1 and PSM 2 TDA8920BJ DATASHEET

Figure 1.2: Class D Topology

Figure 1.1 Block Diagram of the project.

2.1 Chip TDA8920BJ

Figure 2.1: Block Diagram

2.1.2 Mode Selection

Figure 2.2: Mode select drive input circuit

Figure 2.3: Mode select transfer characteristic

2.2 Pulse Width Modulation

Figure 2.5: Two-Level vs. Three-Level PWM

Figure 2.6: PWM Comparator

2.3 Low Pass Filter

Figure 2.7 Amplitude Response of Butterworth Low Pass Filter

Figure 2.8: Gain responses of Chebyshev Low Pass Filter

2.4 Theoretical analysis of class D operation

Figure 2.9: Loop Filter

Design & Simulate Circuit

Compare Results for Calculation & Simulation

Figure 3.1: Methodology for the Project

Figure 3.2: Block diagram

Efficiency = OutputPower / InputPower

Figure 4.1: current limiting

4.2 Mode Selector

Figure 4.3: Mode switching directly from standby-operating

Figure 4.4: oscillator

Figure 4.6: Bode Plot for 1 Ohm load

Figure 4.7: Bode Plot for 2 Ohm load

Figure 4.8: Bode Plot for 4 Ohm load

Po(1%) = [(RL / RL+0.4)VP(1-tminfosc) 2RL]

Figure 4.10: Input vs. Output

1 http://www.cpemma.co.uk/pwm.html 2 www.xtant.com/html/products/xtant1.li.cfm 3 Class D Audio Amplifier, WPI MQP,2003 4 http://www.extron.com

GANTT CHART PSM 1

GANTT CHART PSM 2

4. Quick reference data

Stereo single-ended conguration Po 110 86 W W