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Document # : SAED_90nm_LO_DR_01
Revision
: 1.2
Technology : SAED90nm
Process
: SAED90nm 1P9M 1.2v / 2.5v / 3.3v
Rev. 1.2
Page 1 of 24
Rev. 1.2
Page 2 of 24
Rev. 1.2
Page 3 of 24
Rev. 1.2
Page 4 of 24
1. Introduction
This document is the part of SAED_EDK90 Design Kit documentation.
These design rules are free from intellectual property restrictions. It was considered to develop
90nm rules but sizes can be larger by 5-20% than in real processes to provide further portability
of projects designed by this design rules to real processes (TSMC90nm or IBM90nm).
As basis for layer names and design rules SCN6M (TSMC 0.18) process was used described in
the following mosis site:
http://mosis.com/Technical/Layermaps/lm-scmos_scn6m.html
as well as documentation (manual_lite_v31.pdf) available at www.microwind.org .
Some layers such as dummy, marking and text, have been added to the layer map. Design rule
values for 90nm process are obtained by scaling available rules values.
Rev. 1.2
Page 5 of 24
2. Layer Map
Layer
#
Data
type
Tape
Out
Layer
Drawing or
Composite
Layer
Layer name
in Tech/Map
File
1
2
0
0
YES
YES
Drawing
Drawing
NWELL
DNW
NWELLi
DNWi
NWELLi
DNWi
YES
Drawing
DIFF
DIFFi
DIFFi
YES
Drawing
DDMY
DDMYi
DDMYi
4
5
6
7
0
0
0
0
YES
YES
YES
YES
Drawing
Drawing
Drawing
Drawing
PIMP
NIMP
DIFF_25
PAD
PIMPi
NIMPi
DIFF_25i
PADi
PIMPi
NIMPi
DIFF_25i
PADi
YES
Drawing
ESD_25
ESD_25
ESD_25
YES
Drawing
SBLK
SBLKi
SBLKi
10
YES
Drawing
PO
POi
POi
10
YES
Drawing
PODMY
PODMYi
PODMYi
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
Drawing
M1
M1DMY
M2
M2DMY
M3
M3DMY
M4
M4DMY
M5
M5DMY
M6
M6DMY
M7
M7DMY
M8
M8DMY
M9
M9DMY
CO
VIA1
VIA2
VIA3
VIA4
VIA5
VIA6
VIA7
VIA8
HVTIMP
LVTIMP
M1PIN
M2PIN
M3PIN
M4PIN
M5PIN
M6PIN
M7PIN
M8PIN
M9PIN
M1i
M1DMYi
M2i
M2DMYi
M3i
M3DMYi
M4i
M4DMYi
M5i
M5DMYi
M6i
M6DMYi
M7i
M7DMYi
M8i
M8DMYi
M9i
M9DMYi
COi
VIA1i
VIA2i
VIA3i
VIA4i
VIA5i
VIA6i
VIA7i
VIA8i
HVTIMPi
LVTIMPi
M1PIN
M2PIN
M3PIN
M4PIN
M5PIN
M6PIN
M7PIN
M8PIN
M9PIN
M1i
M1DMYi
M2i
M2DMYi
M3i
M3DMYi
M4i
M4DMYi
M5i
M5DMYi
M6i
M6DMYi
M7i
M7DMYi
M8i
M8DMYi
M9i
M9DMYi
COi
VIA1i
VIA2i
VIA3i
VIA4i
VIA5i
VIA6i
VIA7i
VIA8i
HVTIMPi
LVTIMPi
M1PIN
M2PIN
M3PIN
M4PIN
M5PIN
M6PIN
M7PIN
M8PIN
M9PIN
Rev. 1.2
Page 6 of 24
Data
type
Tape
Out
Layer
Drawing or
Composite
Layer
40
NO
N/A
41
NO
Drawing
42
NO
N/A
43
NO
44
45
Layer name
in Tech/Map
File
HOTNWL
HOTNWLi
HOTNWLi
Drawing
DIOD
DIODi
DIODi
NO
Drawing
BJTDMY
BJTDMYi
BJTDMYi
NO
Drawing
RNW
RNWi
RNWi
46
NO
Drawing
RPOLY
RPOLYi
RPOLYi
47
NO
Drawing
RDIFF
RDIFFi
RDIFFi
48
49
50
0
0
0
NO
NO
NO
Drawing
Drawing
Drawing
LOGO
IP
prBoundary
LOGO
IP
51
NO
Drawing
RM1
RM1i
RM1i
52
NO
Drawing
RM2
RM2i
RM2i
53
NO
Drawing
RM3
RM3i
RM3i
54
NO
Drawing
RM4
RM4i
RM4i
55
NO
Drawing
RM5
RM5i
RM5i
56
NO
Drawing
RM6
RM6i
RM6i
57
NO
Drawing
RM7
RM7i
RM7i
58
NO
Drawing
RM8
RM8i
RM8i
59
NO
Drawing
RM9
RM9i
RM9i
60
NO
N/A
61
NO
Drawing
DM1EXCL
DM1EXCLi
62
NO
Drawing
DM2EXCL
DM2EXCLi
63
NO
Drawing
DM3EXCL
DM3EXCLi
64
NO
Drawing
DM4EXCL
DM4EXCLi
65
NO
Drawing
DM5EXCL
DM5EXCLi
66
NO
Drawing
DM6EXCL
DM6EXCLi
Rev. 1.2
Page 7 of 24
Data
type
Tape
Out
Layer
Drawing or
Composite
Layer
Layer name
in Tech/Map
File
67
NO
Drawing
DM7EXCL
DM7EXCLi
68
NO
Drawing
DM8EXCL
DM8EXCLi
69
NO
Drawing
DM9EXCL
DM9EXCLi
Rev. 1.2
Page 8 of 24
3. Design Rules
Definitions of layout geometrical terminology
d
b
a enclosure
b space
c overlap
d width
e extension
Figure 1. Definitions of layout geometrical terminology
a distance between inside of the edge of 1st layer and outside of the edge of 2nd layer
b distance between outside of the edge of 1st layer and outside of the edge of 2nd layer
c distance between inside of the edge of 1st layer and inside of the edge of 2nd layer
d distance between inside parts of the same layer
e distance between inside of the edge of 1st layer and outside of the edge of 2nd layer
- Resulting Layer
Figure 2. AND
- Resulting Layer
Figure 3. OR
2011 SYNOPSYS ARMENIA Educational Department
Rev. 1.2
Page 9 of 24
L1
L2
Figure 5. INSIDE
Figure 6. OUTSIDE
Rev. 1.2
Page 10 of 24
Mark
0.65
0.65
1.2
a
b
c
Rule description
Mark
Minimum width
Minimum spacing, Deep_N_Well to Deep_N_Well
Minimum spacing, Deep_N_Well to unrelated N_Well
Minimum spacing, external N+Active to Deep_N_Well
Minimum spacing, P+Active in N_Well to its Deep_N_Well
Minimum enclosure, N+Active by isolated P-well
Minimum enclosure, N_Well beyond Deep_N_Well edge
Minimum overlap, N_Well over Deep_N_Well edge
3.5
5
3.5
2
1
0.7
1.5
0.5
a
b
c
d
e
f
g
h
Rule #
Rule description
NWELL.W.1
NWELL.S.1
NWELL.S.2
Minimum width
Minimum spacing between wells at same potential
Minimum spacing between wells at different potential
V2
V1
V1
N_well
N_well
N_well
a
Figure 7. NWELL
Table 2. DNW Rules
Rule #
DNW.W.1
DNW.S.1
DNW.S.2
DNW.S.3
DNW.S.4
DNW.E.1
DNW.E.2
DNW.O.1
h
f
b
a
c
d
N_Well
N+ Active
P_Well
P+ Active
Deep_N_Well
Figure 8. DNW
2011 SYNOPSYS ARMENIA Educational Department
Rev. 1.2
Page 11 of 24
Rule description
Minimum width
Minimum spacing
Minimum spacing in DIFF_25
Source/drain active to well edge (min enclosure by well)
Substrate/well contact diff to well edge (min enclosure by well)
DIFF w/o IMP is not allowed
N
a DIFF
N
DIFF
Mark
0.12
0.14
0.18
0.24
0.2
a
b
c
d
e
P
DIFF
NIMP
d
P-Well
N-Well
PIMP
e
e
N
a
P
DIFF
P
DIFF
PIMP
DIFF
NIMP
Figure 9. DIFF
Table 4. PIMP Rules
Rule #
PIMP.W.1
PIMP.E.1
PIMP.E.2
PIMP.E.3
PIMP.S.1
PIMP.S.2
PIMP.S.3
PIMP.O.1
Rule description
Minimum width
Enclosure of P+Active
Enclosure of PTAP
Poly enclosure
Minimum space
Minimum space to butted N+Active
Minimum space to N+Active in PWELL
Minimum active overlap
Mark
0.24
0.14
0.04
0.24
0
0.14
0.14
a
b
c
d
e
f
g
h
Mark
0.24
0.14
0.04
a
b
c
d
e
Rule description
Minimum width
Enclosure of N+Active
Enclosure of NTAP
Poly enclosure
Minimum space
0.24
Rev. 1.2
Page 12 of 24
0
0.14
0.14
a PIMP*
a
e
Contact
f
g
h
NIMP
d
Poly
e
g
PIMP
Active
NIMP*
* The same rules apply to N+_inplant
reversed.
Figure 10. PIMP, NIMP
Rule description
Minimum width
Minimum Spacing
Minimum DIFF enclosure
Minimum space to external DIFF
DIFF_25
DIFF_25
Active
Mark
0.66
0.66
0.3
0.3
a
b
c
d
Active
Active
d
a
c
Figure 11. DIFF_25
Rev. 1.2
Page 13 of 24
Rule description
PAD.W.1
PAD.E.1
PAD.S.1
PAD.S.2
Mark
60
2
10
3
a
b
c
d
MT
PAD
b
MT
PAD
b
MT
Rule description
Minimum SBLK width
Minimum SBLK spacing
Minimum spacing, SBLK to contact (no contacts allowed
inside SBLK)
Minimum spacing, SBLK to external diff
Minimum spacing, SBLK to external poly
Minimum spacing of poly resistors (in a single SBLK
region)
Minimum spacing, SBLK to poly (in a single active region)
Resistor is poly inside SBLK: poly ends stick out for
contacts the entire resistor must be outside well and
over field
Minimum poly width in unsalicided resistor
Minimum SBLK extension of poly or active
Minimum poly extension of SBLK
Rev. 1.2
Mark
0.44
0.44
0.24
a
b
c
0.24
0.3
0.3
d
e
f
0.4
0.4
0.24
0.24
h
i
j
Page 14 of 24
SBLK
POLY-1
i
c
Contact
f
d
g
SBLK
ACTIVE
i
c
Rev. 1.2
Page 15 of 24
Mark
0.1
0.3
0.18
0.2
0.18
0.16
0.05
a
b
c
d
e
f
g
Rule description
Mark
Minimum width
Minimum spacing
Minimum spacing when either metal line is wider than 5 m
0.14
0.14
1.5
a
b
c
Rule #
PO.W.1
PO.W.2
PO.S.1
PO.S.2
PO.EX.1
PO.EX.2
PO.S.3
PO.G.1
Rule description
Minimum width
Minimum poly width in a thick oxide gate
Minimum spacing over field
Minimum spacing over active
Minimum gate extension of active (end cap)
Minimum active extension of gate
Minimum field poly to DIFF
45 degree and 90 degree bent gate are not allowed
Active
g
b
c
Poly
d
Poly
e
f
Active
Figure 14. PO
Table 10. M1 Rules
Rule #
M1.W.1
M1.S.1
M1.S.2
Rev. 1.2
Page 16 of 24
Wide
M1
5m
M1
M1
Figure 15. M1
Table 11. MX Rules, where X=2...T-1
Rule description
Mark
Minimum width
Minimum spacing
Minimum spacing when either metal line is wider than 5 m
0.16
0.16
1.5
a
b
c
Rule #
MX.W.1
MX.S.1
MX.S.2
Wide
MX
5m
MX
MX
Figure 16. MX
Rev. 1.2
Page 17 of 24
Mark
Minimum width
Minimum spacing
Minimum spacing when either metal line is wider than 5 m
0.45
0.45
1.5
a
b
c
Rule #
MT.W.1
MT.S.1
MT.S.2
Wide
MT
5m
MT
MT
Figure 17. MT
Table 13. Metal Density Rules, where X=2...T-1
Rule #
M1.DN.1
M1.DN.2
MX.DN.1
MX.DN.2
MT.DN.1
MT.DN.2
Rule description
Rule
Rev. 1.2
10% in 50x50
60% in 100x100
90%
15% in 50x50
70% in 100x100
90%
15% in 50x50
60% in 100x100
90%
Page 18 of 24
Rule description
CO.W.1
CO.S.1
CO.S.2
CO.S.3
CO.E.1
CO.E.2
CO.E.3
CO.E.4
CO.E.5
CO.E.6
CO.E.7
Mark
0.13
0.13
0.12
0.12
0.04
0.04
0.05
0.05
0.06
0.005
a
b
c
d
e
f
g
h
i
j
0.05
Poly
Poly
h
c
PIMP
b
ii
DIFF
NIMP
d
k
M1
e
M1
j
k
k
Figure 18. CO
Rev. 1.2
Page 19 of 24
Mark
0.14
0.16
0.005
0.05
a
b
c
d
Rule description
Exact size
Minimum viaX spacing
Minimum viaX enclosure by MX and MX+1
Minimum viaX enclosure by MX and MX+1 at end of line
a
b
ViaX
ViaX
ViaX
MX/MX+1
c
Figure 19. VIAX
Rule description
Exact size
Minimum viaX spacing
Minimum VIAT enclosure by MT and MT-1
Minimum VIAT enclosure by MT and MT-1 at end of line
Mark
0.36
0.34
0.05
0.08
a
b
c
d
a
ViaT
ViaT
ViaT
MT/MT-1
c
Figure 20. VIAT
Rule description
Minimum width
Minimum spacing
Minimum enclosure
Rev. 1.2
Mark
0.24
0.24
0.14
a
b
c
Page 20 of 24
Rule description
Minimum width
Minimum spacing
Minimum enclosure
Mark
0.24
0.24
0.14
a
b
c
HVT/LVT
Active
c
b
Active
Rev. 1.2
Page 21 of 24
Sheet Resistance
Thicknees (nm)
0.009
0.009
0.009
0.009
0.009
0.009
0.009
0.009
0.028
280
280
280
280
280
280
280
280
900
Dielectrics
Name
GOX
FOX
D1
D2
D3
D4
D5
D6
D7
D8
D9
PASS
Thicknees (nm)
3.9
3.9
3.9
3.9
3.9
3.9
3.9
3.9
3.9
3.9
3.9
3.9
2
200
900
900
900
900
900
900
900
900
900
5000
Rev. 1.2
Page 22 of 24
PASS (5.00)
M9
Er=3.9
VIA8
D9 (0.9)
M8
Er=3.9
VIA7
VIA6
M7
Er=3.9
VIA5
M6
Er=3.9
VIA4
M5
Er=3.
D8 (0.9)
D7 (0.9)
D6 (0.9)
D5 (0.9)
M4
Er=3.9
VIA3
VIA2
M3
Er=3.9
VIA1
M2
Er=3.9
DIFFCONT
POLYCONT
n+
Substrate
D3 (0.9)
D2 (0.9)
M1
Er=3.9
Gate
Er=3.9
D4 (0.9)
n+
D1 (0.9)
FOX (0.02)
GOX
Rev. 1.2
Page 23 of 24
4. Revision History
Table 19. Revision History
Revision
A1.2
Date
11/07/2009
Change
Density rules added
Rev. 1.2
Page 24 of 24