CONTENTS

1) Introduction.01
1.1. Need for High speed I/O01
1.2. Basic Operation of SERDES.........02
1.3. Phase Locked Loop...............................................................................................03
1.4. Importance of Reference Clock.............................................................................04

2) Source Synchronous Interfaces ....05

2.1 Parallel Data Bus ........................05
2.2 Source Synchronous Interfaces ..06
2.2.1 Reducing the no of I/O pins.06
2.2.2 Clock Forwarding.06
2.2.3 Higher Speed Source Synchronous Interfaces 08
2.2.4 Differential Signals..08

3) High Speed SERDES10

3.1. Serializer/Deserializer blocks....11
3.2. Equalizers.....................................11
3.3. Clock and Data recovery......................................................................................12
3.4. Differential Driver................................................................................................12
3.5. Differential Receiver...........................................................................................12
3.6. Phase Locked Loop..............................................................................................12

4) SERDES Architectures..14
4.1. Parallel clock SERDES. ..14
4.2. Embedded clock SERDES ..........15
4.3. 8b/10b SERDES..................................................................................................15
4.4. FPGA-Attach SERDES......................................................................................16

5) Conclusions18

6) References..19

LIST OF FIGURES
Fig.1.1 The Serialization Process. 02
Fig.2.1 Parallel data bus between two chips. ...05
Fig.2.2 Serializing the data to reduce pin counts..06
Fig.2.3 High speed clock data with clock forwarding..07
Fig.2.4 Single data rate and double data rate clocks07
Fig.2.5 Example of serial data eye...08
Fig 2.6 Multiple sets of data with separate high speed clocks.09
Fig.3.1 Basic block diagram of typical high speed SERDES..10
Fig.3.2 Signal distortion for typical channel application.11
Fig.3.3 Typical channel application with equalization at the transmitter12
Fig.4.1 Parallel clock serializer coding example.14
Fig.4.2 18-Bit Embedded-clock-Bits-serializer coding example 15
Fig.4.3 8b/10b-Serializer coding example.................15
Fig.4.4 FPGA-Attach serializer optimizes the analog intensive functions example...16

ABSTRACT
The current high-growth nature of digital communications demands higher speed serial
communication circuits. Present day technologies barely manage to keep up with this
demand.A Serializer/Deserializer is a pair of functional blocks commonly used in high speed
communications to compensate for limited input/output. SERDES (Serializers/Deserializers) are
devices that can take wide bit-width, single-ended signal buses and compress them to a few,
typically one, differential signal that switches at a much higher frequency rate than the wide
single-ended data bus. SERDES enable the movement of a large amount of data point-to-point
while reducing the complexity, cost, power, and board space usage associated with having to
implement wide parallel data buses. SERDES usage becomes especially beneficial as the
frequency rate of parallel data buses moves beyond 500 MHz (1000 Mbps).

A SEMINAR REPORT ON

INTRODUCTION TO SERDES

By
S Subba Reddy
II M.Tech (VLSI-SD)
(Roll No: 114565)

Department of Electronics and Communication Engineering

NATIONAL INSTITUTE OF TECHNOLOGY, WARANGAL
(DEEMED UNIVERSITY)
ANDHRA PRADESH-506004
2011- 2013

ACKNOWLEDGEMENTS

I wish my deep sense of gratitude to Prof. K.S.R.Krishna Prasad, department of

electronics and communication engineering, National Institute of Technology Warangal for his
help, motivating thoughts and kindness throughout the course work. He has been the basic source
of inspiration.
I would like to thank Dr. Patri Sreehari Rao, faculty, department of electronics and
communication engineering, National Institute of Technology Warangal for his invaluable
guidance and motivation. His devotion in the field of VLSI has been a great inspiration in
finishing my masters studies.
I want to express my gratitude to Smt. Dr. Lakshmi. B, Head of the electronics and
communication engineering department, national institute of technology Warangal.