GATE DRIVERS

THE POWER MANAGEMENT LEADER

By A. Merello, A. Rugginenti and M. Grasso, International Rectifier

Using Monolithic High Voltage Gate Drivers

time since they are limited by the requirement to refresh the charge in the bootstrap capacitor. Proper capacitor choice can reduce drastically these limitations. Bootstrap capacitor sizing To size the bootstrap capacitor, the first step is to establish the minimum voltage drop (VBS) that we have to guarantee when the high side IGBT is on. If VGEmin is the minimum gate emitter voltage to maintain, the voltage drop must be: VBS VCC VF VGEmin VCEon under the condition: VGEmin > VBSUV

INTRODUCTION
The purpose of this paper is to highlight the most common subjects driving a half bridge power stage in motor drive applications (with monolithic IC gate driver) and to suggest appropriate solutions to solve the issues. In the following sections different topics are discussed: the sizing of some fundamental components, as bootstrap circuit and on/off gate resistors; the half bridge parasitic elements are presented with their effects and some possible solutions are proposed. In the end section some layout tips are presented. All the situations and the solutions proposed are, unless otherwise specified, for a typical IR monolithic gate driver with floating bootstrap supply.

BOOTSTRAP CIRCUIT

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where V is the IC voltage supply, VF is bootstrap diode The bootstrap supply is formed by a diode and a capacitor Using monolithic high voltage gate drivers CC forward voltage, VCEon is emittercollector voltage of low side connected as in figure 1. IGBT and VBSUV- is the high-side supply undervoltage negative BOOTSTRAP CIRCUIT going threshold. This method has the advantage of being simple and low The bootstrap supply is formed by a diode and a capacitor connected as in figure 1. Now we must consider the influencing factors contributing cost but may force some limitations on duty-cycle and onVBS to decrease:
bootstrap resistor bootstrap diode DC+ Rboot VF

VCC

VB

VBS

bootstrap capacitor

VGE ILOAD

VCC

VS

motor

VCEon VFP

IGBT turn on required Gate charge (QG); IGBT gate-source leakage current (ILK_GE); Floating section quiescent current (IQBS); Floating section leakage current (ILK) Bootstrap diode leakage current (ILK_DIODE); Desat diode bias when on (IDS- ) Charge required by the internal level shifters (QLS); Bootstrap capacitor leakage current (ILK_CAP); High side on time (THON). ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are used. It is strongly recommend using at least one low ESR ceramic
DT04-04

DC-

Figure 1: bootstrap supply schematic

This method has the advantage of being simple and low cost but may force some limitations on Foron-time more information in North America call +1 requirement 310 252 7105, in call +49 6102 884 duty-cycle and since they are limited by the toEurope refresh the charge in311, theor visit us at www.irf.com bootstrap capacitor. Proper capacitor choice can reduce drastically these limitations.

Bootstrap capacitor sizing

Using monolithic high voltage gate drivers

Bootstrap diode leakage current (ILK_DIODE); Desat diode bias when on (IDS- ) Charge required by Voltage the internal Gate level shifters (QLS); Monolithic High Drivers Bootstrap capacitor leakage current (ILK_CAP); High side on time (THON).

Using

ILK_CAP is only relevant when using anand electrolytic capacitor and may can be ignored if otherformulas. types of capacitor (paralleling electrolytic low ESR ceramic the above capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor result in an efficient solution). (paralleling electrolytic and low ESR ceramic may result in an efficient solution). 2. This kind of bootstrap sizing approach does not take into Then have: account neither the duty cycle of the PWM, nor the funda Thenwe we have: mental frequency QTOT = QG + QLS + (ILK _ GE + IQBS + ILK + ILK _ DIODE + ILK _ CAP + IDS ) THON DT04-4 revA of the current. It considers only the amount of charge that is needed when the high voltage side QTOT = QG +QLS + (ILK _GE + IQBS + ILK + ILK _DIODE + ILK _CAP + IDS ) THON The size of bootstrap capacitor is: Using gate drivers of the driver is floating and IGBT gate is driven once. Theminimum minimum size of bootstrap capacitor is: monolithic high voltage Considerations on PWM duty cycle, kind of modulation (six Bootstrap diode leakage current (ILK_DIODE); QTOT CBOOT min = ) Desat diode bias when on ( I DSstep, 12-step, sine-wave) must be considered with their own VBS Charge required by the internal level shifters (QLS); peculiarity to achieve best bootstrap circuit sizing. Bootstrap capacitor leakage current (ILK_CAP); Anexample follows: ). High side on time ( T HON An example follows: ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if gate other types of about bootstrap circuit Considerations a) using a 25A @ 125C IGBT (IRGP30B120KD) and a high voltage half-bridge driver capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor (IR2214): a) using a 25A @ 125C IGBT (IRGP30B120KD) and aefficient high volt(paralleling electrolytic and low ESR ceramic may result in an solution). a. Voltage ripple age half-bridge gate driver (IR2214): Then = 800 A (Datasheet IR2214); Iwe QBShave: (Datasheet IR2214); ILK = 50 A = 20 nC; Q LS IQBS = 800 A (Datasheet IR2214); (Datasheet IRGP30B120KD); QG = 160 nC The size of bootstrap capacitor is: minimum ILK = 50 IR2214); = A 100(Datasheet nA (Datasheet IRGP30B120KD); ILK_GE = 100 (with reverse recovery time <100 ns); ILK_DIODE Q = 20 nC; QA = 160 nC (Datasheet IRGP30B120KD); QTOT G CBOOT LS min = =V 0 (neglected for ceramic capacitor); ILK_CAP BS ILK_GE = 100 nA (Datasheet IRGP30B120KD); (Datasheet IR2214); IDS- = 150 A = 100 An example 100 s.A (with reverse recovery time <100 ns); ILK_DIODE THON = follows:
QTOT = QG + QLS + (I LK _ GE + IQBS + ILK + ILK _ DIODE + I LK _ CAP + IDS ) THON

Three different situations can occur in the bootstrap capacitor charging (see figure 1): - ILOAD < 0; the load current flows in the low side IGBT displaying relevant VCEon
BS CC F

LK_CAP a) using And: a 25A @ 125C IGBT (IRGP30B120KD) and a high voltage half-bridge gate driver (IR2214): I - = 150 A (Datasheet IR2214); V =V V

= 0 (neglected for ceramic capacitor);

V And: CEonmax
GEmin

100 s. = A 15 V IT V= CC = 800 (Datasheet IR2214); QBS HON 1V 50 A (Datasheet IR2214); ILK = V F= nC; QLS = V20 CEonmax = 3.1 V And: 160 nC (Datasheet IRGP30B120KD); QG =V GEmin = 10.5 V (Datasheet IRGP30B120KD); ILK_GE = 100 nA (with reverse recovery time <100 ns); ILK_DIODE = 100 A the maximum voltage drop V BS becomes 0V (neglected for ceramic capacitor); IV == 15 LK_CAP CC (Datasheet IR2214); IDS- = 150 A V == 1 V V VF VGEmin VCEon = 15V 1V 10.5 V 3.1V = 0.4 V 100 s. T F V HON BS CC = 3.1 V
VCC = 15 V V nC V = 1290 C VF = 3.1 V = 725 nF BOOT CEonmax the maximum voltage drop 0. 4 V VGEmin = 10.5 V

DS

VCEon

In this case we have the lowest value for VBS. This represents the worst case for the bootstrap capacitor sizing. When the IGBT is turned off the Vs node is pushed up by the load current until the high side freewheeling diode gets forwarded biased - ILOAD = 0; the IGBT is not loaded while being on and VCE can be neglected VBS =VCC VF - ILOAD > 0; the load current flows through the freewheeling diode 3 VBS =VCC VF +VFP In this case we have the highest value for VBS. Turning on the high side IGBT, ILOAD flows into it and VS is pulled up.
3

And Vthe bootstrap = 10.5 Vcapacitor is:

VBS becomes

NOTES: the maximum voltage drop VBS becomes

VBS VCC VF VGEmin VCEon=15V 1V 10.5V 3.1V = 0.4V

VBS VCC VF VGEmin VCEon = 15V 1V 10.5 V 3.1V = 0.4 V

And the bootstrap capacitor is: www.irf.com And the bootstrap capacitor is:
CBOOT 290 nC = 725 nF 0. 4 V

NOTES:

Notes:
www.irf.com

1. Here above VCC has been chosen to be 15V. Some IGBTs may require higher supply to properly work with the bootstrap technique. Also Vcc variations must be accounted in

To minimize the risk of undervoltage, bootstrap capacitor should be sized according to the ILOAD<0 case.

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d. off Bootstrap capacitor sizing. When the IGBT is turned the Vs Diode node is pushed up by the load current until The diode must have a BV > DC+ and a fast recovery time (trr < 100 ns) to minimize the amou the high side freewheeling diode get forwarded biased of charge fed back from the bootstrap capacitor to VCC supply.

Using Monolithic High Voltage Gate Drivers GATE RESISTANCES

VBS = VCC VF

 ILOAD = 0; the IGBT is not loaded while being on and VCE can be neglected

In this case we have the highest value for VBS. Turning on the high side IGBT, ILOAD flows into it is initially charged. The choice of bootstrap resistor is strictly and V S is pulled up. I C related to VBS time-constant. The minimum on time for chargthe risk of undervoltage, capacitor should be sized according to the ingTo theminimize bootstrap capacitor or for refreshing its bootstrap charge must I LOAD<0 case. V be verified against this time-constant.
C RES GE 1 GE 2 GC

The switching speed of the output transistor can be controlled by properly size the resisto controlling the turn-on and turn-off gate current. The following section provides some basic rule 0; the load current flows through the freewheeling ILOAD > b.  Bootstrap Resistor Qgc and diode Q indicate the gate to collector and gate to emitter for sizing the resistors to ge obtain the desired switching time and speed by introducing th equivalent output resistance of the gate driver (RDRp and RDRn respectively of p and n channel). charge respectively. VBS = VCC VF + VFP The examples always use IGBT power transistor. Figure 2 shows the nomenclature used in th A resistor (Rboot) is placed in series with bootstrap diode (see Sizing the turn-on resistor indicates the plateau voltage, Qgc and Qge indicate the ga following paragraphs. In addition, Vge* gate to collector and gate to emitter charge respectively. figure 1) so to limit the current when the bootstrap capacitor

b. Bootstrap Resistor t ,Q t ,Q c. Capacitor A Bootstrap resistor (R boot) is placed in series with bootstrap diode (see figure 1) so to limit the current when V the bootstrap capacitor is initially charged. The choice of bootstrap resistor isdV/dt strictly related to time-constant. The minimum on time for charging the bootstrap capacitor or for refreshing its V BS For high THON designs where is used an electrolytic tank caI charge must be verified against this time-constant. 90% pacitor, its ESR must be considered. This parasitic resistance C V V * forms voltage divider with Rboot generating a voltage step on c. aBootstrap Capacitor at the first of bootstrap capacitor. Theelectrolytic voltage steptank capacitor, its ESR must be considered. VBSFor where is used an high Tcharge HON designs 10% 10% step on VBS at the This parasitic resistance voltage with Rboot generating a voltage and the related speed (dVBS/dt)forms shoulda be limited.divider As a general first charge of bootstrap capacitor. The voltage step and the related speed (dV BS/dt) should be rule, ESR should meet the following constraint: limited. As a general rule, ESR should meet the following constraint:
CE C RES
ge

CRESon

GE

CRESoff

t,Q

tSW

ESR VCC 3 V ESR + RBOOT

tDon

tR

Figure 2: Nomenclature

Sizing the turn-on gate resistor

Parallel combination of small ceramic and large electrolytic Gate resitances may be chosen in order to fix either the switching-time or the output voltage slope. Hereafter presented both the methods. capacitors is normally the best compromise, the first acting as are Gate resitances may be chosen in order 4 to fix either the www.irf.com fast charge tank for the gate charge only and limiting the dVBS/ switching-time or the output voltage slope. Hereafter are preSwitching-time dt by reducing the equivalent resistance, while the second sented both the methods. keeps the VBS voltage drop inside the desired V . the matters of the calculation included hereafter, the switching time tsw is defined as the tim For BS spent to reach theSwitching-time end of the plateau voltage (a total Qgc + Qge has been provided to the IGB d. Bootstrap Diode For the matters of the calculation included hereafter, the www.irf.com The diode must have a BV > DC+ and a fast recovery time switching time tsw is defined as the time spent to reach the (trr < 100 ns) to minimize the amount of charge fed back from end of the plateau voltage (a total Qgc + Qge has been proUsing mono vided to the IGBT gate). To obtain the desired switching time the bootstrap capacitor to VCC supply. the gate resistance can the be sized starting from Qge and Qgc, gate). To obtain desired switching time the gate resistanc * Vcc, Vge* figure GATE RESISTANCES Vcc, Vge 3): (see figure 3): Qgc, (see The switching speed of the output transistor can be controlled by properly size the resistors controlling the turn-on and turn-off gate current. The following section provides some basic rules for sizing the resistors to obtain the desired switching time and speed by introducing the equivalent output resistance of the gate driver (RDRp and RDRn respectively of p and n channel). The examples always use IGBT power transistor. Figure 2 shows the nomenclature used in the following paragraphs. In addition, Vge* indicates the plateau voltage,

I avg =

Qgc + Qge t sw
* Vcc Vge

and
RTOT =

Iavg

where RTOT = R DRp + RGon , RGon = gate on-resistor and RD (from the gate driver datasheet)

For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 884 311, or visit us at www.irf.com

Vcc/Vb RDRp

Iavg CRES

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+ Qge

Using monolithic high voltage gate drivers

Using monolithic high voltage gate drivers

gate). To obtain the desired switching time the gate resistance can be sized starting from Qge and DT04-4 Qgc, Vcc, Vge* (see figure 3): Using Monolithic High Gate Drivers gate). To obtain the Voltage desired switching time the gate resistance can be sized starting from Qge and * Using monolithic high voltage gate , V Qgc, Vcc * ge (see figure 3): Qgc + Qge Vcc Vge I avg = Iavg t sw Qge gc + where Q TOT DRp Gon R = R + R , RGon = gatethe on-resistor and gate external events. Sizing turn-off resistor I = avg and RGon RGon = gate on-resistor and (from RDRp the = driver equivalent t sw RDRp = ,driver equivalent on-resistance gate driver In on-resistance this case, dV/dt of the output node induces a parasitic TOT = R DRp + and when the the IGBT in off The worst case in sizing current the turn-off resistor datasheet) through CRESoffR flowing RGoff andcollector RDRn (seeof figure gate driver datasheet) Goff is in * Vcc Vge forced to commutate by external events. 4)1. RTOT = Using monolith * Using monolith flowing In this case, dV/dt of the output nodedrop induces a parasitic through CRESoff Vge VccIavg If the voltage at the gate exceedscurrent the threshold voltage Iavg 1 Vcc/Vb RTOT = (see figure 4) . and R DRn Iavg= R of the IGBT, device may self turn on causing large oscillaRGon = gate on-resistor and RDRp = the driver equivalent on-resistance where RTOT DRp + RGon ,C IfRES the voltage drop at the gate exceeds the threshold voltage of the IGBT, the device may Sizing the turn-off gate resistor Sizing the turn-off gate resistor tion and relevant relevant cross conduction. RTOT = driver R DRp + RGon , R = gate on-resistor and Rand driver equivalent on-resistance where (from the gate datasheet) Goncausing DRp = on large oscillation cross conduction. RDRp (from the gate driver datasheet) is when when the the co co Theworst worstcase casein insizing sizingthe theturn-off turn-off resistor resistor R R Goff is The Goff forced to commutate by external events. I avg forced to commutate by external events. Vcc/Vb Inthis thiscase, case,dV/dt dV/dt of of the the output output node node induces induces a parasitic parasitic curren curren dV/dt In a I avg HS Turning ON RGon Vcc/Vb CRES 11. (see figure 4) and R DRn and RDRn (see figure 4) . CRES IfIfthe thevoltage voltagedrop dropat atthe the gateexceeds exceedsthe thethreshold thresholdvoltage voltage of of th th Cgate RESoff RDRp oncausing causinglarge largeoscillation oscillationand andrelevant relevantcross crossconduction. conduction. COM/Vs on RDRp RGoff
t sw

Figure 3: RGon sizing

eports the gate resistance size for two commonly used IGBTs (calculation made using C RESoff C RESoff COM/Vs atasheet values and assuming Vcc=15V). Figure 4: RGoff sizing: current path when Low Side is off and COM/Vs Table 1 reports the gate resistance size for two commonly R Goff R Goff High Side turns on oltage slope sizing: current path when Low Side is off and High Side turns Figure3: 4:R R OFF on used IGBTs (calculation made using typical datasheet values Goff sizing Figure OFF Gon ON sizing Figure 3: R ON Gon C R IES and assuming Vcc=15V). C DRn R IES DRn can1be sized to control output slope (dV /dt). gate resistor RGon Hereafter isfor described how to size the turn-off resistor when the output dV/dt is caused OUT Table reports the gate resistance size two commonly used IGBTs (calculation made using Hereafter is described how tomade size the turn-off resistor when Table 1 reports the gate resistance size for two commonly used IGBTs (calculation using e output voltage has a non-linear behaviour, the maximum output slope can be companion IGBT turning-on (as shown in figure 4). typical datasheet values and assuming Vcc=15V). the output dV/dt is caused by the companion IGBT turning-on Output voltage slope typical datasheet values and assuming Vcc=15V). ated by: Other dV/dt cases may be present and must be taken into account. As an example, th (as shown in figure 4). frequency spikes). generated by long motor cable coupling (high Output voltage slope sizing:current current path wheninto LowSide Side is is off off Figure 4: R Goffsizing: path when Low Figure R Output slope Goff Iavg Other dV/dt cases may be present and must be taken Turn-on voltage gate resistor RGon can be sized control output For this to reason the off-resistance must be 4: properly sized according to the application wors account. As OUT an example, the dV/dt by long motor slope (dVOUTgate /dt). resistor RGon can be sized to control output CRESoff slope (dV /dt). Turn-on Hereafter is described described how togenerated size the the turn-off turn-off resistor when when the th Hereafter is how to size resistor can The be sized to control output slope (dV /dt). Turn-on gate resistor RGon OUT following equation the IGBT gate threshold voltage to the collector dV/dt: cable coupling (high frequency spikes). While the output voltage has a non-linear behaviour, the relates While the output voltage has a non-linear behaviour, the maximum output slope can be companion IGBT turning-on (as shown in figure 4). companion IGBT turning-on (as shown in figure 4). While the output voltage has a non-linear behaviour, the maximum output slope can be the expression yielding Iavg and approximated by:rearranging: Other dV/dt cases may be be present present and must beactaken into into acc acc For this reason the off-resistance must be properly sized maximum output slope can be approximated by: Other dV/dt cases may and must be taken approximated by: dV generated by long motor cable coupling (high frequency spikes). out generated by long motor cable coupling (high frequency spikes). cording to the application worst case. Vth (RGoff + RDRn ) I = (RGoff + RDRn ) CRESoff * Forthis thisreason reasonthe theoff-resistance off-resistance mustbe beproperly properlysized sized accordin accordin dt For must dVout Vcc Vge avg II dV avg out = = dt CRESoff dV The following equation relates the IGBT gate threshold volt- voltage to dt C RESoff CRESoff out The following equation relates theIGBT IGBT gatethreshold threshold following equation relates the gate voltage to Rearranging the equation The yields: dt age to the collector dV/dt: and rearranging: inserting the expression yielding Iavg and rearranging: inserting the expression yielding inserting the expression yielding IavgIavg and rearranging: dV dV out Vthout/dt=5V/nsV out two ample, table 2 shows the sizing of gate resistance to get dV (using (R V R R R C (R + +R )) I I==(R R C th Goff + DRn Goff + DRn)) RESoff RGoff RDRnwhen th Goff DRn Goff DRn RESoff dt dt dV GBTs, typical datasheet values and * * assuming Vcc=15V. Vcc V CRESoff Vcc V ge ge = RTOT = dt TOT dV dV Rearranging the equation yields: Rearranging the equation yields: out out Rearranging the equation yields: C C RESoff RESoff dt dt As an example, table 3 reports RGoff for two popular IGBT to withstand dVout/dt = 5V/ns. V V th th R R dV /dt=5V/ns R R Goff DRn Goff DRn when using two two As an the sizing ofof gate resistance to get when using an example, example,table table22shows shows the sizing gate resistance to get dV out dV intended out/dt=5V/ns dV NOTES: The above-described equations are to be an approximated way for t C As an example, table 2 shows the sizing of gate resistance C RESoff popular values and assuming Vcc=15V . . RESoff popular IGBTs, IGBTs,typical typicaldatasheet datasheet values and assuming Vcc=15V dt take into account more precise device m dt resistances sizing. More accurate sizing may to get dVout/dt=5V/ns when using two popular IGBTs, typical om 6 the PCB and power section layout and and parasitic component dependent on Asan an example, table 3 reports RGoff for two IGBT to datasheet values and assuming Vcc=15V. forpopular twopopular popular IGBT to to withs withs As an example, table 3reports reports R two IGBT As example, table 3 R Gofffor Goff connections. withstand dV /dt = 5V/ns. out Another way to size the gate resistors is following power dissipation constraints. This wa NOTES: The The above-described above-described equations equations are are intended intended to to be be an an NOTES: Sizing the turn-off gate resistor investigated here. resistances sizing. More accurate sizing may take into account resistances sizing. More accurate sizing may take into account NOTES: The above-described equations are intended to be and parasitic parasitic component component dependent dependent on on the the PCB PCB and and pow pow and The worst case in sizing the turn-off resistor RGoff is when an approximated way for the gate resistances www.irf.com 6 6 sizing. More connections. connections. www.irf.com the collector of the IGBT in off state is forced to commutate by accurate sizing take into account more is precise device Another waymay tosize size the gate resistors is following following power dissipa dissipa Another way to the gate resistors power 1 investigatedhere. here. investigated

RGon

RGon

ON

OFF RDRn CIES

HSTurning TurningON ON HS

This is true under the assumption that gate voltage remains fixed during dV/dt. The resu is884 at 311, least two of magnitude greater than C reasonable whenever CIES RES), For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 or visit usorder at www.irf.com DT04-04
www.irf.com
11

This Thisis istrue trueunder under the theassumption assumptionthat thatgate gatevoltage voltageremains remains fixe fixe

DT04-4 revA
Using Monolithic High Voltage Gate Drivers Using monolithic high voltage gate drivers

Table 1: tsw driven RGon sizing (for RDRp = 7 )

IGBT IRGP30B120K(D) IRG4PH30K(D) Qge 19nC 10nC Qgc 82nC 20nC Vge* 9V 9V tsw 400ns 200ns Iavg 0.25A 0.15A Rtot 24 40 RGon std commercial value RTOT - RDRp = 17 18 RTOT - RDRp = 33 Tsw 420ns 200ns

Table 2: dVOUT/dt driven RGon sizing (for RDRp = 7 )

IGBT IRGP30B120K(D) IRG4PH30K(D) Qge 19nC 10nc Qgc 82nC 20nC Vge* 9V 9V CRESoff 85pF 14pF Rtot 14 85 RGon std commercial value RTOT - RDRp = 7 8.2 RTOT - RDRp = 78 82 dVout/dt 4.5V/ns 5V/ns

Table 3: RGoff sizing

IGBT IRGP30B120K(D) IRG4PH30K(D) Vth(min)Using CRESoff RGoffhigh monolithic 4 3 85pF 14pF RGoff 4 RGoff 35

DT04-4 revA

voltage gate drivers

ble 1: tsw driven RGon sizing (for RDRp = EFFECTS 7 ) PARASITIC ELEMENT

GBT

Another way to size the gate resistors is following power variations, induced by a fast current change, may influence L R DC+ (high voltage supply) dissipation constraints. This way not investigated here. the gate driver performances. ble 2: dVOUT/dt driven RGon sizing (for Ris DRp = 7 ) In presence high and low power signals both referenced GBT Qge Qgc Vge* CRESoff Rtot RGon std commercial value ofdVout/dt 1 This is true under the assumption that gate voltage remains to the same ground, it is important to avoid ground loops on Q GP30B120K(D) 19nC 82nC 9V 85pF 14 RTOT - RDRp = 7 8.2 D V 4.5V/ns result14pF is reasonable is= 78 board planes G4PH30K(D) fixed during 10nc dV/dt. 20nC The 9V V 85whenever RTOT -CIES RDRp or 82 ground 5V/ns close to the switching portions of the at least two order of magnitude greater than CRES). board. This solution reduces the noise coupled to the local high side V L ble 3: RGoff sizing driver ground of the driver. Moreover it is suggested to make star C low V LOAD GBT Vth(min) ELEMENT CRESoff RGoff PARASITIC EFFECTSvoltage connections between ground pins and board ground for all supply GP30B120K(D) 4 85pF RGoff 4 V gate drivers (see layout tips). L low side G4PH30K(D) 3 14pF RGoff 35 driver In figure 5 a single-phase motor drive power stage and its DT04-4 revA ARASITIC ELEMENT EFFECTS driver is shown. Some of the characteristics of the driver and COM below Ground (Vss-COM) GATE DRIVER Q V D Using monolithic high voltage gate drivers the power stage will drive be analyzed. properly the powfigure 5 a single-phase motor power To stage and drive its driver is shown. Some of the COM aracteristics of the driver and the power stage will be analyzed. Low side IGBT is considered to explain COM below Vss L R event. Figure 6 shows one of the possible configurations of COM below Ground (Vss-COM) L R DC+ (high voltage supply) the parasitic elements in the half bridge GND Low side IGBT is considered to explain COM below Vss configuration event. Figure 6 (here shows one of the
DC+ DC+ H H FDH
S CC

GP30B120K(D) 19nC 82nC 9V 400ns 0.25A 24 RTOT - RDRp = 17 18 In 420ns operation mode the fast voltage power section layout and related connections. parasitic elements. normal characteristics of the driver and the power stage will be analyzed. G4PH30K(D) 10nC 20nC 9V 200ns 0.15A RTOT - RDRp = 33 40 200ns

Qge and Qgc Vge* tsw dependent Iavg Rtot Tsw RGon std modelling parasitic component on the PCB and ercommercial stage it is value very important to know the effects of inductive In figure 5 a single-phase motor drive power stage and its driver is shown. Some of the

VCC

OUT

SS

FDL

DC+

DC+

DC-

DC-

possible configurations of the parasitic elements Figure 5: Parasitic elements in the sense shunt is power included stage for completeness).
QH DH VFDH
S

in the half bridge configuration (here emitter

To properly drive the power stage it is V very important to know the effects of inductive parasitic elements. In normal operation voltage variations, induced by a fast current change, high side the fast L V mode driver may influence the low gate driver performances. C V LOAD voltage In presence of high and low power signals both referenced to the same ground, it is important to V supply avoid ground loops on boardV or ground planes close to the switching portions of the board. This L R low side to the local ground of the driver. Moreover C solution reduces the noise coupled it is suggested to driver make star connections between ground pins and board ground for all gate drivers (see layout V COM GATE DRIVER tips). Q V D
CC

VOUT LL ILOAD

VCC

OUT

CC

SS

GOFF

VCC

VG VE

QL

DL

VFDL

ON

SS

FDL

GATE DRIVER

COM

RSENSE GND

LDCGND

RDC-

LDC-

RDC-

Figure 5: Parasitic elements in the power stage

Figure 6: Parasitic elements during low-side turn-off

www.irf.com properly drive the power stage it is very important to know the arrow). effects ofthe inductive parasitic As power device turns off the current flowing 8 in the parasitic inductance (LDC-) changes rapidly and the induced pushes COM below ground. The amount ments. In normal operation mode the fast voltage variations, induced by a fast current change, For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 884 311, or visit us voltage at www.irf.com DT04-04of voltage flyback is governed by the well known law: y influence the gate driver performances. dI L presence of high and low power signals both referenced to the same to = LDC it is important . VL ground, dt board. This oid ground loops on board or ground planes close to the switching portions of the This equation relates COM undershoot (strictly dependent on inductance voltage) to the slope of ution reduces the noise coupled to the local ground of the driver. Moreover load current. it is suggested to
DC dc

Consider to turn off (dotted arrow) the low side IGBT when load current is flowing through it (bold

CVCC
ON

RGOFF

VG VE

QL

DL

VFDL

Using Monolithic High Voltage Gate Drivers

VSS

COM

GATE DRIVER

NOTES: IGBT short circuit desaturation easily generate high emitter sense shunt is included for completeness). collector dV/dt. IGBT gate is pulled above the local supply by Consider to turn off (dotted arrow) the low side IGBT when GND LDCR load current is flowing through it (bold arrow). As the power the DC-gate-collector stray capacitance. In some cases (usually when turn-on resistor is low) a fast device turns off the current flowing in the parasitic inductance Figure 6: Parasitic elements during low-side turn-off pro(LDC-) changes rapidly and the induced voltage pushes COM diode is needed between IGBT gate and local supply to DT04-4 revA tect the driver output (figure 8). below ground. Consider to turn off (dotted arrow) the low side IGBT when load current is flowing through it (bold Using monolithic high gate drivers As an alternative solution a zener clamp can be beThe amount of the voltage flyback is governed by the the current well ) voltage arrow). As power device turns off flowing in the parasitic inductance (L DC-placed changes rapidly and the induced voltage pushes COM below ground. The amount of voltage known law: flyback is governed by the well known law: DC+

RSENSE

VLdc = LDC

dI LDC dt

.
SH O
VE
TURNING OFF

This equation relates COM undershoot (strictly dependent on inductance voltage) to the slope of load current. This equation relates COM undershoot (strictly dependent DT04-4 revA For this first solution to turn off more softly the IGBT, by increasing the low side turn on inductancereason, voltage) the to the slope of loadis current. VOUT Using monolithic high voltage gate drivers off resistor (respecting the superior limit, see sizing the turn-off gate resistor section), to limit the For this reason, the first solution is to turn off more softly the dIL/dt. R CGC DC+ D IGBT, by increasing the low side turn off resistor (respecting VCC RGATE the superior limit, see sizing turn-off gate when resistor QL (ON) This solution may bethe not sufficient insection), presence of a phase-DC+ short circuit. VG /dt. of short circuits are usually broken turning off the low side to limit the dILkind These IGBT. Short circuit D D detection may react when current has exceeded several times the rated current for normal V This solution may be not sufficient when in presence of a E Vcc operation inducing VG phase-DC+ short circuit. faster current change at turn-off. V In that case the solution shown in figure 7 prevents COM pin to follow IGBT emitter filtering the These kind of short circuits are usually broken turning off under-Vss spike. R C D the low side IGBT. Short circuit detection may react when curV R (ON) desaturation Figure 8: Driver output protection in caseQ of IGBT rent has exceeded several times the rated current for normal V operation inducing faster current change at turn-off. As an alternative solution a zener clamp can be placed between IGBT gate and emitter. It should V Vcc In that case the solution shown in figure 7 prevents COM pin be sized accordingly to IGBT gate-emitterVabsolute maximum ratings. DT04-4 revA The advantage of the zener is both protect It the driver output, sinking the current generated by tween IGBT gate and to emitter. should be sized accordingly to to follow IGBT emitter filtering the under-Vss spike. the collector dV/dt, and to keep IGBT gate-emitter voltage under control. Using monolithic voltage gate IGBTdrivers gate-emitter absolute maximum ratings. RCOM should be taken into account when sizinghigh the turn-off This is particularly important DT04-4 during IGBTrevA turn-off after short circuit detection, while IGBT emitter Figure 8: Driver output protection in case of IGBT to DCstray , see figure 9). desaturation spikes under The VSS due DCadvantage of inductance the zener(L is both to protect the driver outUsing monolithic high voltage gate drivers As an alternative solution a zener clamp can be placed between IGBT gate and emitter. put, sinking the current generated by the collector dV/dt, and It should be sized accordingly to IGBT gate-emitter absolute maximum ratings. The advantage of the zener is both to protect the driver output, sinking the current generated by to keep IGBT gate-emitter voltage under control. DC+ the collector dV/dt, and to keep IGBT gate-emitter Desaturation voltage under control. C Vcc This isimportant particularly during IGBT turn-off after short This is particularly duringimportant IGBT turn-off after short circuit detection, while IGBT emitter and www.irf.com 9 (LDC, see figure 9). spikes under VSS due to DC- stray inductance DC+ recirculation during C circuit detection, while IGBT emitter spikes under VSS due to R turn-off C Vcc
ONp Pn

OUT

CC

ONp

Pn

GATE

GC

COM

Vcc

GOFF

COM

ON

CVcc

RGOFF
ON

Vss

COM
Vss COM

GATE DRIVER

RCOM
RCOM

Desaturationcoupling and DC+ recirculation during VCC turn-off

gate-collector

OUT DC+

Figure 7: CCOM and RCOM added

GATE DRIVER

CVCC
VCC
ON

gate-collector coupling

VOUT

VG

RCOM should be taken into account when sizing the turn-off resistance (that becomes RGOFF + VSS COM C RCOM). RGOFF + RCOM should be taken into account when sizing the turn-off resistance (that becomes GATE DRIVER sizingR establishes the time constant of COM pin that can be set to some hundred RCOM and CCOM resistance (that RGOFF + RCOM). ). becomes COM V COM of ns. hundred RCOM and CCOM sizing establishes the time constant of COM pin that can be set to some
VCC
ON

Figure 7: CCOM and RCOM added

VG

Figure 9: zener protection for IGBT gate-emitter NOTES: IGBT short circuit desaturation easily generate high collector dV/dt. IGBT gate is pulled NOTES: IGBT short circuit desaturation easily generate high collector dV/dt. IGBT gate is pulled above the local supply by the gate-collector stray capacitance. Figure 9: zener protection for IGBT gate-emitter above the local supply by the gate-collector stray capacitance. In some cases (usually when turn-on resistor is low) a fast diode is needed between IGBT gate In some cases (usually when turn-on resistor is low) a fast diode is needed between IGBT gate and local supply to protect the driver output (figure 8). and local supply to protect the driver output (figure 8). For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 884 311, or visit us at www.irf.com www.irf.com
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RCOM and CCOM sizing establishes the time constant of of ns. COM pin that can be set to some hundred of ns. C To avoid noise coupling to VCC size the rule COM << 1 as required GND C by the application. To avoid noise coupling to C VCC size the rule as size the rule COM << 1 as required by the application. To avoid noise coupling to VCC VCC CVCC GND required by the application.

SS

VE

GATE DRIVER

LDCLDC-

SH O

R T

TURNING OFF

RT

DG

DH

LDC- flyback
LDC- flyback

DN04-04

11

11

Using Monolithic High Voltage Gate Drivers

DC- stray inductance (LDC-, see figure 9). VS below Ground (Vs-COM/VSS)

DT04-4 revA

Using monolithic high voltage gate drivers Using monolithic DT04-4 revA DT04-4 revA Using monolithic hig

Using monolithic monolithic high high voltage voltage gate gate drivers drivers Using

DC+

DC+ DC+

A well known event that triggers Vs to go below Vss or COM high side V L I Using monolithic high voltage gate drivers driver DT04-4 revA VS below Ground (Vs-COM/VSS) is the biasing of the(Vs-COM/VSS) low side Sforward V below Ground high side V high V side V LOAD freewheeling diode. This usually happens when current driver driver A well well known known event that triggers Vs to go below Vss or COM is the forward biasing of the low side A event that triggers Vs to go below Vss or COM is the forward biasing of the low side I monolithic high voltage gate drivers V DT04-4 revA flows out of theUsing half-bridge towards the L freewheeling diode. diode. This This usually usually happens happens when when current current flows flows out out of of the the half-bridge half-bridge towards the VSS low side towards freewheeling the driver load. load. load. V V Using monolithic high voltage gate drivers In state Vs is clamped below Vss Vss of about: Insteady steady state Vs is clamped clamped below Vss of about: about: VSS low side VSS low side GATE DRIVER In steady state Vs is below of V below Ground (Vs-COM/VSS)
CC

DT04-4 revA V
S
H OUT

VS

VS
LH

CC

CC

LH

IH

IH

SS

VOUT VOUT
LL LL

LOA LOAD

SS

SS

IL

IL

QL

steady steady GATE DRIVER )below Vwell V VSS = VFDL triggers RSENSE +R R A known event that to go ((R V S SS = V FDL SENSE Vs + DC ) IILOAD LOAD Vss or COM is the forward biasing of the low side S DC d (Vs-COM/VSS) R freewheeling diode. This usually happens when current flows out of the half-bridge towards the
COM

driver DL VFDLdriver

GATE DRIVER

load. And below COM: below COM: And below COM: hat triggers Vs And to go below Vss or COM is the forward biasing of the low side In state Vs is clamped below Vss of about: Vsteady Ground (Vs-COM/VSS) S below This usually happens when current flows out of the half-bridge towards the
steady steady Swell known event that FDL triggers steady AS FDL below Vss of about: S SS FDL SENSE

LDC-

RDC-

SENSE

QL QL
COM COM

DFDL V DL V L

GND

under Vss 10: Elements causing s going to go below Vss or COM is theFigure forward biasing of theVlow side +Vs RDC GND ) I LOAD GND freewheeling diode. This usually happens when current flows out of the half-bridge towards the is positive positive flowing towards the load. load. Resistor between Vs and Vout where LOAD load. IIILOAD flowing towards the where is is positive flowing towards the load. where going under V Figure 10: Elements causing VsV LOAD COM: And below Figure 10: Elements causing s going unde ) maximum I LOAD and V Vss or COM can be found found in the the datasheet The voltage difference between Vss and ss or In steady state voltage Vs is clamped below Vss of about: L (RSENSE + RThe DC COM can be in datasheet maximum difference between V While the above mentioned solution may work in normal The maximum voltage difference between and VWhile or the above mentioned conditions. solution may work in normal operating conditions, it can be not s ss absolute maximum ratingsV and recommended operating looking for V VS S absolute maximum ratings and recommended operating conditions. looking for Resistor between Vs and Vout steady sufficient, as an example, when a short circuit between phase andas ground occurs while the highoperating conditions, it can be not sufficient, an example, Resistor between Vs and Vout COM can be found in the datasheet looking for V absolute steady COM = V V S S FDL ( ) V V = V R + R I side IGBT is on. Once the high side IGBT has been turned off, the high amount of current that S SS may appear FDL SENSE commutation, DC LOADjust before when short circuit between phase and ground occurs while Major issues during thea freewheeling diode the starts clamping, maximum ratings and recommended operating conditions. Major issues may appear during commutation, just before the freewheeling diode starts clamping, was flowing through it starts flowing through low-side freewheeling diode. While the above mentioned solution may work in normal operating -, LLL and and LH may act pushing In this this case the inductive parasitic elements shown in figure figure 10 (Ldc While the above mentioned solution may work normal operati the highside IGBT is on. Once the high side IGBT hasin been dc H Major issues may appear during commutation, just before -, L L )) may act pushing In case the inductive parasitic elements shown in 10 (L is positive flowing towards the load. where I dI LOAD sufficient, as an example, when a short circuit between phase and gro And below COM: FDL down Vs below below Vss even even more than than as above above mentioned for steady state condition. may even pull VB (the floating stagea supply) below ground by means of the The V high or sufficient, as an example, when short circuit between phase and g down Vs Vss more as for steady state condition. off, the high amount of current that was flowing through and COM can be found in the The maximum voltage difference between Vsmentioned the freewheeling diode starts clamping. side IGBT is on. Once the highdatasheet side IGBT has been turned off, the h ss turned dt The derivative terms of the following equation may be the highest contribute during commutation side IGBT is on. Once the high side IGBT has been turned off, the The derivative terms of the following equation may be the highest contribute commutation maximum ratings and recommended operating conditions. looking for V was flowing through it during starts flowing through the diode. low-side freewheeling d it starts flowing through the low-side freewheeling S absolute steady In this case the inductive parasitic elements shown in figure bootstrap was capacitor. This happens when: e flowing towards the load. transient: flowing through it starts flowing through the low-side freewheelin V COM = V transient: S FDL The high dI may even pull VB (the floating stage supply) (Ldc-Vss: ,Vss: LL and ) may down Vsfound belowin Vss even and Vssact or pushing COM can be the datasheet ge difference10 between Vs L For H dI may diode even starts pull VB (the floating stage supply) below The high For tran Major issues may appear during commutation, just before the freewheeling clamping, V V < Vhigh even pull VB (the floating stage supply) belo The te maximum more ratings and operating conditions. S SS CCdI dtLmay than as recommended above mentioned for steady state condition. dI -, and L ) may act pushing In this case the inductive parasitic elements shown in figure 10 (L is positive flowing towards the load. where I tran dI dI L H dc L H LOAD tran V dt L capacitor. H happens when: ) ground V V R R Lthe L L )COM Lbe = ((difference +R be +below bootstrap This by means of the bootstrap capacitor. This hap)) IImay ((L V V R L L V + found S derivative SS = FDL SENSE DC LV DC H The terms of the following equation down Vs below Vss even more than as above mentioned for state condition. V+ or can in the datasheet The maximum voltage between S SS FDL SENSE DC L DC L steady H s and ssbootstrap dt we dt capacitor. This happens It should be noted that are considering high frequencywhen: events, so that the bootstrap diode may pear during commutation, just before the freewheeling diode starts clamping, dt dt pens when: The derivative of the following equation may be the highest contribute during commutation absolute maximum ratings and recommended operating conditions. looking for VS terms highest contribute during commutation reasonably keep For COM: tran turned off. LL and LH) may act pushing ctive parasitic elements shown in figure 10 (Ldc-,transient: For COM: V VSS < VCC transient: S tran Vss: even more thanFor as above mentioned for steady condition. dIstate dIH VS the VSS < ICs Vis tran Lcommutation, H dI dI CC For Vss: tran Major issues may appear during just before freewheeling diode clamping, L Real damage for monolithic caused by starts the amount of current stolen from VB pin (via Cboot =be L L V COM V L LH = S FDL highest L contribute H during commutation V COM V of the following equation may the S FDL L -, L and L ) may act pushing In this case the inductive parasitic elements shown in figure 10 (L dt dt be placed between VS coupling with VS). In order to minimize this current a resistor (Rhigh It should be noted that we are considering frequency events, so th dc L dI H VS) can dI dt dt tran L be noted that H we are considering high frequency It should ( ) ( ) V V V R R I L L L = + + and Vout as shown in figure 11. It should be noted that we are considering high frequency events, so down Vs below Vss even more than as above mentioned for steady state condition. reasonably keep turned off. S SS FDL SENSE DC L DC L H dt dt events, soinductances that the bootstrap diode maythe reasonably keep reasonably keep turned off. The derivative terms of the following equation may be the highest contribute during commutation In order to reduce the slope of current flowing in the parasitic so to minimize In order to reduce the slope of current flowing Suggested in the parasitic inductances so to minimize the in the rangeconstraints of some values for RVS are For COM: terms, RGOFF can dI Lbe increased, dI H respecting Real damage for monolithic ICsOhms. is caused by the amount of current sto transient: turned off. previously discussed (RGOFF derivative GOFF can be increased, respecting previously discussed constraints (R terms, R GOFF ) ( ) L L L I (R SENSE + Rderivative + Vss: DC L DC L H coupling with VS). In order to minimize this current a resistor (RVS) c dI dI Real damage for monolithic ICs is caused by theamount amount of current For sizing section) . tran L H Real damage for monolithic ICs is caused by the dt sizing . V NOTES: and section) LH dt V COM = S FDL LL Vout as shown in figure 11. coupling with VS). In order to minimize this current a resistor (R dI dI in L series to the VB bootstrap resistor and must be with considered in sizing the VS 1. Rof dt dt stolen from Cboot coupling VS). In H pin (via VS works ) V Stran V SS = V FDL (R SENSE + R DC ) I L (L DC bootstrap Lcurrent L +and resistance Vout as shown in figure 11. L H *= R +R ). (R BOOT BOOT VS dI L For COM: dI ) can be Ohms. placed order to dt minimize this current resistor (RVSof dt in the range some Suggested values for R VS area Hto reduce the slope of current flowing in the LH 2. It is also important to notice that theto current developed across RVS during initial bootstrap DL LL In order parasitic inductances so minimize the For COM: between VS and Vout as shown in figure 11. dt derivative dt terms, R are in the range of some Ohms. Suggested values for R charge may be such that a relevant high side IGBT VS voltage is developed between the discussed constraints (RGOFF GOFF can be increased, respecting previously NOTES: dI dI emitter and the VS pin. This voltage may be brought to the high side output Suggested values for RVS are in the range of some Ohms. (usually HO) tran section) . L H sizing VS flowing COM Vparasitic LH so to minimize in series 1. RVS works through the HO-VS ESD protection diode.to the bootstrap resistor and must be FDL LL NOTES: he slope of current in = the inductances the dt dt *= R bootstrap resistance (Rto BOOT BOOT+RVS).resistor and must the bootstrap 1. RVS works in series OFF can be increased, respecting previously discussed constraints (RGOFF NOTES: 2. bootstrap It is also important to notice that the current developed across resistance (RBOOT*= R BOOT+RVS). In order to reduce the slope of current flowing in the parasitic inductances so to minimize the charge may be such that a relevant voltage is developed be In order to reduce the slope of current flowing in the para2. It is also important to notice that the current developed acro discussed constraints derivative terms, RGOFF can be increased, respecting previously emitter and the VS pin. This (R voltage GOFF may be brought to the hig charge may be such that aresistor relevant voltage 1. RVS works in series to the bootstrap and must is developed sitic inductances so. to minimize the derivative terms, RGOFF can through the HO-VS ESD protection diode. www.irf.com sizing section) 13 emitter and the VS pin. This voltage may be be considered in sizing the bootstrap resistance (RBOOT *= brought to the be increased, respecting previously discussed constraints through the HO-VS ESD protection diode. RBOOT+RVS). (R sizing section).
GOFF

clamped

V V V

COM COM = V V = = V V (R

LDCL

DC-

RDCR

RSENSE R

SENSE

DC-

Resistor between Vs and Vout

www.irf.com

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DN04-04

12 12

Using Monolithic High Voltage Gate Drivers

2. It is also important to notice that the current developed across RVS during initial bootstrap charge may be such that a relevant voltage is developed between the high side IGBT emitter and the VS pin. This voltage may be brought to the DT04-4 revA high side output (usually HO) through the HO-VS ESD protection diode. In this case it must be verified that IGBT gate Using(gate monolithic high voltage gate drivers doesnt turn on at bootstrap start-up resistor and gateemitter capacitance help to filter out this pulse). This may In this casecause it must be verified that IGBT gate doesnt turn on at bootstrap start-up (gate a short shoot-through at inverter output. resistor and gate-emitter capacitance help to filter out this pulse). This may cause a short shoot-through at inverter output. 3. RVS takes also part in turn-on (RGON +RVS) an turn-off resispart in turn-on (RGON +RVS) an turn-off resistor sizing (RGOFF+RVS) as shown 3. RVS takes also in figure 12.tor sizing (RGOFF+RVS) as shown in figure 12.
Rboot Dboot DC+

VCC
ON

VB

Cboot

RGON QH DH

OFF

VSS

VS

RVS

RGOFF

GATE DRIVER

VOUT

QH

DH

Figure 11: RVS connection

For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 884 311, or visit us at www.irf.com

DN04-04

DT04-4 revA
Using Monolithic High Voltage Gate Drivers
DC+

RBOOT

Dboot

RBOOT RBOOT RBOOT Dboot VCC Dboot CVCC

VCC VCC VB VSS VB VSS

Dboot
VB

DC+ DC+ Cboot DC+ RGOFF Cboot RGOFF RGOFF RGOFF QH QH

DC+ Using monolithic high voltage gate drivers D R Using monolithic high voltage gate drivers
BOOT boot

DT04-4 revA DT04-4 revA Using monolithic high voltage gate drivers
RBOOT RBOOT RBOOT Dboot VCC Dboot CVCC
VCC VCC VB VSS VB VSS VSS
ON ON

DT04-4 revA Using monolithic high voltage gate drivers

Dboot
VB

DC+

DC+ Cboot DC+

VB
OFF

DH

VB VS Cboot

Cboot

VCC

CVCC

VS Cboot

RGON

QH

DH

CVCC CVCC
VSS
OFF OFF

GATE DRIVER OFF VS

Cboot

QH DH DH VOUT

DH CVCC CVCC

VCC

CVCC

ON ON

GATE DRIVER VS

Cboot RGON RGON

RVS QH RVS

RGON RVSQH QH RVS

QH DH DH VOUT VOUT

DH

VS GATE DRIVER

VS DRIVER GATE

VSS VS GATE DRIVER GATE DRIVER

VOUT VOUT
OUT

VSS VS GATE DRIVER GATE DRIVER

RVS RVS

Figure 12: Gate turn-on and turn-off with RVS V

RVS RVS

VOUT VOUT

Figure 12: Gate turn-on and turn-off with RVS only the HV diode is used. Clamping diode for Vs Clamping diode for Vs Figure 12: Gate turn-on and turn-off with RVS The clamp Figure 12: Gate turn-on and turn-off with must RVS be connected to COM pin (just in some cases to Vss pin) according to device This information In the previous paragraph it has been supposed that D Clamping diode for Vs switched off datasheet. considering such In the previous paragraph it has been supposed that DBOOT keeps BOOT Clamping diode for Vs keeps switched offacting considering such events acting at high fre- can be usually found under the absolute maximum ratings. events at high frequency. Clamping diode for follows VOUT, switched VB can be to VCC by the Whenever thisVs assumption is not verified, whilethat VS D off tied considering such the previous paragraph it has been supposed quency. In BOOT keeps and V should be kept inside the absolute boostrap diode. In this case the difference between V events acting at high frequency. keeps switched off considering such In the previous paragraph it has been supposed that D B S BOOT Whenever this assumption is not verified, while VS follows PCB LAYOUT TIPS keeps V switched off considering such In theWhenever previous it has been supposed that DV maximum specification (see datasheet): be tied to V this assumption isIC not verified, while BOOT events acting atparagraph high frequency. S follows OUT, VB can CC by the VOUT , V can be tied to V by the boostrap diode. In this case B CC events acting at high frequency. and V should be kept inside the absolute boostrap diode. In this case the difference between V VB can be tied to VCC by the Whenever this assumption is not verified, while VS follows B VOUT, S theWhenever difference between V and V should be kept inside the Distance from high to low voltage follows V , V can be tied to V by the this assumption is not verified, while V maximum specification (see IC datasheet): S OUT B CC B S and V should be kept inside the absolute boostrap diode. In this case the difference between V VB VS < VVBS _ abs max B S boostrap diode. In this case the difference between VB and VS should be kept inside the absolute absolute maximum specification (see datasheet): maximum specification (see IC IC datasheet): maximum specification (see IC datasheet): minimize noise coupled between signals referred V VS <to VVBS B _ absin maxspecification, a clamp device To and VS as In order keep should be the positioned between VSS the VB Vshown to ground and those floating its strongly recommended to S < VVBS _ abs max in figure 13, where a zener diode and a 600V diode are placed. VB V < V S VBS _ abs max components tied to between floating voltage in the VShigh as voltage In order to keep in specification, a clamp deviceplace should be positioned VSS and Zener voltage must be a sized the rule: shown in figure 13, where a zener diode and a 600V diode are placed. and V as Inorder order keep in specification, afollowing clamp device should be V SS Scomponents In to to keep in specification, clamp device should be side of positioned device (VB, Vbetween side) while the other in the S In order to keep in where specification, a clamp device should be positioned between VSS and VS as shown in figure 13, a zener diode and a 600V diode are placed. positioned between VSS and VS as shown in figure 13, where a opposite side. shown in figure 13, where a zener andthe a 600V Zener voltage mustV be sized diode following rule: diode are placed. V V600V Z a VB _ abs max CC zener diode and diode are placed. Zener voltage must be sized following the rule: Zener voltage must be sized the rule: Ground plane Zener voltage must be sized following the rule: V V Vfollowing Z most VBof _ abs max CCthe use of a zener is not necessary, and only the HV diode is used. In the cases
floating to minimize noise coupling. datasheet. This information can be found voltage under the absolute maximum ratings. In most of the cases the use of a zener is usually not necessary, and only the side HV diode is used. In most of the cases the use of a zener is not necessary, and only the HV diode is used. The clamp must be connected to COM pin (just in some cases to Vss pin) according to device In most of the cases the use of a zener is not necessary, and datasheet. information can be usually found under the absolute maximum ratings. The clamp must This be connected to COM pin (just in some cases to Vss pin) according to device The clamp This mustinformation be connected pin (just under in some to Vss pin) according datasheet. can to beCOM usually found thecases absolute maximum ratings. to device datasheet. This information can be usually found under the absolute maximum ratings.

VZ VVB _ abs max VCC VZ In V V Ground plane must not placed under or VB _ abs max CC The clamp must bethe connected COM (just in some cases to Vss pin) according to nearby devicethe high most of the cases use of a to zener is pin not necessary, and only the HVbe diode is used.

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15 15 15 15

DN04-04

DT04-4 revA

Using Monolithic High Voltage Gate Drivers Using monolithic high voltage gate drivers
DC+

DT04-

RBOOT

Dboot

VCC
ON

VB

Cboot

VB/ VCC HOP/LOP HON/LON

Using monolithic high voltage a voltage across the gate-emitter increasing the possibility of self turn-on effect. For this reason is strongly recommended to place the gate resistances close together and to minimize the IGC loop area (see figure 14).
Routing and placement example
gate resistance

gate

CGC

CVCC
VSS or COM (see comments) VS

We consider, as example, the IR2214 a high voltage and high output current gate driver, seeGate the lead Drive assignments in figure Loop GATE DRIVER VGE 15. RVS Figure 16 shows one of the possible layout solutions using a VOUT VS/COM 3 layer PCB. This example takes into account all the previous considerations. Placement and routing for supply capacitors Figure 14: gate drive loop side minimize and gate resistances in the high and low voltage Figure 13: Clamping structure with zener diode respectively supply path and gate drive loop. The bootstrap diode is placed under the device to have the cathode as close Routing and placement example B LAYOUT TIPS as possible to bootstrap capacitor and the anode far from high Supply capacitors We consider, as example, high voltage and high output current gate driver voltagethe andIR2214 close to a VCC . ance from high to low voltage lead assignments in figure 15. If the output stages are able to quickly turn on IGBT with minimize the noise coupled between the signals referred to ground and those floating its high value of current, the supply must in bethe placed gly recommended to place components tied to capacitors floating voltage high as voltage side of HIN 1 DSH 24 while as the other components in the opposite side. ce (VB, VS side)close possible to the device pins (VCC and VSS for the ground VB LIN N.C. FLT_CLR tied supply, VB and VS for the floating supply) in order to miniund plane SY_FLT HOP mize parasitic inductance/resistance.
RGON
FAULT/SD VSS HON VS

QH

DH

SSOP24 Gate drive loops SSDL SSDH N.C. COM ply capacitors N.C. LON Current loops behave like an antenna able to receive and N.C. e output stages are able to quickly turn on IGBT with high value of current, the supply LOP EM noise. In order to to the reduce EM coupling and imN.C. VSS for the ground VCC citors must betransmit placed as close as possible device pins (VCC and VS for the in order to minimize parasitic inductance/resistance. supply, VB and prove 12 N.C. DSL 13 the floating power supply) switch turn on/off performances, gate drive loops must be reduced as much as possible. Figure 14 shows e drive loops the high and low side gate loops. Figure 15: IR2214 lead assignments ent loops behaveMoreover, like an antenna able tobe receive and transmit noise. order to reduce current can injected inside the EM gate drive In loop DT04-4 revA coupling and improve the power switch turn on/off performances, gate drive loops must be Figure 16 The shows via the IGBT collector-to-gate capacitance. par- one of the possible layout solutions using a 3 layer PCB. This exam ced as much as possible. Figure 14 shows the parasitic high and low side gate loops. into account all the previous considerations. Placement and routing for supply capac over, current asitic can be injected inside of the gate loop via high thetoIGBT collector-to-gate auto-inductance the gatedrive loop contributes develop Using monolithic voltage gate drivers gate resistances in the high and low voltage side minimize respectively supply path sitic capacitance. The parasitic auto-inductance of the gate loop contributes to develop a drive loop. The is placed under the device to have the cathode as ge across the gate-emitter increasing the possibility of self turn-on effect. For bootstrap this reason diode is gly recommended to place the gate resistances close together and toto minimize the loop area and the anode far from high voltage and close to VCC. possible bootstrap capacitor IGC
VB/ VCC HOP/LOP HON/LON
Gate Drive Loop gate resistance

nd plane must not be placed under or nearby the high voltage floating side to minimize noise ling.

figure 14).

CGC

irf.com

16
VGE

VS/COM

Figure 14: gate drive loop

DN04-04

For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 884 311, or visit us at www.irf.com uting and placement example

www.irf.com consider, as example, the IR2214 a high voltage and high output current gate driver, see the d assignments in figure 15.

DT04-4 revA
Using Monolithic High Voltage Gate Drivers
Using monolithic high voltage gate drivers

VGH

R2 R3 R4 IR2214

D2

DC+

VEH
D1
D3 C2

C1

VGL

R5 R6 R7

Phase

VCC VEL

R1

Figure 16(a): TOP

Figure 16(b): BOTTOM Referred to figure 16: Bootstrap section: R1, C1, D1 High side gate: R2, R3, R4 High side Desat: D2 Low side supply: C2 Low side gate: R5, R6, R7 Low side Desat: D3 Figure 16(c): Ground plane

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